HetNet Wireless Fronthaul - IEEE Communications Theory...

HetNet Wireless Fronthaul The Challenge Missed Gerhard P. Fettweis – Vodafone Chair Professor coordinator serial entrepreneur

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Announcing in partnership with

The Mission

• Understand and drive the holistic requirements and solutions of 5G

• Deliver technology breakthrough

• Be Opinion Leader in forming 5G

• Deliver lab examples and test beds

• Deliver business innovation through technology transfer and cooperation

• Simple one-stop shop for complex 5G research topics

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5G – “Massive” Requirements

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Sta

te o

f th

e ar

t

Massive throughput

Massive reduction in latency

Massive sensing

Massive resilience

Massive safety and security

Massive fractal heterogeneity

> 10Gbit/s per user < 1ms RTT > 10k sensors per cell < 10−8 outage < 10−12 security 10x10 heterogenity

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Mobile edge cloud

Dresden 5G Lab

5G Research on four Tracks

Wireless

Silicon systems

Tactile Internet applications

Grand opening Sept 2014 in Dresden

Team Members

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G. Fettweis Wireless

Communication

E. Jorswieck Information

Theory

F. Ellinger RFIC Design

L. Urbas Human-Machine-

Interfaces

C. Baier Formal

Methods

E. Altinsoy Audio & Haptic Engineering

W. Lehner Databases

W. Nagel Big Data and HPC

C. Fetzer Resilience and Safety

F. Fitzek Communication

and Storage

R. Schüffny SoC Integration

T. Strufe Privacy

and Security

K. Janschek Automation

H. Härtig Operating Systems

U. Aßmann Software

Engineering

D. Plettemeier RF Engineering

Members on Tracks

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Wireless track

Silicon systems track

Mobile edge cloud track

Tactile Internet application track

Gerhard Fettweis

Eduard Jorswieck

Frank Ellinger

Christel Baier

Rene Schüffny

Frank Fitzek

Leon Urbas

Christof Fetzer Uwe Aßmann

Wolfgang Lehner

Ercan Altinsoy Thorsten Strufe

Klaus Janschek

Dirk Plettemeier

Wolfgang Nagel

Hermann Härtig

Team of 500+ Researchers !!!

25 Relevant Startups Generated by Team

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Wireless track Silicon systems track Mobile edge cloud

track Tactile Internet

application track

freedelity

Live 5G GFDM PHY: NI @ Dresden 5G Lab

5/26/2014 Gerhard Fettweis

Connected industry partners

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Problem Statement:

Wireless Fronthaul

The System With Wireless Fronthaul

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terminal / Ue

Remote Radio Head

RRH

Wireless Fronthaul

Base Station

Radio Access High Rate

Wireless Fronthaul

Interim Summary Fronthaul Specification

Data rates of N x CPRI / ORI

i.e. N x 1.5 Gb/s

≥ 10 Gb/s required

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Latency minimized

Speed of light: 300m ↔ 1µs

Marginal latency due to signal

processing

0.1µs @ 10 Gb/s ↔ 1000 bits

Fronthaul: Low Latency Encoding

Acknowledging my student: Najeeb ul Hassan

Low-Density Parity-Check Code

Gerhard Fettweis Slide 19

A valid edge spreading should satisfy

�𝐁𝐁𝑖𝑖 = 𝐁𝐁𝑚𝑚𝑐𝑐𝑐𝑐

𝑖𝑖=0

𝑚𝑚𝑐𝑐𝑐𝑐 : memory of the convolutional code

Consider a sequence of 𝐿𝐿 = 6 code blocks of LDPC block code (LDPC-BC)

𝐯𝐯1 𝐯𝐯2 𝐯𝐯3 𝐯𝐯4 𝐯𝐯5 𝐯𝐯6

LDPC Convolutional code: use edge spreading

𝐁𝐁0 = 𝐁𝐁1 = 𝐁𝐁2 = 1, 1 , 𝑚𝑚𝑐𝑐𝑐𝑐 = 2

𝐁𝐁 = 3, 3

𝐯𝐯1 𝐯𝐯2 𝐯𝐯3 𝐯𝐯4 𝐯𝐯5 𝐯𝐯6

Independent transmission of blocks 𝐯𝐯1

Coupled transmission of consecutive blocks

Windowed Decoding


Window decoder of size 𝑊𝑊 operates on 𝑊𝑊 received blocks [𝐲𝐲𝑡𝑡 , 𝐲𝐲𝑡𝑡+1, 𝐲𝐲𝑡𝑡+2, … , 𝐲𝐲𝑡𝑡+𝑾𝑾−𝟏𝟏]

Structural latency: For a fixed code with rate 𝑅𝑅

𝑇𝑇WD = 𝑊𝑊 ∙ 𝑁𝑁𝑛𝑛𝑣𝑣 ⋅ 𝑅𝑅 [info. bits]

latency depends on 𝑊𝑊, but is independent of length of code 𝐿𝐿

… …

𝑊𝑊 𝑚𝑚𝑐𝑐𝑐𝑐

Decoded blocks Target blocks 𝐲𝐲𝑡𝑡−2 𝐲𝐲𝑡𝑡−1 𝐲𝐲𝑡𝑡 𝐲𝐲𝑡𝑡+1 𝐲𝐲𝑡𝑡+2 𝐲𝐲𝑡𝑡+3 𝐲𝐲𝑡𝑡+4

Example: • 𝑊𝑊 = 4

• Continuous decoding is possible

• Low storage requirements

𝑚𝑚cc 𝑊𝑊

𝐲𝐲 𝑡𝑡−𝑚𝑚cc

𝐲𝐲 𝑡𝑡

𝐲𝐲 𝑡𝑡−𝑊𝑊−1 𝐲𝐲𝑡𝑡−𝑊𝑊

𝐮𝐮�𝑡𝑡 BP Decoding decoded block

new input block

Schematic Diagram:

Comparison Result: LDPC-BC vs. LDPC-CC


• For Low latency, Convolutional Code with Viterbi decoder is favorable.

• LDPC-CC improves the range of LDPC-BC from medium to high latency

• 𝑊𝑊 can be varied to get a trade-off between latency and performance

Comparison of required 𝐸𝐸𝑏𝑏 𝑁𝑁0⁄ to achieve BER = 10−5 for LDPC-BCs and LDPC-CCs

at 𝐸𝐸𝑏𝑏/𝑁𝑁0 = 3dB: LDPC-BC = 410 bits LDPC-CC = 210 bits

Observations:

N. ul Hassan, M. Lentmaier, and G. Fettw eis, “Comparison of LDPC block and LDPC convolutional codes based on their decoding latency,” in (ISTC), 7th International Symposium on Turbo Codes and Iterative Information Processing, Aug. 2012, pp. 225–229.

Joint Access & Fronthaul Design

Acknowledging my student: Jens Bartelt

𝑑𝑑𝑑 𝑣𝑣 𝐶𝐶1 𝐻𝐻−1 𝐻𝐻 𝑥𝑥 𝑢𝑢

Uplink Approach - Overview

Jens Bartelt Slide 25

𝑄𝑄

𝑛𝑛1~𝒩𝒩(0,𝜎𝜎1)

𝑥𝑥𝑑 𝑦𝑦


𝑄𝑄−1 𝑦𝑦𝑑 𝑥𝑥𝑑𝑑 𝑀𝑀1 𝑀𝑀2 𝑀𝑀2−1 𝑣𝑣𝑑 𝑀𝑀1

−1 𝑢𝑢𝑑 UE RRH BBU RAN FH

𝐶𝐶2 𝐶𝐶2−1 𝐶𝐶1−1 𝑤𝑤 𝑤𝑤𝑑 𝑑𝑑

outer code

Inner code

joint encoding – reduced latency, simplified hardware

joint decoding – improved BER

Joint Encoding

Simple integration into standard:

• Additional channel increases BER

• BBU will select lower MCS for UE for UL grant Jens Bartelt & Gerhard Fettweis Slide 26

𝑑𝑑𝑑 𝑣𝑣 𝐶𝐶1 𝐻𝐻−1 𝐻𝐻 𝑥𝑥 𝑢𝑢 𝑄𝑄




𝑦𝑦𝑑 𝑀𝑀1 𝑀𝑀2 𝑀𝑀2−1 𝑣𝑣𝑑 𝑢𝑢𝑑

UE RRH BBU RAN FH 𝐶𝐶2 𝐶𝐶2−1 𝐶𝐶1−1 𝑤𝑤 𝑤𝑤𝑑 𝑑𝑑 𝑄𝑄−1 𝑥𝑥𝑑𝑑 𝑀𝑀1

−1

FER measurement

MCS selection

DCI information UL grant

𝑑𝑑𝑑 𝑣𝑣 𝐶𝐶1 𝐻𝐻−1 𝐻𝐻 𝑥𝑥 𝑢𝑢

Approach

Jens Bartelt & Gerhard Fettweis Slide 27

𝑄𝑄




SISODQ 𝑦𝑦𝑑 𝑀𝑀1 𝑀𝑀2 𝑀𝑀2−1 𝑣𝑣𝑑 𝑢𝑢𝑑

UE RRH BBU RAN BH 𝐶𝐶2 𝐶𝐶2−1 𝐶𝐶1−1 𝑤𝑤 𝑤𝑤𝑑 𝑑𝑑

011|0… 0

1 111 110 101 100 011 010 001 000

pr ob

0 1

01|10…

prob. x=1

0

1

𝑃𝑃 𝑢𝑢𝑘𝑘 = 0 𝑦𝑦′ = � 𝑃𝑃 𝑢𝑢𝑘𝑘 = 0 𝑣𝑣 = 𝑐𝑐𝑞𝑞 ⋅ 𝑃𝑃(𝑣𝑣 = 𝑐𝑐𝑞𝑞|𝑦𝑦′)2𝐵𝐵

𝑞𝑞=1

use soft information

LLRs LLRs

𝐿𝐿 𝑥𝑥 =𝑃𝑃(𝑥𝑥 = 0)

1− 𝑃𝑃(𝑥𝑥 = 0)

Performance vs. Conventional Dequantizer operating point for RAN:

𝑆𝑆𝑁𝑁𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅 = 10 𝑑𝑑𝑑𝑑 , 𝑀𝑀𝑅𝑅𝑅𝑅𝑅𝑅 = 4 , 𝑅𝑅𝑐𝑐𝑅𝑅𝑅𝑅𝑅𝑅 = 0.8

𝑑𝑑𝐸𝐸𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅 ≈ 10−4 for error-free BH

Jens Bartelt & Gerhard Fettweis Slide 28

Improved BER/throughput under imperfect fronthaul No additional fronthaul FEC – reduced latency Higher range/lower transmit energy

J. Bartelt, G. Fettweis, „A Soft-Input/Soft-Output Dequantizer for Cloud-Based Mobile Networks”,15th IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC 2014) (IEEE SPAWC 2014), Toronto, Canada, June 2014.

The Analog/Digital Conversion

Acknowledging my student: Lukas Landau

Power Bottleneck: Conversion


baseband DAC RF PA

baseband ADC RF LNA

Time Versus Amplitude Processing


time

amplitude amplitude

The Challenges Ahead: Paradigm Shift?

Amplitude resolution ADC Interface:

• ADC 3-bit, 30GHz sampling rate

500mW best in class (Frank Ellinger, TU Dresden)

240 G res /s = 2nJ/res

Time resolution ADC

• 1-bit, 240GHz sampling rate

10mW (estimate) by processing in time (Bogdan Staszewski, TU Delft)

240 G res /s = 40pJ/res


Multilevel Modulation With 1-Bit Oversampling

TU Dresden Slide 35

1. No ISI Ambiguities likely occure

2. Symbol-by-Symbol Detection ISI can be used as an advanced dithering signal

3. Sequence Estimation Linear combinations of different signals can be exploited

What is the optimal filter design in terms of information rate?

Optimal Intersymbol Interference Design

TU Dresden Slide 36

5-fold oversampling M=5 max. symbol overlap L=2 16-QAM Communications

Summary: • Intersymbol-interference can be exploited • Sequence estimation improves performance

Achievable Rate for Different Receiver Designs

Lukas Landau Slide 37

-10 -5 0 5 10 15 20 25 300

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4

SNR / [dB]

achi

evab

le ra

te /

[bpc

u]

UnquantizedM=3M=3, Symbol-by-SymbolM=2M=2, Symbol-by-SymbolM=1

M=3

M=2

The optimal receiver exploits the inherent channel memory

The symbol-by-symbol detection benefits from complexity relaxation

Significant advantage provided by oversampling

16 QAM

Lab Demonstrator Setup


Millimeter Wave Radio Links Demonstrator @ TU Dresden

60GHz Demonstrator at TU Dresden 2x 5Gbps @ 2.5m distance (polariz. diversity)

hybrid frontend (GaAs)

Digital baseband hardware

60GHz link

Hardware Modules 60GHz Digital Baseband: 5Gbps Implementation

1-bit ADC (2x)

1-bit DAC (2x)

Implemented on 65nm-CMOS FPGAs: ALTERA Stratix III / II-GX Power consumption estimates by projection to 65nm std.-cell ASIC [18] [18] I. Kuon and J. Rose, “Measuring the Gap Between FPGAs and ASICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, 2007.

60% (30mW of 50mW)

70% (210mW of 300mW)

Power Over Ethernet Possible? Overall Power Budget @ 28nm CMOS / SiGe

Transmit mode / polarization: Controller module: 50mW 25mW 60GHz analog frontend: 150mW 150mW 60GHz digital baseband: 50mW 25mW Power Amplifier: 1500mW 750mW

1750mW 950mW

Receive mode / polarization: Controller module: 50mW 25mW 60GHz analog frontend: 150mW 150mW 60GHz digital baseband: 300mW 100mW LNA module : 500mW 300mW

1000mW 575mW

Tx Rx

1000mW

500mW

1750mW

1500mW

Power Over Ethernet Possible !!

Achieving Fronthaul Data Rates

DFG SFB 912 www.tu-dresden.de/sfb912 (German Science Foundation Collaborative Research Center) In operations since July-1, 2011 Gerhard P. Fettweis (coordinator) Wolfgang Lehner (vice coordinator) Wolfgang Nagel (vice coordinator)

Highly Adaptive Energy-Efficient Computing

http://www.tu-dresden.de/sfb912

Highly Adaptive Energy-Efficient Computing Inter-Chip Communications

Gerhard Fettweis Slide 45 5/26/2014

Radio Interconnect

• on-chip/on-package antenna arrays • analog/digital beamsteering and

interference minimization • 100Gb/s • 220GHz carrier / 25GHz channel • 3D routing & flow management

Optical Interconnect

• adaptive analog/digital circuits for e/o transceiver

• embedded polymer waveguide • packaging technologies

(e.g. 3D stacking of Si/III-V hybrids) • 90° coupling of laser

Board-to-Board Channel Characterization

TU Dresden Slide 46

Board_1 Board_2

Multipath component

Line of Sight component

• Multipath propagation (?) • Pathloss exponent

→ Initial investigations using a copper board measurement setup as the worst-case scenario

Network Analyzer

220 – 245 GHz

Horn-antennas Copper boards

Channel Impulse Response (Direct Link): Copper Boards versus Freespace


Copper boards induce additional multipath reflections of less than -20dB as compared to the LOS component → frequency flat channel

Where to Find The Spectrum For 1Tb/s?


100 GHz

Jonathan Well, „ Faster Than Fiber: The Future of Multi-Gb/s Wireless,“ IEEE Mirrowave Magazine, May 2009, pp. 104-112

220 GHz

100 GHz

Conclusions

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Wireless Fronthaul Is Possible

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Data Rate Latency

Power Consumption Realization (mmW)

Thank you!

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Dresden 5G Lab

Coordinator: Gerhard Fettweis dresden5GLab.org [email protected]

http://www.dresden5glab.org/

Thanks to Vodafone for 19 years of continued support !

www.vodafone-chair.org

http://www.youtube.com/watch?v=_VXEPzQgpok cfaed.tu-dresden.de

www.tu-dresden.de/sfb912

www.twinlab3d.org

HetNet Wireless Fronthaul - IEEE Communications Theory...

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