DOI: 10.1126/science.1132394, 1754 (2006);314 Science

et al.Jong-Hyun AhnSemiconductor NanomaterialsHeterogeneous Three-Dimensional Electronics by Use of Printed

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9. M. Schwarzschild, R. Härm, Astrophys. J. 150, 961 (1967).10. R. H. Sanders, Astrophys. J. 150, 971 (1967).11. M. Busso, R. Gallino, G. J. Wasserburg, Annu. Rev. Astron.

Astrophys. 37, 239 (1999).12. O. Straniero et al., Astrophys. J. 440, L85 (1995).13. J. W. Truran, I. Iben Jr., Astrophys. J. 216, 797

(1977).14. H. Beer, R. L. Macklin, Astrophys. J. 339, 962 (1989).15. C. Abia et al., Astrophys. J. 559, 1117 (2001).16. D. L. Lambert et al., Astrophys. J. 450, 302 (1995).17. J. Tomkin, D. L. Lambert, Astrophys. J. 523, 234 (1999).18. A. Banerjee, D. Das, V. Natarajan, Europhys. Lett. 65,

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(1998).20. P. S. Chen, R. Szczerba, S. Kwok, K. Volk, Astron.

Astrophys. 368, 1006 (2001).

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22. P. Ventura et al., Astrophys. J. 550, L65 (2001).23. C. M. O’D. Alexander, Philos. Trans. R. Soc. London Ser. A

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(2005).25. K. D. McKeegan, A. M. Davis, in Meteorites, Planets, and

Comets, A. Davis, Ed., vol. 1 of Treatise on Geochemistry(Elsevier-Pergamon, Oxford, 2003), pp. 431–460.

26. F. A. Podosek et al., Geochim. Cosmochim. Acta 55,1083 (1991).

27. Supported by the Spanish Ministerio de Educación yCiencia (MEC) grants AYA 2004-3136 and AYA 2003-

9499 (A.M. and P.G.L.) and a MEC JdC grant (J.M.T.R.).This work is based on observations obtained at the4.2-m William Herschel Telescope, operated on theisland of La Palma by the Isaac Newton Group in theObservatorio del Roque de Los Muchachos of theInstituto de Astrofisica de Canarias, and on observationsobtained with the 3.6-m telescope at ESO–La SillaObservatory (Chile).

Supporting Online Materialwww.sciencemag.org/cgi/content/full/1133706/DC1Fig. S1

10 August 2006; accepted 19 October 2006Published online 9 November 2006;10.1126/science.1133706Include this information when citing this paper.

Heterogeneous Three-DimensionalElectronics by Use of PrintedSemiconductor NanomaterialsJong-Hyun Ahn,1,2,3 Hoon-Sik Kim,5 Keon Jae Lee,1,3 Seokwoo Jeon,1,2,3 Seong Jun Kang,1,2,3Yugang Sun,1,2,3 Ralph G. Nuzzo,1,2,3,4 John A. Rogers1,2,3,4,5*

We developed a simple approach to combine broad classes of dissimilar materials intoheterogeneously integrated electronic systems with two- or three-dimensional layouts. The processbegins with the synthesis of different semiconductor nanomaterials, such as single-walled carbonnanotubes and single-crystal micro- and nanoscale wires and ribbons of gallium nitride, silicon,and gallium arsenide on separate substrates. Repeated application of an additive, transfer printingprocess that uses soft stamps with these substrates as donors, followed by device and interconnectformation, yields high-performance heterogeneously integrated electronics that incorporate anycombination of semiconductor nanomaterials on rigid or flexible device substrates. This versatilemethodology can produce a wide range of unusual electronic systems that would be impossible toachieve with other techniques.

Many existing and emerging electronicdevices benefit from the heteroge-neous integration of dissimilar classes

of semiconductors into single systems, in eithertwo-dimensional (2D) or 3D layouts (1, 2). Ex-amples include multifunctional radio-frequencycommunication devices, infrared imaging cam-eras, addressable sensor arrays, and hybrid sili-con complementary metal oxide semiconductor(CMOS) circuits and nanowire devices (3–7).In some representative systems, compound semi-conductors or other materials provide high-speedoperation, efficient photodetection, or sensingcapabilities; the silicon CMOS provides digitalreadout and signal processing in circuits that of-ten involve stacked 3D configurations.Wafer- or

chip-scale bonding (1, 2, 6, 8–10) and epitaxialgrowth (3, 11, 12) represent the two most widelyused methods for achieving these types ofintegrated systems.

The bonding processes use fusion processes(8, 9) or layers of adhesives (6, 10) to combineintegrated circuits, photodiodes, or sensorsformed separately on different semiconductorwafers. This approach works well in manycases, but it has important drawbacks (1, 9),including (i) limited ability to scale to largeareas (i.e., larger than the wafers) or to morethan a few layers in the third (i.e., stacking)dimension; (ii) incompatibility with unusualmaterials (such as nanostructured materials)and/or low-temperature materials and substrates;(iii) challenging fabrication and alignment forthe through-wafer electrical interconnects; (iv)demanding requirements for planar bondingsurfaces; and (v) bowing and cracking that canoccur from mechanical strains generated bydifferential thermal expansion and contractionof disparate materials. Epitaxial growth providesa different approach, which uses molecularbeam epitaxy or other means to form thin layersof semiconductor materials directly on thesurfaces of wafers of other materials. Although

this method avoids some of the aforementionedproblems, the requirements for epitaxy placesevere restrictions on the quality and type ofmaterials that can be grown, even when bufferlayers and other advanced techniques are used(1, 13).

By contrast, nanoscale wires, ribbons, mem-branes, or particles of inorganic materials, orcarbon-based systems such as single-walledcarbon nanotubes (SWNTs) or graphene sheets(14–17), can be grown and then suspended insolvents or transferred onto substrates in amanner that bypasses the need for epitaxialgrowth or wafer bonding. Recent work hasshown the integration of isolated crossed nano-wire diodes in 2D layouts formed by solutioncasting (18). Our results show how dissimilarsingle-crystal inorganic semiconductors (suchas micro- and nanoscale wires and ribbons ofGaN, Si, and GaAs) can be combined with oneanother and also with other classes of nano-materials (such as SWNTs) with the use of ascalable and deterministic printing method toyield complex, heterogeneously integratedelectronic systems in 2D or 3D layouts. Thecapabilities of this process are demonstrated byultrathin multilayer stacks of high-performancemetal oxide semiconductor field-effect transis-tors (MOSFETs), high electron mobility tran-sistors (HEMTs), thin-film transistors (TFTs),photodiodes, and other components that areintegrated into device arrays, logic gates, andactively addressable photodetectors on rigidinorganic and flexible plastic substrates.

Figure 1 illustrates representative steps forproducing these types of systems. The processbegins with the synthesis of the semiconductornanomaterials, each on their own source sub-strate. The devices shown in Fig. 1 allowmicro-and nanoscale wires and ribbons of single-crystalline GaN, GaAs, and Si that were formedwith the use of wafer-based source materialsand lithographic etching procedures (19–23) tobe integrated with each other or with networksof SWNTs that were grown by chemical vapordeposition (16, 23). Scanning electron micro-graphs at the top of Fig. 1 show thesesemiconductor nanomaterials after their removalfrom the source substrates. For circuit fabrica-

1Department of Materials Science and Engineering, Uni-versity of Illinois, Urbana-Champaign, IL 61801, USA.2Beckman Institute for Advanced Science and Technology,University of Illinois, Urbana-Champaign, IL 61801, USA.3Frederick Seitz Materials Research Laboratory, Universityof Illinois, Urbana-Champaign, IL 61801, USA. 4Departmentof Chemistry, University of Illinois, Urbana-Champaign, IL61801, USA. 5Department of Electrical and Computer En-gineering, University of Illinois, Urbana-Champaign, IL 61801,USA.

*To whom correspondence should be addressed. E-mail:jrogers@uiuc.edu

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tion, these elements remain in the configurationsdefined on the wafers during the fabrication orgrowth stage: aligned arrays in the case of theGaN,GaAs, and Simaterials, and submonolayer randomnetworks for the SWNTs. High-temperature dop-ing and annealing procedures for ohmic contactsto the GaN, GaAs, and Si can be performed onthe source substrates.

The next step involves transferring theseprocessed elements, with the use of an elasto-meric stamp–based printing technique (19),from the source substrates to a device substrate,such as a sheet of polyimide (PI) (Fig. 1). Inparticular, laminating a stamp of polydimethyl-siloxane against the source substrate establishessoft, van der Waals adhesion contacts to thesemiconductor nanomaterial elements. We con-tacted the “inked” stamp to a device substrate(such as a PI sheet) with a thin, spin-cast layerof a liquid prepolymer (such as polyamic acid)on its surface and then cured the polymer,which left these semiconductor materialsembedded on and well adhered to this layer(19–22) when the stamp was removed. Similarprocedures work well with a range of substrates(i.e., rigid or flexible and organic or inorganic)and semiconductor nanomaterials. We used aslightly modified version of this process for theSWNT devices (23). The thickness of the inter-layer (PI in this case) can be as small as 500 nmand was typically 1 to 1.5 mm for the systems wedescribe.

After some additional processing—includingdeposition and patterning of gate dielectrics,electrodes, and interconnects—the transferprinting and device fabrication steps can be re-peated, beginning with spin-coating a new pre-polymer interlayer on top of the previouslycompleted circuit level. Automated stages spe-cially designed for transfer printing or conven-tional mask aligners enable overlay registrationaccuracy of ~2 mm over several square centi-meters (fig. S1). The spatial distortions asso-ciated with the printing had a mean value of~0.5 mm (fig. S2). The yields for printing of Si,SWNT, GaAs, and GaN were >99%, >99%,>95%, and >85%, respectively. Defects in theselast two cases were associated with fracture andimpartial transfer for the relatively wide GaAsribbons and relatively thick GaN bars, respec-tively (fig. S3). Layer-to-layer interconnects(24) were formed simply by evaporating metallines over and into openings in the interlayersdefined by photopatterning and/or dry etching.

This fabrication approach has several im-portant features. First, all of the processing onthe device substrate occurs at low temperatures,thereby avoiding differential thermal expansionand shrinkage effects that can result in un-wanted deformations in multilayer stacked sys-tems. This operation also enables the use oflow-temperature plastic substrates and inter-layer materials, and it helps to ensure thatunderlying circuit layers are not thermally de-graded by the processing of overlying devices.

Second, the method is applicable to broadclasses of semiconductor nanomaterials, includ-ing emerging materials such as SWNTs. Third,the soft stamps enable nondestructive contactswith underlying device layers; these stamps,together with the ultrathin semiconductor ma-terials, can also tolerate surfaces that have sometopography. Fourth, the ultrathin device geom-etries and interlayers allow easy formation oflayer-to-layer electrical interconnects by directmetallization over the device structure. Thesefeatures overcome many of the disadvantagesof conventional approaches.

Figure 2 presents three-layer, 3D stacks ofarrays of Si MOSFETs fabricated by the generalprocess flow shown in Fig. 1. We used single-crystalline silicon nanoribbons with dopedcontacts (formed on the source wafer), SiO2

dielectrics formed by plasma-enhanced chemi-cal vapor deposition, and Cr/Au metallizationfor the source, drain, and gate electrodes (25).Each device uses three aligned nanoribbons,each with length L = 250 mm, widthW = 87 mm,and thickness = 290 nm. Figure 2A shows an

optical micrograph of an edge of the system; thelayout of the system was designed to revealseparately the parts of the substrate that sup-port one, two, and three layers of MOSFETs.A 90° rotation of the device geometry for thesecond layer, relative to the first and third,helps to clarify the layout of the system. Sche-matic cross-sectional and angled views of thestacked structure are shown in Fig. 2B. Thesample can be viewed in 3D using confocaloptical microscopy. Figure 2C shows top andangled views of such images. (The image qual-ity degrades somewhat with depth because ofscattering and absorption from the upper layers).Figure 2D presents electrical measurements ofrepresentative devices in each layer. Devices on

Fig. 2. (A) Optical micrograph view of the topof a 3D multilayer stack of arrays of single-crystalsilicon MOSFETs that use printed silicon nano-ribbons for the semiconductor. The bottom (1st),middle (2nd), and top (3rd) parts of this imagecorrespond to regions with one, two, and threelayers of devices, respectively. (B) Schematic cross-sectional (top) and angled (bottom) views. S, D,and G refer to source, drain, and gate electrodes(all shown in gold), respectively. The light and darkblue regions correspond to doped and undopedregions of the silicon ribbons; the purple layer isthe SiO2 gate dielectric. (C) 3D images (left, topview; right, angled view) collected by confocalmicroscopy on a device substrate similar to thatshown in (A) and (B). The layers are colorized (gold,top layer; red, middle layer; blue, bottom layer;silicon, gray) for ease of viewing. (D) Current-voltage characteristics of Si MOSFETs in each of thelayers, showing excellent performance (mobilitiesof 470 ± 30 cm2/Vs) and good uniformity in theproperties. The channel lengths and widths are 19and 200 mm, respectively. The overlap lengths, asdefined by distance that the gate electrode ex-tends over the doped source and drain regions,are 5.5 mm. IDS, drain current; VGS, bias voltage;VDS, drain voltage.

Fig. 1. Schematic illustration of a printed semi-conductor nanomaterials–based approach toheterogeneous 3D electronics. The process in-volves the repetitive transfer printing of col-lections of nanotubes, nanowires, nanoribbons,or other active nanomaterials, separately formedon source substrates, to a common device sub-strate to generate interconnected electronicsin ultrathin, multilayer stack geometries. HGI,heterogeneous integration.

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each of the three layers, which are formed ona PI substrate, show excellent properties withlinear mobilities of 470 ± 30 cm2/Vs (where theerror is SD), on/off ratios greater than 104, andthreshold voltages of –0.1 ± 0.2 V; there are nosystematic differences between devices in dif-ferent layers. Additional layers can be addedto this system by repeating the same proce-dures. To investigate issues related to mis-matches in coefficients of thermal expansionin these systems, we evaluated the behavior ofthe devices under thermal cycling (60 times)between room temperature and 90°C. Smallchanges were observed for the first few cyclesfollowed by stable behavior (fig. S9).

In addition to 3D circuits with a single semi-conductor, Fig. 3 illustrates that the capabilityto combine various semiconductors can be usedin multiple layers. We fabricated arrays ofHEMTs, MOSFETs, and TFTs—with the useof GaN bars, Si nanoribbons, and SWNT films,respectively, on PI substrates. Figure 3, A andB, shows high-magnification optical and con-focal images, respectively, of the resultingdevices. The GaN HEMTs on the first layeruse ohmic contacts (Ti/Al/Mo/Au, annealed onthe source wafer) for the source and drain, andSchottky (Ni/Au) contacts for the gates. Eachdevice uses GaN ribbons (composed of multi-layer stacks of AlGaN/GaN/AlN) intercon-nected electrically by processing on the devicesubstrate. The SWNT TFTs on the second layeruse SiO2 and epoxy for the gate dielectric andCr/Au for the source, drain, and gate. The SiMOSFETs use the same design as those shownin Fig. 2. Various other devices can be con-structed with different combinations of Si,SWNT, and GaN (figs. S4 and S5). Figure 3Cpresents the current-voltage characteristics oftypical devices in the systems of Fig. 3, A andB. In all cases, the properties are similar to thosefabricated on the source wafers: The GaNHEMTs have threshold voltages (Vth) of –2.4 ±0.2 V, on/off ratios greater than 106, and trans-conductances of 0.6 ± 0.5 mS; the SWNT TFTshave Vth = –5.3 ± 1.5 V, on/off ratios greater than105, and linear mobilities of 5.9 ± 2.0 cm2/Vs;and the Si MOSFETs have Vth = 0.2 ± 0.3 V,on/off ratios greater than 104, and linear mobil-ities of 500 ± 30 cm2/Vs.

Another interesting aspect of these devices,which follows from the use of thin PI substrates(25 mm), devices (<1.7 mm), and PI interlayers(1.5 mm), is their mechanical bendability. Thischaracteristic is important for applications inflexible electronics, for which these systemsmight provide attractive alternatives becauseof their enhanced capabilities compared withthose of conventional organic-based devices.We evaluated the effective transconductance(geff) for the Si, SWNT, and GaN devices in thesystem of Fig. 3A as a function of bend radius.Figure 3D, which shows these data normalizedto the transconductance in the unbent state(g0eff), demonstrates the stable performance for

bend radii down to 3.7 mm. To explore theresponse of devices to operation under variousconditions, such as repeated bending and elec-trical testing, we carried out two sets of exper-iments. Repeated bending (up to 2000 cycles)resulted in no substantial change in the prop-erties of the devices (fig. S8). Repeated elec-trical testing showed stable responses (~10%changes in properties, or less) (fig. S11). Figures

S12 to S15 present information on variation indevice properties.

Electrical interconnections formed betweendifferent levels in these devices can create

Fig. 4. (A) Image of a printed array of 3D siliconn-channel metal oxide semiconductor inverters ona PI substrate. The inverters consist of MOSFETs(channel lengths of 4 mm, load-to-driver widthratio of 6.7, and a driver width of 200 mm) on twodifferent levels, interconnected by electrical viastructures. The image on the top right provides amagnified view of the region indicated by the redbox in the left frame. The graph on the bottomright shows transfer characteristics of a typicalinverter. (B) Transfer characteristics of a printedcomplementary inverter that uses a p-channelSWNT TFT (channel length and width of 30 and200 mm, respectively) and an n-channel Si MOSFET(channel length and width of 75 and 50 mm,respectively). The insets provide an optical micro-graph of an inverter (left) and a circuit schematic(right). (C) Current-voltage response of a GaAsMSM (channel length and width of 10 and 100 mm,respectively) integrated with a Si MOSFET (channellength and width of 9 and 200 mm, respectively) atdifferent levels of illumination from dark to 11 mWwith an infrared light source at 850 nm. The insetsshow an optical image (left) and a circuit diagram(right). gnd, ground.

Fig. 3. (A) Optical micrograph of 3D heteroge-neously integrated electronic devices, includingGaN nanoribbon HEMTs, Si nanoribbon MOSFETs,and SWNT network TFTs, in a three-layer stack. (B)3D image collected by confocal microscopy. Thelayers are colorized (gold: top layer, Si MOSFETs;red: middle layer, SWNT TFTs; pink: bottom layer)for ease of viewing. (C) Electrical characteristics ofGaN devices on the first layer (channel lengths,widths and gate widths of 20, 170, and 5 mm,respectively, and ribbon thicknesses, widths, andlengths of 1.2, 10, and 150 mm, respectively),SWNT devices on the second layer (channel lengthsand widths of 50 and 200 mm, respectively, andaverage tube diameters and lengths of ~1.5 nmand ~10 mm, respectively), and Si devices on thethird layer (channel lengths and widths of 19 and200 mm, respectively). (D) (Left) Normalized trans-conductances (gm/g0m) of devices in each layer(black squares, Si MOSFETs; red circles, SWNT TFTs;green triangles, GaN HEMTs) as a function of bend-ing radius of the plastic substrate. T, tension; C,compression. (Right) Image of the bent system andprobing apparatus.

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interesting circuit capabilities. The thin polymerinterlayers allow robust interconnects to beformed easily by evaporating metal lines overlithographically defined openings. Thermalcycling tests showed no changes in theirproperties (fig. S10). Figure 4A shows a 3Dn-channel metal oxide semiconductor inverter(logic gate) in which the drive (L = 4 mm, W =200 mm) and load (L = 4 mm, W = 30 mm) SiMOSFETs are on different levels. With a sup-ply voltage of 5 V, this double-layer inverterexhibits well-defined transfer characteristicswith gains of ~2, comparable to the perform-ance of conventional planar inverters that usesimilar transistors. Figure 4B shows an inverterwith a complementary design (CMOS) with theuse of integrated n-channel Si MOSFETs andp-channel SWNT TFTs, designed to equalizethe current-driving capability in both pull-upand pull-down directions. Transfer curves col-lected with a supply voltage (VDD) of 5 V andgate voltage (input) swept from 0 to 5 V ap-pear in Fig. 4B. The curve shapes and gains(as high as ~7) are qualitatively consistentwith numerical circuit simulations (fig. S6).As a third example, we built GaAs metal-semiconductor-metal (MSM) infrared detectors(26), integrated with Si MOSFETs on flexible PIsubstrates, to demonstrate a capability for fab-ricating unit cells that could be used in activeinfrared imagers. In this case, printed nano-ribbons of GaAs (L = 400 mm,W = 100 mm, andthickness = 270 nm) transferred onto a substratewith a printed array of Si nanoribbon MOSFETsform the basis of the MSMs. Electrodes (Ti/Au)deposited on the ends of these GaAs nanoribbonsform back-to-back Schottky diodes with sepa-rations of 10 mm. The resulting detector cellsexhibit current enhancement as the intensity ofinfrared illumination increases (Fig. 4C), con-

sistent with circuit simulation (fig. S7). A re-sponsivity of about 0.30 A/W at the 850-nmwavelength is observed from 1 to 5 V. (This valueunderestimates the true responsivity because itignores optical reflection). The bendability of thissystem, which is comparable to that of the devicesin Fig. 3, could be useful for advanced systemssuch as curved focal plane arrays for wide-angleinfrared night vision imagers.

Printed semiconductor nanomaterials providenew approaches to 3D heterogeneously integratedsystems that could be important in various fieldsof application, including not only those suggestedby the systems reported here but also others suchas microfluidic devices with integrated electron-ics, chemical and biological sensor systems thatincorporate unusual materials with conventionalsilicon-based electronics, and photonic andoptoelectronic systems that combine light emit-ters and detectors of compound semiconductorwith silicon drive electronics or microelectro-mechanical structures. Furthermore, the compat-ibility of this approach with thin, lightweightplastic substrates may create additional oppor-tunities for devices that have unusual formfactors or mechanical flexibility as key features.

References and Notes1. K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat,

Proc. IEEE 89, 602 (2001).2. S. F. Al-Sarawi, D. Abbott, P. D. Franzon, IEEE Trans.

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3. A. S. Brown et al., Mater. Sci. Eng. B 87, 317 (2001).4. Y.-C. Tseng et al., Nano Lett. 4, 123 (2004).5. C. Joachim, J. K. Gimzewski, A. Aviram, Nature 408, 541

(2000).6. G. Roelkens et al., Opt. Express 13, 10102 (2005).7. D. B. Strukov, K. K. Likharev,Nanotechnology 16, 888 (2005).8. Q. Y. Tong, U. Gosele, Semiconductor Wafer Bonding:

Science and Technology (John Wiley, New York, 1999).9. M. A. Schmidt, Proc. IEEE 86, 1575 (1998).

10. P. Garrou, Semicond. Int. 28, SP10 (February, 2005).11. H. Amano, N. Sawaki, I. Akasaki, Y. Toyoda, Appl. Phys.

Lett. 48, 353 (1986).12. T. Kuykendall et al., Nat. Mater. 3, 524 (2004).13. J. C. Bean, Proc. IEEE 80, 571 (1992).14. A. M. Morales, C. M. Lieber, Science 279, 208 (1998).15. M. Law et al., Science 305, 1269 (2004).16. J. Kong, H. T. Soh, A. M. Cassell, C. F. Quate, H. Dai,

Nature 395, 878 (1998).17. K. S. Novoselov et al., Science 306, 666 (2004).18. Y. Huang, X. Duan, C. M. Lieber, Small 1, 142 (2005).19. M. A. Meitl et al., Nat. Mater. 5, 33 (2006).20. E. Menard, K. J. Lee, D. Y. Khang, R. G. Nuzzo, J. A. Rogers,

Appl. Phys. Lett. 84, 5398 (2004).21. Y. Sun, S. Kim, I. Adesida, J. A. Rogers, Appl. Phys. Lett.

87, 083501 (2005).22. S.-H. Hur, D.-Y. Khang, C. Kocabas, J. A. Rogers,

Appl. Phys. Lett. 85, 5730 (2004).23. Materials and methods are available as supporting

material on Science Online.24. S. Linder, H. Baltes, F. Gnaedinger, E. Doering, in

Proceedings of the 7th IEEE International Workshop onMicro Electro Mechanical Systems, Oiso, Japan, 25 to 28January 1994 (IEEE, Piscataway, NJ, 1994), pp. 349–354.

25. J.-H. Ahn et al., IEEE Electron Devices Lett 27, 460 (2006).26. J. B. D. Soole, H. Schumacher, IEEE J. Quantum Electron.

27, 737 (1991).27. The research was supported by the U.S. Department of

Energy, Division of Materials Sciences under award no.DEFG02-91ER45439, through the Frederick Seitz MaterialsResearch Laboratory (FS-MRL). We thank T. Banks andK. Colravy for help with cleanroom and other facilities at theFrederick Seitz Materials Research Laboratory and H. C. Ko,Q. Cao, P. Ferreira, J. Dong, and E. Menard for help withprinting and distortion measurements using facilities andmanufacturing approaches developed at the Center forNanoscale Chemical Electrical Mechanical ManufacturingSystems at the University of Illinois (funded by the NSF undergrant DMI-0328162). All imaging and surface analysis wasperformed at the FS-MRL Center for Microanalysis ofMaterials at the University of Illinois at Urbana-Champaign,supported by award no. DEFG02-91ER45439.

Supporting Online Materialwww.sciencemag.org/cgi/content/full/314/5806/1754/DC1Materials and MethodsFigs. S1 to S15

12 July 2006; accepted 31 October 200610.1126/science.1132394

Quantum Spin Hall Effect andTopological Phase Transition inHgTe Quantum WellsB. Andrei Bernevig,1,2 Taylor L. Hughes,1 Shou-Cheng Zhang1*

We show that the quantum spin Hall (QSH) effect, a state of matter with topological propertiesdistinct from those of conventional insulators, can be realized in mercury telluride–cadmiumtelluride semiconductor quantum wells. When the thickness of the quantum well is varied, theelectronic state changes from a normal to an “inverted” type at a critical thickness dc. We show thatthis transition is a topological quantum phase transition between a conventional insulating phaseand a phase exhibiting the QSH effect with a single pair of helical edge states. We also discussmethods for experimental detection of the QSH effect.

The spin Hall effect (1–5) has recently at-tracted great attention in condensed mat-ter physics, not only for its fundamental

scientific importance but also because of itspotential application in semiconductor spin-

tronics. In particular, the intrinsic spin Hall effectpromises the possibility of designing the intrinsicelectronic properties of materials so that the effectcan be maximized. On the basis of this line ofreasoning, it was shown (6) that the intrinsic spin

Hall effect can in principle exist in band in-sulators, where the spin current can flow withoutdissipation. Motivated by this suggestion, re-searchers have proposed the quantum spin Hall(QSH) effect for graphene (7) as well as forsemiconductors (8, 9), where the spin current iscarried entirely by the helical edge states in two-dimensional samples.

Time-reversal symmetry plays an importantrole in the dynamics of the helical edge states(10–12). When there is an even number of pairsof helical states at each edge, impurity scatteringor many-body interactions can open a gap at theedge and render the system topologically trivial.However, when there is an odd number of pairsof helical states at each edge, these effects can-not open a gap unless time-reversal symmetry is

1Department of Physics, Stanford University, Stanford, CA94305, USA. 2Kavli Institute for Theoretical Physics, Universityof California, Santa Barbara, CA 93106, USA.

*To whom correspondence should be addressed. E-mail:sczhang@stanford.edu

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www.sciencemag.org/cgi/content/full/314/5806/1754/DC1

Supporting Online Material for

Heterogeneous Three-Dimensional Electronics by Use of Printed Semiconductor Nanomaterials

Jong-Hyun Ahn, Hoon-Sik Kim, Keon Jae Lee, Seokwoo Jeon, Seong Jun Kang, Yugang Sun, Ralph G. Nuzzo, John A. Rogers*

*To whom correspondence should be addressed. E-mail: jrogers@uiuc.edu

Published 15 December, Science 314, 1754 (2006) DOI: 10.1126/science.1132394

This PDF file includes:

Materials and Methods Figs. S1 to S15

SUPPORTING ONLINE MATERIAL “Heterogeneous Three Dimensional Electronics by Use of Printed Semiconductor Nanomaterials” J.-H. Ahn, H.-S. Kim, K. Lee, S. Jeon, S. J. Kang, Y. Sun, R. G. Nuzzo and J. A. Rogers MATERIALS AND METHODS Printing Process

The printing involves the positioning of a PDMS stamp over a source wafer, establishing contact with this wafer, followed by peeling back to remove the nanostructures and, finally, transfer printing of these structures onto the target substrate. Figure S1 provides an image of a printer designed specifically for this purpose. The fabrication was performed using this system or a commercial mask aligner (Suss Microtech. Inc. MJB3). The reproducibility of the printing process has two aspects: (a) yields with which the structures can be printed onto the target substrate, and (b) absolute and relative positional accuracy of this printing process.

The registration depends on the mechanical accuracy of the stages of the printer and the distortions that can be induced in the PDMS during printing. To investigate these issues, we printed a layer of interconnected Si ribbons, spin cast a polyimide separation layer, and then printed another layer of interconnected ribbons but with an overall, well-defined rotation relative to the first layer. From this bilayer system, we measured the local offsets as a function of position across the printed area, in a point by point fashion, after subtracting the overall rotation. The results define a vector field of offsets. Using these data, we calculated the position averaged magnitude of the offsets. This comparison defines the positioning accuracy of our printer to be ~2 µm. Next, we subtracted a rigid overall translation from the vector field of offsets to reveal the underlying random distortions associated with the printing process. We find that these distortions have a distribution that is random across the printed area, with an average magnitude of ~0.5 �µm. Figure S2 summarizes this information. These results, while sufficient for many applications, do not represent fundamental limits. Increasing the engineering sophistication of the stages (e.g. using optically encoded stages) and of the stamps (e.g. using designs with rigid backings in composite layouts) can improve the performance.

The yields depend on the type of material, and the geometries of the structures. We find that the yields for the Si, SWNT, GaAs and GaN structures are >99%, >99%, >95% and >85%, respectively. Detailed examination of the printing defects in these second two cases shows that they arise from impartial transfer of the GaN bars, due to their relatively large thicknesses, and fracture of the GaAs ribbons, due to their relatively large widths. These results reinforce a key message of the paper: material structures with nanoscale dimensions are critically important to the printing and integration processes for these systems. Figure S3 shows typical results.

Device fabrication (a) Silicon devices: The fabrication begins with definition of contact doped thin ribbons of single crystal silicon, by processing silicon on insulator wafer (SOI; Soitec unibond with a 290 nm top Si layer with doping level of 6.0~9.4x1014/cm3). The first step involved phosphorous doping, using a solid source and spin-on-dopant (Filmtronic, P509), and a photolithographically defined layer of plasma enhanced chemical vapor (PECVD) deposited SiO2 (Plasmatherm, 300nm, 900mTorr, 350sccm, 2% SiH4/He, 795sccm NO2, 250˚C) as a mask to control where dopant diffuses into the silicon. After doping, SF6 plasma etching through a patterned layer of photoresist defined the ribbons. Undercut etching of the buried oxide with concentrated HF solution (Fisher Chemicals) released the ribbons from the wafer. This procedure completed the fabrication of contact doped ribbons of single crystal silicon. In the next step, contacting a flat elastomeric stamp of polydimethylsiloxane (PDMS, A:B=1:10, Sylgard 184, Dow Corning) with the photoresist-coated ribbons and then peeling back the stamp removed the ribbons from the wafer and left them adhered, by van der Waals forces between the hydrophobic PDMS and the photoresist, to the surface of the stamp. The stamp thus ‘inked’ with µs-Si ribbons from wafer was laminated against a polyimide (PI) sheet of 25 µm (Dupont, Kapton100E) spin-coated with a thin layer (~1.5µm) of liquid PI precursor, polyamic acid (Sigma_Aldrich Inc.). Curing the precursor, peeling off the PDMS stamp, and stripping the photoresist left the ribbons embedded on and well adhered to the surface of the PI substrate. The gate dielectric layer consisted of a layer of SiO2 (thickness ~100 nm) deposited by PECVD at relatively low temperature, 250oC. Photolithography and CF4 plasma etching defined openings to the doped source/drain regions of the silicon. Source, drain and gate electrodes of Cr/Au (5/100 nm, from bottom to top by electron beam evaporation, Temescal FC-1800) were defined in a single step by photolithography and wet etching. (b) GaN devices: GaN microstructures were fabricated on a bulk wafer of GaN with heteorostructure [ AlGaN(18 nm)/ GaN(0.6 µm)/ AlN(0.6 µm)/ Si]. An ohmic contact area defined by AZ 5214 photoresist and then cleaned with SiCl4

plasma in a RIE system. A Ti/Al/Mo/Au (15/60/35/50 nm) metal layer was then deposited by e-beam evaporation (Ti/Al/Mo) and thermal evaporation (Au). Washing away the resist completed left metal contacts on the GaN. Thermal annealed at 850 ˚C for 30 sec in N2 ambient formed the ohmics. SiO2 (Plasmatherm, 300nm, 900mTorr, 350sccm, 2% SiH4/He, 795sccm NO2, 250˚C) and Cr metal (e-beam evaporator, 150 nm) layers were deposited as the mask materials for subsequent inductively coupled plasma (ICP) etching. Photolithography, wet etching, and RIE processing (50 mTorr, 40 sccm CF4, 100W, 14 min) defined the ribbon geometries of the GaN. After removing the photoresist with acetone, ICP dry etching (3.2 mTorr, 15 sccm Cl2, 5 sccm Ar, -100V Bias, 14 min) was used to remove the exposed GaN and to etch slightly into the Si (~1.5µm) to facilitate the subsequent anisotropic etching. The Si was then etched away from underneath the GaN using a tetramethyl ammonium hydroxide (Aldrich, 150˚C for 4 min 30 sec). The sample was dipped in BOE (6:1, NH4F: HF) for 30 sec to remove the PECVD SiO2 and a new 50 nm e-beam evaporated SiO2

layer was deposited on top of the GaN ribbons. A PDMS slab ‘inked’ with the GaN ribbons from

mother wafer was then laminated against a PI sheet coated with 2 µm polyurethane (PU, Norland optical adhesive, No. 73). The sample was exposed to UV light (173 µWcm-2) for 15min to cure the PU. Peeling back the PDMS and removing the e-beam SiO2 by immersion in BOE for 20sec resulted in the transfer of the GaN elements to the plastic substrate. A negative photoresist (AZ nLOF2020) was used to pattern Schottky contacts of Ni/Au (80/180nm). The photoresist was removed with an AZ stripper (KWIK for 30min). (c) SWNT devices: Chemical vapor deposition (CVD) was used to grow random networks of individual single walled carbon nanotubes on SiO2/Si wafers. Ferritin (Sigma Aldrich) deposited on the substrate with a methanol was used as a catalyst. The feeding gas was methane (1900 sccm CH4 with a 300 sccm H2). The quartz tube in the furnace was flushed with a high flow of Ar gas for cleaning before growth. During the growth, the temperature was held at 900oC for 20 minutes. The transfer involved either procedures similar to the printing like processes described previously, or a slightly different method in which a thick Au layer and a PI precursor were coated on the SiO2/Si substrate with the tubes. After curing the PI, the Au/PI was peeled back. Laminating this layer against a prepatterned device substrate coated with a thin epoxy layer (SU8, 150 nm) and then removing the PI and Au layer by oxygen reactive ion etching and wet etching, respectively, completed the transfer. In the case of bottom gate devices, the substrate supported prepatterned gate electrodes and dielectrics. In particular, gate electrodes of Cr/Au/Cr (2/10/10 nm) were patterned by photolithography and then, 300 nm SiO2 was deposited on the substrate using PECVD. The source and drain electrodes of Cr/Au (2/20nm) were defined directly on top of the tubes. (d) 3D multilayer stacks of arrays of devices: Sequential application of the processing steps described above can yield stacks of devices in 3D layouts. Figures S4 and S5 give some examples. 3D Circuit (a) 3D Si NMOS inverter: Multilayer devices were constructed by repetitively applying the same fabrication procedures. In particular, to the PI precursor was spin-cast on the top of an existing layer of devices, and silicon ribbons were transfer-printed on top. The same processes were then used to fabricate devices. For vertical metal interconnects, an electrode area was defined by photo-patterning openings in a layer of AZ4620 photoresist, and then etching away the SiO2 and PI in this exposed area using CF4 and O2

plasma in a RIE system. Depositing 300 nm Al into this area established contacts at the bottom, and provided an electrically continuous connection over the step edge formed by the etched SiO2 and PI. (b) SWNT and Si CMOS inverter: The SWNT devices consisted of source/drain contacts of Au (20 nm) defined by photolithography on the tube networks. The SiO2 (100nm)/Si wafer substrate provided the gate dielectric and gate. Epoxy (SU8, 500 nm) was

then spin-coated onto this substrate after the SWNT transistors were selectively coated with photoresist (AZ5214). After UV exposure for curing of epoxy, a PDMS slab ‘inked’ with undoped Si ribbons was laminated against the substrate and subsequently removed by slow manual peeling to complete the transfer-printing process. Cr/Au (5/100 nm) were used as Schottky contacts for source and drain electrodes in the silicon devices. Al (100 nm) was used to connect the SWNT and Si transistor. See Fig. S6. (c) GaAs MSM IR detector integrated with Si TFT: GaAs wafers (IQE Inc., Bethlehem, PA.) were used to generate back-to-back schottky diodes. The ribbons were generated from a high-quality bulk wafer of GaAs with multiple epitaxial layers [Si-doped n-type GaAs(120 nm)/semi-insulating(SI)-GaAs(150 nm)/AlAs(200 nm)/SI-GaAs]. The carrier concentration of n-type GaAs is 4×1017 cm−3. GaAs wafers with photoresist mask patterns were anisotropically etched in the etchant (4mL H3PO4 (85 wt%), 52 mL H2O2 (30 wt%), and 48 mL deionized water). The AlAs layers were etched away with a diluted HF solution in ethanol (1:2 in volume). Layers of 2nm Ti and 28nm SiO2 were the deposited by e-beam evaporator. A PDMS stamp inked with the GaAs ribbons was then contacted to a layer of Si transistors coated with PI (thickness 1.5 µm). Peeling back the PDMS and removing Ti and SiO2 by BOE etchant completed the transfer of GaAs to the device substrate. Metals (Ti/Au = 5/70 nm) for the Schottky contacts were deposited by e-beam evaporation. Electrical interconnects between the GaAs back-to-back Schottky diodes and the Si MOSFET were defined by first patterning a layer of AZ4620 photoresist, then etching through the openings using CF4 and O2

plasma in a RIE system and then depositing a 300 nm of Al. See Fig. S7. Device characterization A semiconductor parameter analyzer (Agilent, 4155C) and a conventional probing station were used for the electrical characterization of the diodes and transistors. The IR response was measured under IR LED source with wavelength of 850 nM. Circuit Simulation To compare the measured transfer curve of the CMOS inverter with a simulation, level 2 PSPICE models for the n-channel Si MOSFET and the p-channel SWNT TFT were generated empirically. These PSPICE models were created based on the default PSPICE MOSFET model (MbreakN and MbreakP) with extracted parameters to fit the measured I-V curves of both Si NMOS and SWNT PMOS shown in Figure S5B. The PSPICE model for GaAs MSM photo-detector was created empirically using back-to-back schottky diodes connected in series with Si MOSFET. See Figs. S6 and S7. Reliability, Stability and Dispersion in Device Properties

Reliability – Reliability is interpreted to refer to the response of devices to operation under various conditions, such as repeated bending and thermal cycling. To explore this

issue, we carried out two sets of experiments. In the first, we subjected a trilayer stack of Si, GaN and SWNT devices on plastic to 2000 cycles of bending to a radius of curvature of 3.7 mm followed by releasing to a flat, relaxed state. The data from this mechanical fatigue test indicate negligible changes in device behavior. See Fig. S8. In the second set of experiments, we subjected layer to layer electrical interconnects and devices to repeated thermal cycling between room temperature and 90 oC. The interconnects show no change in electrical properties for up to 60 cycles. For devices, we chose to study Si MOSFETs because the mismatch between the coefficient of thermal expansion of Si and the polyimide is the larger than that for the other semiconductor materials explored in this paper, thereby providing the most demanding test of reliability under thermal cycling. The data show that these devices exhibit only modest change after the first 20 cycles, followed by stable behavior for up to 60 cycles. These results are shown in Figs. S9 and S10. Stability – Stability is interpreted to refer to the response of devices to repeated electrical cycling and test. To explore this issue, we cycled the Si, GaN and SWNT devices up to 100 times. We observed changes in properties at the ~10% level, or less. These results are shown in Fig. S11. Dispersion – We interpret dispersion to mean variations in device properties on a given substrate as well as between different substrates. The data appear in Figs. S12-15. We also explored the nature of defects that can appear in devices (due to processing, as opposed to printing, the latter of which is addressed in Fig. S3), which are summarized in Figs. S13-S15.

Figure S1. Image of the automated stage for transfer-printing.

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Figure S2. (A) Optical micrographs of a two layer printed structure consisting of interconnected Si ribbons. The arrow indicates the shift between two layers, achieved by a rotation between printing steps. The left frame shows a schematic illustration of the structure. (B) Vector diagrams and a histogram plot of misalignment between the positions of particular features of printed-interconnected matrices of Si ribbons in a two layer stack with the size of 7.44 x 6.8 mm. The left vector diagram shows distortion after subtraction of the rotation between the layers. The middle diagram shows distortion after translational and rotational misalignments are subtracted. The right plot shows a histogram of the magnitudes of the distortion as defined in the middle frame. The median distortion is less than 0.5µm.

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Figure S3. (A) Optical images of the Si, GaN, GaAs and SWNT structures printed onto plastic substrates. The images highlight (red squares) the defects that can occur in the GaN and GaAscases. (B) Transfer efficiencies from source to target substrates, as determined by optial and electron microscopy. The non-ideal printing yields of the GaN and GaAs structures result, in part, from their relatively large thicknesses and widths, respectively.

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Figure S4. (A) Optical micrographs of three dimensional, heterogeneously integrated arrays of Si MOSFETs and GaN HEMTs on a polyimide substrate. The right inset shows a cross sectional schematic view. The electrodes (gold), SiO2 (PEO; purple), Si (light blue: undoped; dark blue: doped), GaN (dark green: ohmic contacts; light green: channel), polyimide (PI; brown) and polyurethane (PU; tan) are all shown. (B) Current-voltage characteristics of a typical Si MOSFET (channel length and width of 14 µm and 200 µm, respectively) and a GaN HEMT with (gate length and channel width 5 µm and 200 µm, respectively). The data for the Si and GaN in the left frames were measured at Vdd = 0.1V and Vdd = 2V, respectively.

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Figure S5. (A) Optical micrographs of three dimensional, heterogeneously integrated arrays of Si MOSFETs and SWNT TFTs on a polyimide substrate. The right inset shows a cross sectional schematic view. The electrodes (gold), SiO2 (PEO; purple), Si (light blue: undoped; dark blue: doped), SWNTs (grey), polyimide (PI; brown) and cured polyimide (tan) are all shown. (B)Current-voltage characteristics of a typical SWNT TFT (channel length and width of 75 µm and 200 µm, respectively) and a typical Si MOSFET (gate length and channel width 19 µm and 200 µm, respectively). The data for the SWNT and Si in the left frames were measured at Vdd = -0.5 V and Vdd = 0.1 V, respectively.

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Figure S7. (A) Schematic structure of the cross section and circuit schematic of GaAs MSM-Si TFT IR detector built on a polyimide substrate. (B) Current-Voltage charateristic of GaAs MSM IR detector (L:10µm, W=100µm) and transfer and I-V characteristics of Si TFT (L = 9µm, W = 200µm) with a 3V supply. (C) Calculated I-V charateristic of GaAs MSM (channel length and width of 10 µm and 100 µm, respectively) and I-V response of a GaAs MSM integrated with a Si MOSFET (channel length and width of 9 µm and 100 µm, respectively) with a 3V supply.

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Figure S11. Electrical cycling tests on (A) Si MOSFETs (channel length = 9 µm, channel width = 200 µm. Vdd = 0.1 V). (B) SWNT TFTs (channel length = 50 µm, channel width = 200 µm. Vdd= -0.5 V). (C) GaN HEMTs (Gate length, channel width and gate width are 20 µm, 170 µm and 5 µm, respectively. Vdd = 2 V).

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Figure S12. (A) Cross sectional schematic illustration of three dimensional, heterogeneously integrated arrays of Si MOSFETs, SWNT TFTs and GaN HEMTs on a polyimide substrate. (B)Transfer characteristics, effective mobilities and on/off ratios for several of the Si MOSFETs(channel width = 200 µm, black line: channel length = 9 µm, red: 14 µm, green:19 µm, blue: 24 µm), (C) the SWNT TFTs (channel width = 200 µm, black line: channel length = 25 µm, red: 50 µm, green:75 µm, blue: 100 µm) and (D) transfer characteristics, transconductances and on/off ratios for GaN HEMTs (channel lengths, widths and gate widths of 20 µm, 5 µm and 200 µm, respectively)

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mer

A

Figure S13. (A) Histograms of threshold voltages, on/off ratio and mobility of typical Si MOSFETs fabricated on eleven different substrates (channel length = 9 µm, channel width = 200 µm. Vdd = 0.1 V). (B) Optical images showing an example of device failure associated with a hairline crack formed in the silicon during processing.

200 µm

Failure of device by defect

B

40 µm

A

0

1

2

3

4

On/Off ratio106104102

Num

ber

0.0 2.0 4.0 6.00

1

2

3

Num

ber

µ (cm2/VS)-7.0 -6.0 -5.0 -4.00

1

2

3

Num

ber

Threshold Voltage (V)

B

400 µm

200 µm

Figure S14. (A) Histograms of threshold voltages, on/off ratio and mobility of typical SWNT TFTs fabricated on five different substrates (channel length = 50 µm, channel width = 200 µm. Vdd = -0.5 V) . (B) Optical images showing an example of device failure by a defect associated with the photolithographic pattern of the source metal.

A

2.0 2.6 3.2 3.80

1

2

Num

ber

gm (mS)

0

1

2

3

On/Off ratio106104102

Num

ber

-2.6 -2.2 -1.8 -1.4 -1.00

1

2

3

Num

ber

Threshold Voltage (V)

Figure S15. (A) Histograms of threshold voltages, on/off ratio and mobility typical GaN HEMTsfabricated on five different substrates (Devices with perfect ribbons were chose selectively. Gate length, channel width and gate width are 20 µm, 170 µm and 5 µm, respectively. Vdd = 2 V) (B)Optical images showing an example of device failure associated with a missing GaN bar.

Failure by disconnection of gate metal

B

200 µm

20 µm