HDL+ Sub-Committees Chairs Meeting

Vassilios GerousisHDL+ Committee Chairman + Accellera Technical Chairman

Infineon Technologies

June 20, 2002 www.accellera.org2 Vassilios Gerousis

1- Introduction.

A- HDL+ Charter.

B- Accellera Organization.

2- Operational Sub-committees for HDL+.

A- Scope.

B- Structure.

C- Donation Process.

D- Voting.

E- Milestones and Expectation.

4- HDL+ Targets expected for all committees.

5- Synchronization.

Agenda

June 20, 2002 www.accellera.org3 Vassilios Gerousis

HDL+ Charter

• Advanced HDL languages into higher design abstraction and verification.• Our Focus is on Verilog First.

June 20, 2002 www.accellera.org4 Vassilios Gerousis

Hierarchy and Functions• Accellera Board manage the business of Accellera and

provide “Guidance” to its technical committees.• Technical Coordinating Committee (TCC):

• The TC-chair is appointed by Accellera board.• Manage Rules and Guidelines for the committees.• Create and manage technical roadmap.• Can creat new committees with approval of the board.

• Technical Committees: Develop draft standards based on business guidance of the Board and Technical guidance by the TCC.

• Committee operation is governed by TCC rules and guidelines.

June 20, 2002 www.accellera.org5 Vassilios Gerousis

Technical (sub-)Committee• Technical chairs are appointed by the TC chair.• Technical chairs can be fired by the TC chair.• Each Committee/Sub-committee must establish:

• Email reflector and Web.

• Mission

• Goals.

• Milestones.

• Deliverables.

• Status report.

• Technical donation must go through Accellera Chairman and the TC chairman, before donation analysis can start.

June 20, 2002 www.accellera.org6 Vassilios Gerousis

Current HDL+ Subcommittees• SV-BC: Focus on the the basic issue list.

• Chairman: Cliff Cummings.

• Co-Chairman: ?

• SV-EC: Focus on the enhancement and focused area of donations. The only donation we have is Synopsys. In addition to the committee list we have the TestBench from Synopsys.• Chairman: David Smith.

• Co-Chairman: ?

• SV-CC: Focus on the C/C++ interface (API, Coverage, etc.). Analyze the Synopsys Direct-C donation.• Chairman: John Stickley ? (Suggestion by Stuart Sutherland).

• Co-Chairman: Ghassan Khoory

• SV-AC: Focus on SystemVerilog Assertion. Analyze donation from Synopsys. Synchronize with Sugar and OVL.

June 20, 2002 www.accellera.org7 Vassilios Gerousis

HDL+ Sub-Committee - Continued

• OVL Committee: Focus on OVL library only.• Chairman: David Lacey.

• Co-Chairman: Tom Fitz. (Transfer to SV-AC Co-Chair?).

• Harry Foster and Erich Marschner from FV committee will help HDL+ to syncrhonize the assertion with Sugar.• A common viewpoint will be established.

• Accept inputs from members to formulate a practical solution.

• Guide Accellera to unify Assertion and Property Assertion Language (Sugar).

June 20, 2002 www.accellera.org8 Vassilios Gerousis

Donation• Donation negotiation must only go through Accellera Chairman and

TC Chairman.

• Donation will have “assigned” status by signing a legal letter. • Technical discussion cannot start prior to the assigned status.

• The assigned donation will be sent to one designated committee. The committee will • Analyze.

• Evaluate.

• Accept or Reject the donation through a formal vote.

• Accepted donation marks the donation as Accellera property.

• An Accellera draft LRM can be started.

• Committee is allowed to do changes in the donation.

June 20, 2002 www.accellera.org9 Vassilios Gerousis

Voting structure and Rules• Three out four meetings applies (75%).• One vote per company.• Voting rules will apply to THE designated company

representative. Accellera membership applies.• Each company must designate a person for voting. No alternate is

allowed unless the person leaves the company.

• Each one of SystemVerilog 3.0 IEEE members, who is not an Accellera member or have a commercial affiliation, will have an individual vote.• Proxy can vote.

• We make decisions with the best inputs at the time.• We commit to track issues even after the vote

June 20, 2002 www.accellera.org10 Vassilios Gerousis

Expected Milestones• Planning meeting on June 5th, 2002.• HDL+ committee meeting will happen once a month

to synchronize activities and resolve issues.• A “qualified” voting member of a committee will

automatically have a voting previlage in HDL+.

• The first month:• Start addressing issue list.

• Start analyzing the “assigned” donation.

• Get the committee operation (mission, goals, members, etc.).

• Identify areas of disconnects and areas for synchronization.

June 20, 2002 www.accellera.org11 Vassilios Gerousis

HDL+ Targets

Septemeber 1 Targets• Each issue item should have an assigned owner. The

owner must develop changes/proposed enhancement and obtain sub-committee approval.

• Donations should have been completed (analyzed, evaluated and voting completed).• No new donation will be accepted after September.

• New donation should be complementary.> One competing donation will add 6/12 months to the schedule.

• A face to face meeting will be planned in San Jose.

June 20, 2002 www.accellera.org12 Vassilios Gerousis

HDL+ Targets - Continued 1

December 2002 Target• Language LRM (First Draft) for SystemVerilog. Owner is

SV-EC. The SV-BC will collaborate on certain sections to be modified.

• C/C++ SystemVerilog LRM Draft. Owner is SV-CC.

• Assertion SystemVerilog LRM Draft. Owner is SV-AC.

• OVL 2.0 LRM Draft. Owner is OVL committee.

• HDL+ will organize the different LRM Drafts and ensure they are synchronized.

> PSL (Sugar) synchronization as agreed by the chairs viewpoints.

June 20, 2002 www.accellera.org13 Vassilios Gerousis

HDL+ Targets - Continued 2

February 15 Target:• Final Fraft version sent to the Accellera Board.

June 20, 2002 www.accellera.org14 Vassilios Gerousis

Synchronization - Understanding

• Basic SystemVerilog Assertion Requirements:• SystemVerilog must increase the coverage of “embedded”

assertions. (targeted for smart verification and smart synthesis).

• It must adhere to Verilog structure.

• It must provide both simulation and formal semantics.

• PSL Sugar:• It has a rich semantics. Currently a subset is being

implemented by EDA vendors.

• It can support Verilog, VHDL and other languages as an external interface

• User wish: One language.

June 20, 2002 www.accellera.org15 Vassilios Gerousis

Possibility Number One

Formula One:• Define a common set of Sugar and Vera-Assertion.• The common set can be made as close as possible in

terms of semantics and syntax.• Both Sugar and SystemVerilog assertion must adhere to

this new syntax and semantics.

• The common set must adhere to Verilog Rules of compatibility.

• Disadvantages:• Two separate languages.

• Delays in releasing Sugar 1.0