CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component toprevent damage and/or degradation which may be induced by ESD.

HCPL-316J

Features• Drive IGBTs up to

IC = 150 A, VCE = 1200 V• Optically Isolated, FAULT

Status Feedback• SO-16 Package• CMOS/TTL Compatible• 500 ns Max. Switching

Speeds

• “Soft” IGBT Turn-off• Integrated Fail-Safe IGBT

Protection– Desat (VCE) Detection– Under Voltage Lock-Out

Protection (UVLO) withHysterisis

• User Configurable:Inverting, Non-inverting,Auto-Reset, Auto-Shutdown

• Wide Operating VCC Range:15 to 30 Volts

• -40°C to +100°C OperatingTemperature Range

• 15 kV/µs Min. Common ModeRejection (CMR) atVCM = 1500 V

• Regulatory Approvals: UL,CSA, VDE 0884 (891 VpeakWorking Voltage)

Fault Protected IGBT Gate Drive

Hewlett-Packard’s 2.0 Amp Gate Drive Optocoupler with Integrated Desaturation (VCE) Detection and FaultStatus Feedback makes IGBT VCE fault protection compact, affordable, and easy-to-implementwhile satisfying worldwide safety and regulatory requirements.

2.0 Amp Gate Drive Optocouplerwith Integrated (VCE) DesaturationDetection and Fault StatusFeedback

Technical Data

MICRO-CONTROLLER

M

HCPL - 316J

–HV

+HV

ISOLATION BOUNDARY

HCPL - 316J

ISOLATION BOUNDARY

HCPL - 316J

ISOLATION BOUNDARY

HCPL - 316J

ISOLATION BOUNDARY

HCPL - 316J

ISOLATION BOUNDARY

HCPL - 316J

ISOLATION BOUNDARY

HCPL - 316J

ISOLATION BOUNDARY

3-PHASE INPUT

FAULT

2

UVLO Desat Condition Pin 6VIN+ VIN- (VCC2 - VE) Detected on (FAULT) VOUT

Pin 14 OutputX X Active X X LowX X X Yes Low Low

Low X X X X LowX High X X X Low

High Low Not Active No High High

Typical Fault ProtectedIGBT Gate Drive CircuitThe HCPL-316J is an easy-to-use,intelligent gate driver whichmakes IGBT VCE fault protectioncompact, affordable, and easy-to-implement. Features such as user

Figure 1. Typical Desaturation Protected Gate Drive Circuit, Non-Inverting.

configurable inputs, integratedVCE detection, under voltagelockout (UVLO), “soft” IGBTturn-off and isolated fault feed-back provide maximum designflexibility and circuit protection.

Description of Operationduring Fault Condition1. DESAT terminal monitors the

IGBT VCE voltage throughDDESAT.

2. When the voltage on theDESAT terminal exceeds7 volts, the IGBT gate voltage(VOUT) is slowly lowered.

3. FAULT output goes low,notifying the microcontrollerof the fault condition.

4. Microcontroller takesappropriate action.

Output ControlThe outputs (VOUT and FAULT)of the HCPL-316J are controlledby the combination of VIN, UVLOand a detected IGBT Desatcondition. As indicated in thebelow table, the HCPL-316J can

be configured as inverting ornon-inverting using the VIN+ orVIN- inputs respectively. When aninverting configuration is desired,VIN+ must be held high and VIN-toggled. When a non-invertingconfiguration is desired, VIN-must be held low and VIN+toggled. Once UVLO is not active(VCC2 - VE > VUVLO), VOUT isallowed to go high, and the

DESAT (pin 14) detection featureof the HCPL-316J will be theprimary source of IGBT protection.UVLO is needed to ensure DESATis functional. Once VUVLO+ > 11.6V, DESAT will remain functionaluntil VUVLO- < 12.4 V. Thus, theDESAT detection and UVLOfeatures of the HCPL-316J work inconjunction to ensure constantIGBT protection.

* THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED.

+ –

+ –

*

*

*

CBLANK

DDESAT

RPULL-DOWN

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

+ –µC

RF

VF+ –

RGVCE

VCE

+

–

+

–

100 Ω

3

Product OverviewDescriptionThe HCPL-316J is a highlyintegrated power control devicethat incorporates all thenecessary components for acomplete, isolated IGBT gatedrive circuit with fault protectionand feedback into one SO-16package. TTL input logic levelsallow direct interface with amicrocontroller, and an opticallyisolated power output stagedrives IGBTs with power ratingsof up to 150 A and 1200 V. Ahigh speed internal optical linkminimizes the propagation delaysbetween the microcontroller andthe IGBT while allowing the twosystems to operate at very largecommon mode voltagedifferences that are common inindustrial motor drives and otherpower switching applications. An

output IC provides localprotection for the IGBT toprevent damage duringovercurrents, and a secondoptical link provides a fullyisolated fault status feedbacksignal for the microcontroller. Abuilt in “watchdog” circuitmonitors the power stage supplyvoltage to prevent IGBT causedby insufficient gate drivevoltages. This integrated IGBTgate driver is designed toincrease the performance andreliability of a motor drivewithout the cost, size, andcomplexity of a discrete design.

Two light emitting diodes and twointegrated circuits housed in thesame SO-16 package provide theinput control circuitry, the outputpower stage, and two opticalchannels. The input Buffer IC is

designed on a bipolar process,while the output Detector IC isdesigned manufactured on a highvoltage BiCMOS/Power DMOSprocess. The forward opticalsignal path, as indicated byLED1, transmits the gate controlsignal. The return optical signalpath, as indicated by LED2,transmits the fault statusfeedback signal. Both opticalchannels are completelycontrolled by the input andoutput ICs respectively, makingthe internal isolation boundarytransparent to themicrocontroller.

Under normal operation, theinput gate control signal directlycontrols the IGBT gate throughthe isolated output detector IC.LED2 remains off and a faultlatch in the input buffer IC isdisabled. When an IGBT fault isdetected, the output detector ICimmediately begins a “soft”shutdown sequence, reducing theIGBT current to zero in acontrolled manner to avoidpotential IGBT damage frominductive overvoltages.Simultaneously, this fault status istransmitted back to the inputbuffer IC via LED2, where thefault latch disables the gatecontrol input and the active lowfault output alerts themicrocontroller.

During power-up, the UnderVoltage Lockout (UVLO) featureprevents the application ofinsufficient gate voltage to theIGBT, by forcing theHCPL-316J’s output low. Oncethe output is in the high state, theDESAT (VCE) detection feature ofthe HCPL-316J provides IGBTprotection. Thus, UVLO andDESAT work in conjunction toprovide constant IGBTprotection.

SHIELD

DESAT

FAULT

UVLO

OUTPUT ICSHIELD

INPUT IC

RESET 5

FAULT6

VIN+1

VIN- 2

VCC13

VCC213

12

VOUT11

VEE9,10

VE16

DESAT14

VC

VLED2+GND1

154

VLED1-

7 8

VLED1+

LED2

LED1 D R I V E R

4

Pin DescriptionsSymbol Description Symbol Description

VIN+ Non-inverting gate drive voltage output VE Common (IGBT emitter) output supply(VOUT) control input. voltage.

VIN- Inverting gate drive voltage output VLED2+ LED 2 anode. This pin must be left uncon-(VOUT) control input. nected for guaranteed data sheet

performance. (For optical coupling testingonly)

VCC1 Positive input supply voltage. (4.5 V to 5.5 V) DESAT Desaturation voltage input. When the voltageon DESAT exceeds an internal referencevoltage of 7 V while the IGBT is on, FAULToutput is changed from a high impedancestate to a logic low state within 5 µs. SeeNote 25.

GND1 Input Ground. VCC2 Positive output supply voltage.RESET FAULT reset input. A logic low input for at VC Collector of output pull-up triple-darlington

least 0.1 µs, asynchronously resets FAULT transistor. It is connected to VCC2 directly oroutput high and enables VIN. Synchronous through a resistor to limit output turn-oncontrol of RESET relative to VIN is required. current.RESET is not affected by UVLO. AssertingRESET while VOUT is high does not affectVOUT.

FAULT Fault output. FAULT changes from a high VOUT Gate drive voltage output.impedance state to a logic low output within5 µs of the voltage on the DESAT pinexceeding an internal reference voltage of7 V. FAULT output remains low until RESETis brought low. FAULT output is an opencollector which allows the FAULT outputsfrom all HCPL-316Js in a circuitto be connected together in a “wired OR”forming a single fault bus for interfacingdirectly to the micro-controller.

VLED1+ LED 1 anode. This pin must be left uncon- VEE Output supply voltage.nected for guaranteed data sheet per-formance. (For optical coupling testing only)

VLED1- LED 1 cathode. This pin must be connectedto ground.

Package Pin Out

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

5

Package CharacteristicsAll specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, VCC2 - VEE =30 V, VE - VEE = 0 V, and TA = +25°C.

Parameter Symbol Min. Typ. Max. Units Test Conditions NoteInput-Output Momentary VISO 3750 Vrms RH < 50%, t = 1 min., 1, 2,Withstand Voltage TA = 25°C 3Resistance (Input - Output) RI-O >109 Ω VI-O = 500 Vdc 3Capacitance (Input - Output) CI-O 1.3 pF f = 1 MHzOutput IC-to-Pins 9 &10 θO9-10 30 °C/W TA = 100°CThermal ResistanceInput IC-to-Pin 4 Thermal Resistance θI4 60

Ordering InformationSpecify Part Number followed by Option Number (if desired).

Example: HCPL-316J#XXX

No Option = 16-Lead, Surface Mt. package, 45 per tube.500 = Tape and Reel Packaging Option, 850 per reel.

Option data sheets available. Contact Hewlett-Packard sales representative, authorized distributor, or visitour WEB site at www.hp.com/go/isolator.

Package Outline Drawings16-Lead Surface Mount

Maximum Solder Reflow Temperature Profile

240

∆T = 115°C, 0.3°C/SEC

0

∆T = 100°C, 1.5°C/SEC

∆T = 145°C, 1°C/SEC

TIME – MINUTES

TE

MP

ER

AT

UR

E –

°C

220200180160

140120100

80

6040

20

0

260

1 2 3 4 5 6 7 8 9 10 11 12

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

NOTE:

INITIAL AND CONTINUED VARIATION IN THECOLOR OF THE HCPL-316J’s WHITE MOLDCOMPOUND IS NORMAL AND DOES NOT AFFECTDEVICE PERFORMANCE OR RELIABILITY.

dimensions in: inches (millimeters)

9

0.295 ± 0.010 (7.493 ± 0.254)

10111213141516

87654321

0.018 (0.457)

0.138 ± 0.005 (3.505 ± 0.127)

9°

0.406 ± 0.10 (10.312 ± 0.254)

0.408 ± 0.010 (10.160 ± 0.254)

0.025 MIN.0.008 ± 0.003

(0.203 ± 0.076) STANDOFF

0.345 ± 0.010 (8.986 ± 0.254)

0–8°

0.018 (0.457)

0.050 (1.270)

ALL LEADS TO BE COPLANAR ± 0.002

HP 316J YYWW

TYPE NUMBERDATE CODE

6

Regulatory InformationThe HCPL-316J is pendingapproval by the followingorganizations:

VDEApproved under VDE0884/06.92with VIORM = 891 Vpeak.

ULRecognized under UL 1577,component recognition program,File E55361.

CSAApproved under CSA ComponentAcceptance Notice #5, File CA88324.

VDE 0884 Insulation Characteristics* Description Symbol Characteristic Unit

Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms I - IV for rated mains voltage ≤ 300 Vrms I - III for rated mains voltage ≤ 600 Vrms I - IIClimatic Classification 55/100/21Pollution Degree (DIN VDE 0110/1.89) 2Maximum Working Insulation Voltage VIORM 891 VPEAK

Input to Output Test Voltage, Method b**VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 1670 VPEAKPartial Discharge < 5 pC

Input to Output Test Voltage, Method a**VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, VPR 1336 VPEAKPartial Discharge < 5 pC

Highest Allowable Overvoltage**(Transient Overvoltage tini = 10 sec) VIOTM 6000 VPEAK

Safety-limiting values - maximum values allowed in the event ofa failure, also see Figure 2.

Case Temperature TS 175 °CInput Power PS, INPUT 400 mWOutput Power PS, OUTPUT 1200 mW

Insulation Resistance at TS, VIO = 500 V RS >109 Ω

Figure 2. Dependence of Safety Limiting Values on Temperature.

* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits inapplication. Surface mount classification is class A in accordance with CECCOO802.

** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulationssection, (VDE 0884) for a detailed description of Method a and Method b partial discharge test profiles.

PS

– P

OW

ER

– m

W

00

TS – CASE TEMPERATURE – °C

200

1200

800

25

1400

50 75 100

400

150 175

PS, OUTPUT PS, INPUT

125

200

600

1000

7

Absolute Maximum RatingsParameter Symbol Min. Max. Units Note

Storage Temperature Ts -55 125 °COperating Temperature TA -40 100Output IC Junction Temperature TJ 125 4Peak Output Current |Io(peak)| 2.5 A 5Fault Output Current IFAULT 8.0 mAPositive Input Supply Voltage VCC1 -0.5 5.5 VoltsInput Pin Voltages VIN+, VIN- and VRESET -0.5 VCC1

Total Output Supply Voltage (VCC2 - VEE) -0.5 35Negative Output Supply Voltage (VE - VEE) -0.5 15 6Positive Output Supply Voltage (VCC2 - VE) -0.5 35 - (VE - VEE)Gate Drive Output Voltage Vo(peak) -0.5 VCC2

Collector Voltage VC VEE + 5 V VCC2

DESAT Voltage VDESAT VE VE + 10Output IC Power Dissipation PO 600 mW 4Input IC Power Dissipation PI 150Solder Reflow Temperature Profile See Package Outline Drawings section

Recommended Operating Conditions Parameter Symbol Min. Max. Units Note

Operating Temperature TA -40 +100 °CInput Supply Voltage VCC1 4.5 5.5 Volts 28Total Output Supply Voltage (VCC2 - VEE) 15 30 9Negative Output Supply Voltage (VE - VEE) 0 15 6Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE)Collector Voltage VC VEE + 6 VCC2

Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions

Minimum External Air Gap L(101) 8.3 mm Measured from input terminals to output(Clearance) terminals, shortest distance through air.Minimum External L(102) 8.3 mm Measured from input terminals to outputTracking (Creepage) terminals, shortest distance path along body.Minimum Internal Plastic 0.5 mm Through insulation distance conductor toGap (Internal Clearance) conductor, usually the straight line distance

thickness between the emitter and detector.Tracking Resistance CTI >175 Volts DIN IEC 112/VDE 0303 Part 1(Comparative TrackingIndex)Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

8

Electrical Specifications (DC)Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V;all Minimum/Maximum specifications are at Recommended Operating Conditions.

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

Logic Low Input VIN+L, VIN-L, 0.8 VVoltages VRESETL

Logic High Input VIN+H, VIN-H, 2.0Voltages VRESETH

Logic Low Input IIN+L, IIN-L, -0.5 -0.4 mA VIN = 0.4 VCurrents IRESETL

FAULT Logic Low IFAULTL 5.0 12 VFAULT = 0.4 V 30Output Current

FAULT Logic High IFAULTH -40 µA VFAULT = VCC1 31Output Current

High Level Output IOH -0.5 -1.5 A VOUT = VCC2 - 4 V 3, 8, 7

-2.0 VOUT = VCC2 - 15 V 5

Low Level Output IOL 0.5 2.3 VOUT = VEE + 2.5 V 4, 9, 7

2.0 VOUT = VEE + 15 V 33 5

Low Level Output IOLF 90 160 230 mA VOUT - VEE = 14 V 5, 34 8Current during FaultCondition

High Level Output VOH VC - 3.5 VC - 2.5 VC - 1.5 V IOUT = -100 mA 6, 8, 9, 10,Voltage VC -2.9 VC - 2.0 VC - 1.2 IOUT = -650 µA 35 11

VC IOUT = 0

Low Level Output VOL 0.17 0.5 IOUT = 100 mA 7, 9, 26Voltage 36

High Level Input ICC1H 17 22 mA VIN+ = VCC1 = 5.5 V, 10,Supply Current VIN- = 0 V 37,

Low Level Input ICCIL 6 11 VIN+ = VIN- = 0 V,Supply Current VCC1 = 5.5 V

Output Supply ICC2 2.5 5 VOUT open 11,12, 11Current 39,40

Low Level Collector ICL 0.3 1.0 IOUT = 0 15, 27Current 59

High Level Collector ICH 0.3 1.3 IOUT = 0 15, 58 27Current 1.8 3.0 IOUT = -650 µA 15, 57

VE Low Level Supply IEL -0.7 -0.4 0 14,Current 61

VE High Level Supply IEH -0.5 -0.14 0 14, 25Current 40

Blanking Capacitor ICHG -0.13 -0.25 -0.33 VDESAT = 0 - 6 V 13, 11,Charging Current -0.18 -0.25 -0.33 VDESAT = 0 - 6 V, 41 12

TA = 25°C - 100°CBlanking Capacitor IDSCHG 10 50 VDESAT = 7 V 42Discharge Current

UVLO Threshold VUVLO+ 11.6 12.3 13.5 V VOUT > 5 V 43 9, 11,13

VUVLO- 11.1 12.4 VOUT < 5 V 9, 11,14

UVLO Hysteresis (VUVLO+ - 0.4 1.2VUVLO-)

DESAT Threshold VDESAT 6.5 7.0 7.5 VCC2 -VE >VUVLO- 16, 1144

32

38

Current

Current

9

Switching Specifications (AC)Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V;all Minimum/Maximum specifications are at Recommended Operating Conditions.

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

VIN to High Level Output tPLH 0.10 0.30 0.50 µs Rg = 10 Ω 17,18,19, 15Propagation Delay Time Cg = 10 nF, 20,21,22,

VIN to Low Level Output tPHL 0.10 0.32 0.50 f = 10 kHz, 45,54,Propagation Delay Time Duty Cycle = 50% 55

Pulse Width Distortion PWD -0.30 0.02 0.30 16,17

Propagation Delay Difference (tPHL - tPLH) -0.35 0.35 17,18Between Any Two Parts PDD

10% to 90% Rise Time tr 0.1 45

90% to 10% Fall Time tf 0.1

DESAT Sense to 90% VOUT tDESAT(90%) 0.3 0.5 Rg = 10 Ω, 23,56 19Delay Cg = 10 nF

DESAT Sense to 10% VOUT tDESAT(10%) 2.0 3.0 VCC2 - VEE = 30 V 24,28,Delay 46,56

DESAT Sense to Low Level tDESAT(FAULT) 1.8 5 25,47, 20FAULT Signal Delay 56

DESAT Sense to DESAT Low tDESAT(LOW) 0.25 56 21Propagation Delay

RESET to High Level FAULT tRESET(FAULT) 3 7 20 26,27, 22Signal Delay 56

RESET Signal Pulse Width PWRESET 0.1

UVLO to VOUT High Delay tUVLO ON 4.0 VCC2 = 1.0 ms 49 13ramp

UVLO to VOUT Low Delay tUVLO OFF 6.0 14

Output High Level Common |CMH| 15 30 kV/µs TA = 25°C, 50,51, 23Mode Transient Immunity VCM = 1500 V, 52,53

VCC2 = 30 V

Output Low Level Common |CML| 15 30 TA = 25°C, 24Mode Transient Immunity VCM = 1500 V,

VCC2 = 30 V

10

21. This is the amount of time the DESATthreshold must be exceeded beforeVOUT begins to go low, and theFAULT output to go low.

22. This is the amount of time from whenRESET is asserted low, until FAULToutput goes high. The minimumspecification of 3 µs is the guaranteedminimum FAULT signal pulse widthwhen the HCPL-316J is configuredfor Auto-Reset. See the Auto-Resetsection in the applications notes atthe end of this data sheet for furtherdetails.

23. Common mode transient immunity inthe high state is the maximumtolerable dVCM/dt of the commonmode pulse, VCM, to assure that theoutput will remain in the high state(i.e., VO > 15 V or FAULT > 2 V). A100 pF and a 3K Ω pull-up resistor isneeded in fault detection mode.

24. Common mode transient immunity inthe low state is the maximumtolerable dVCM/dt of the commonmode pulse, VCM, to assure that theoutput will remain in a low state (i.e.,VO < 1.0 V or FAULT < 0.8 V).

25. Does not include LED2 currentduring fault or blanking capacitordischarge current.

26. To clamp the output voltage atVCC - 3 VBE, a pull-down resistorbetween the output and VEE isrecommended to sink a static currentof 650 µA while the output is high.See the Output Pull-Down Resistorsection in the application notes at theend of this data sheet if an outputpull-down resistor is not used.

27. The recommended output pull-downresistor between VOUT and VEE doesnot contribute any output currentwhen VOUT = VEE.

28. In most applications VCC1 will bepowered up first (before VCC2) andpowered down last (after VCC2). Thisis desirable for maintaining control ofthe IGBT gate. In applications whereVCC2 is powered up first, it isimportant to ensure that Vin+ remainslow until VCC1 reaches the properoperating voltage (minimum 4.5 V) toavoid any momentary instability atthe output during VCC1 ramp-up orramp-down.

Notes:1. In accordance with UL1577, each

optocoupler is proof tested byapplying an insulation test voltage≥ 4200 Vrms for 1 second (leakagedetection current limit, II-O ≤ 5 µA).This test is performed before the100% production test for partialdischarge (method b) shown in VDE0884 Insulation Characteristic Table,if applicable.

2. The Input-Output Momentary With-stand Voltage is a dielectric voltagerating that should not be interpretedas an input-output continuous voltagerating. For the continuous voltagerating refer to your equipment levelsafety specification or VDEO884Insulation Characteristics Table.

3. Device considered a two terminaldevice: pins 1 - 8 shorted togetherand pins 9 - 16 shorted together.

4. In order to achieve the absolutemaximum power dissipationspecified, pins 4, 9, and 10 requireground plane connections and mayrequire airflow. See the ThermalModel section in the application notesat the end of this data sheet fordetails on how to estimate junctiontemperature and power dissipation. Inmost cases the absolute maximumoutput IC junction temperature is thelimiting factor. The actual powerdissipation achievable will depend onthe application environment (PCBLayout, air flow, part placement,etc.). See the Recommended PCBLayout section in the applicationnotes for layout considerations.Output IC power dissipation isderated linearly at 10 mW/°C above90°C. Input IC power dissipation doesnot require derating.

5. Maximum pulse width = 10 µs,maximum duty cycle = 0.2%. Thisvalue is intended to allow for compo-nent tolerances for designs with IOpeak minimum = 2.0 A. SeeApplications section for additionaldetails on IOH peak. Derate linearlyfrom 3.0 A at +25°C to 2.5 A at+100°C. This compensates forincreased IOPEAK due to changes inVOL over temperature.

6. This supply is optional. Required onlywhen negative gate drive isimplemented.

7. Maximum pulse width = 50 µs,maximum duty cycle = 0.5%.

8. See the Slow IGBT Gate DischargeDuring Fault Condition section in theapplications notes at the end of thisdata sheet for further details.

9. 15 V is the recommended minimumoperating positive supply voltage(VCC2 - VE) to ensure adequatemargin in excess of the maximumVUVLO+ threshold of 13.5 V. For HighLevel Output Voltage testing, VOH ismeasured with a dc load current.When driving capacitive loads, VOHwill approach VCC as IOH approacheszero units.

10. Maximum pulse width = 1.0 ms,maximum duty cycle = 20%.

11. Once VOUT of the HCPL-316J isallowed to go high (VCC2 - VE >VUVLO), the DESAT detection featureof the HCPL-316J will be the primarysource of IGBT protection. UVLO isneeded to ensure DESAT isfunctional. Once VUVLO+ > 11.6 V,DESAT will remain functional untilVUVLO- < 12.4 V. Thus, the DESATdetection and UVLO features of theHCPL-316J work in conjunction toensure constant IGBT protection.

12. See the Blanking Time Controlsection in the applications notes atthe end of this data sheet for furtherdetails.

13. This is the “increasing” (i.e. turn-onor “positive going” direction) ofVCC2 - VE.

14. This is the “decreasing” (i.e. turn-offor “negative going” direction) ofVCC2 - VE.

15. This load condition approximates thegate load of a 1200 V/75A IGBT.

16. Pulse Width Distortion (PWD) isdefined as |tPHL - tPLH| for any givenunit.

17. As measured from VIN+, VIN- to VOUT.18. The difference between tPHL and tPLH

between any two HCPL-316J partsunder the same test conditions.

19. Supply Voltage Dependent.20. This is the amount of time from when

the DESAT threshold is exceeded,until the FAULT output goes low.

11

Performance Plots

Figure 3. IOH vs. Temperature. Figure 5. IOLF vs. VOUT.

Figure 6. VOH vs. Temperature. Figure 7. VOL vs. Temperature. Figure 8. VOH vs. IOH.

Figure 9: VOL vs. IOL. Figure 10. ICC1 vs. Temperature. Figure 11: ICC2 vs. Temperature.

I OH

– O

UT

PU

T H

IGH

CU

RR

EN

T –

A

-401.0

TA – TEMPERATURE – °C

100

1.8

1.6

-20

2.0

0 20 40

1.2

60 80

1.4

I OL

– O

UT

PU

T L

OW

CU

RR

EN

T

-400

TA – TEMPERATURE – °C

100

6

4

-20

7

0 20 40

2

80

VOUT = VEE + 15 V VOUT = VEE + 2.5 V

60

1

3

5

(VO

H -

VC

C)

– H

IGH

OU

TP

UT

VO

LT

AG

E D

RO

P –

V

-40-4

TA – TEMPERATURE – °C

100-20

0

0 20 40 80

IOUT = -650 µA IOUT = -100 mA

60

-3

-2

-1

I CC

2 –

OU

TP

UT

SU

PP

LY

CU

RR

EN

T –

mA

-402.2

TA – TEMPERATURE – °C

100-20

2.6

0 20 40 80

ICC2H ICC2L

60

2.3

2.4

2.5

I OL

F –

LO

W L

EV

EL

OU

TP

UT

CU

RR

EN

T

DU

RIN

G F

AU

LT

CO

ND

ITIO

N –

mA

025

VOUT – OUTPUT VOLTAGE – V

30

175

125

5

200

10 2515

50

100

150

75

20

-40°C 25°C 100°C

VO

L –

OU

TP

UT

LO

W V

OL

TA

GE

– V

-400

TA – TEMPERATURE – °C

100

0.20

0.15

-20

0.25

0 20 40

0.05

60 80

0.10

IOUT = 100 mA

VO

L –

OU

TP

UT

LO

W V

OL

TA

GE

– V

0.10

IOL – OUTPUT LOW CURRENT – A

0.5

6

1.0 1.5 2.0 2.5

3

4

5

2

1

+100°C +25°C -40°C

I CC

1 –

SU

PP

LY

CU

RR

EN

T –

mA

-400

TA – TEMPERATURE – °C

100-20

20

0 20 40 80

ICC1H ICC1L

60

5

10

15

VO

H –

OU

TP

UT

HIG

H V

OL

TA

GE

– V

027.4

IOH – OUTPUT HIGH CURRENT – mA

1.0

28.6

28.4

29.0

0.4

27.8

0.6

28.0

0.2 0.8

27.6

28.2

28.8+100°C +25°C -40°C

Figure 4. IOL vs. Temperature.

12

Figure 12. ICC2 vs. VCC2. Figure 13. ICHG vs. Temperature. Figure 14. IE vs. Temperature.

Figure 15. IC vs. IOUT. Figure 16. DESAT Threshold vs.Temperature.

Figure 17. Propagation Delay vs.Temperature.

Figure 18. Propagation Delay vs.Supply Voltage.

Figure 19. VIN to High PropagationDelay vs. Temperature.

Figure 20. VIN to Low PropagationDelay vs. Temperature.

I CC

2 –

OU

TP

UT

SU

PP

LY

CU

RR

EN

T –

mA

152.35

VCC2 – OUTPUT SUPPLY VOLTAGE – V

30

2.55

2.50

2.60

20

2.40

25

2.45ICC2H ICC2L

I CH

G –

BL

AN

KIN

G C

AP

AC

ITO

R

CH

AR

GIN

G C

UR

RE

NT

– m

A

-40-0.30

TA – TEMPERATURE – °C

100-20

-0.15

0 20 40 8060

-0.25

-0.20

VD

ES

AT

– D

ES

AT

TH

RE

SH

OL

D –

V

-406.0

TA – TEMPERATURE – °C

100-20

7.5

0 20 40 8060

7.0

6.5

TP

– P

RO

PA

GA

TIO

N D

EL

AY

– µ

s

-400.2

TA – TEMPERATURE – °C

100-20

0.5

0 20 40 8060

0.4

0.3

tPHL tPLH

TP

– P

RO

PA

GA

TIO

N D

EL

AY

– µ

s

150.20

VCC – SUPPLY VOLTAGE – V

30

0.40

20 25

0.25

0.30

0.35

tPHL tPLH

PR

OP

AG

AT

ION

DE

LA

Y –

µs

0.25

TEMPERATURE – °C

0.45

0 50 100

0.30

0.35

0.40

VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V

-50

PR

OP

AG

AT

ION

DE

LA

Y –

µs

0.25

TEMPERATURE – °C

0.50

0 50 100

0.40

0.45

VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V

0.30

0.35

-50

I E -V

E S

UP

PL

Y C

UR

RE

NT

– m

A

-400.30

TA – TEMPERATURE – °C

100-20

0.50

0 20 40 80

IEH IEL

60

0.40

0.45

0.35

IC (

mA

)

00

IOUT (mA)

2.0

4

0.5 1.0 1.5

2

3

1-40°C +25°C +100°C

13

Figure 21. Propagation Delay vs. LoadCapacitance.

Figure 22. Propagation Delay vs. LoadResistance.

Figure 23. DESAT Sense to 90% VoutDelay vs. Temperature.

Figure 24. DESAT Sense to 10% VoutDelay vs. Temperature.

Figure 25. DESAT Sense to Low LevelFault Signal Delay vs. Temperature.

Figure 26. DESAT Sense to 10% VoutDelay vs. Load Capacitance.

Figure 27. DESAT Sense to 10% VoutDelay vs. Load Resistance.

Figure 28. RESET to High Level FaultSignal Delay vs. Temperature.

DE

LA

Y –

µs

0.25

TEMPERATURE – °C

0.45

0 100

0.30

0.35

0.40

50-50

DE

LA

Y –

µs

1.0

TEMPERATURE – °C

3.0

0 100

1.5

2.0

2.5

50

VCC2 = 15 V VCC2 = 30 V

-50

DE

LA

Y –

µs

1.6

TEMPERATURE – °C

2.6

0 50 100

2.2

2.4

1.8

2.0

-50

VEE = 0 V VEE = -5 V VEE = -10 V VEE = -15 V

DE

LA

Y –

µs

0.0010

LOAD RESISTANCE – Ω

50

0.0030

10 20 40

0.0015

0.0020

0.0025

30

VCC2 = 15 V VCC2 = 30 V

DE

LA

Y –

µs

4

TEMPERATURE – °C

150

12

0 50 100

6

8

10

VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V

-50

DE

LA

Y –

µs

0.20

LOAD CAPACITANCE – nF

100

0.40

20 40 80

0.25

0.30

0.35

tPLH tPHL

0 60

DE

LA

Y –

µs

0.20

LOAD RESISTANCE – Ω

50

0.40

10 20 40

0.25

0.30

0.35

tPLH tPHL

0 30

DE

LA

Y –

ms

0

LOAD CAPACITANCE – nF

50

0.008

10 20 40

0.002

0.004

0.006

0 30

VCC2 = 15 V VCC2 = 30 V

14

Test Circuit Diagrams

Figure 30. IFAULTL Test Circuit. Figure 31. IFAULTH Test Circuit.

Figure 32. IOH Pulsed Test Circuit. Figure 33. IOL Pulsed Test Circuit.

Figure 34. IOLF Test Circuit. Figure 35. VOH Pulsed Test Circuit.

0.1 µF

+–

10 mAVE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

4.5 V

IFAULT

–+0.4 V

+–

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF5 V

5 V

+–

IFAULT

0.1 µF+–

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF5 V

+–

+–

+–

30 V

30 V

15 V PULSED

0.1 µF

IOUT

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

+–

30 V

30 V

15 V PULSED

0.1 µF

IOUT

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

+–

30 V

30 V

14 V

0.1 µF

IOUT

+–

0.1 µF5 V

0.1 µF+–

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF5 V

+–

+–

30 V

30 V

0.1 µF

VOUT

2A PULSED

15

Figure 36. VOL Test Circuit. Figure 37. ICC1H Test Circuit.

Figure 38. ICC1L Test Circuit. Figure 39. ICC2H Test Circuit.

Figure 40. ICC2L Test Circuit. Figure 41. ICHG Pulsed Test Circuit.

0.1 µF+–

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF5 V

+–

+–

30 V

30 V

0.1 µF

VOUT

100 mA

+–

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

5.5 V

ICC1

+–

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

5.5 V

ICC1

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V

ICC2

0.1 µF

+–

5 V

0.1 µF

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V

ICC2

0.1 µF

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V

ICHG

0.1 µF

+–

5 V

0.1 µF

16

Figure 42. IDSCHG Test Circuit. Figure 43. UVLO Threshold Test Circuit.

Figure 44. DESAT Threshold Test Circuit. Figure 45. tPLH, tPHL, tr, tf Test Circuit.

Figure 46. tDESAT(10%) Test Circuit. Figure 47. tDESAT(FAULT) Test Circuit.

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V

IDSCHG

+–7 V

0.1 µF

+–

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF5 V

+–

SWEEP

0.1 µF

VOUT

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

+–

+–

15 V

15 V

SWEEP

0.1 µF

+–

10 mA

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

5 V

+–

+–

30 V

30 V

VOUT0.1 µF

10 nF

10 Ω

+–

VIN

3 k

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

5 V

+–

+–

30 V

30 V

VOUT

0.1 µF

10 nF

10 Ω3 k

VIN+–

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

5 V

+–

+–

30 V

30 V

0.1 µF

10 nF

10 Ω

3 k

VIN+–

VFAULT

17

Figure 48. tRESET(FAULT) Test Circuit. Figure 49. UVLO Delay Test Circuit.

Figure 50. CMR Test Circuit, LED2 off. Figure 51. CMR Test Circuit, LED2 on.

Figure 52. CMR Test Circuit, LED1 off. Figure 53. CMR Test Circuit, LED1 on.

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1

SCOPE

3 kΩ

100 pF

0.1 µF

10 Ω

0.1 µF

10 nF

VCm

5 V

25 V

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1

SCOPE

3 kΩ

100 pF

0.1 µF

10 Ω

10 nF

VCm

+–

750 Ω

9 V

25 V

5 V

0.1 µF

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1

3 kΩ

100 pF

0.1 µF

10 Ω10 nF

VCm

0.1 µF

SCOPE

25 V

5 V

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1

SCOPE

3 kΩ

100 pF

0.1 µF

10 Ω

10 nF

VCm

0.1 µF

25 V

5 V

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

5 V

+–

+–

30 V

30 V

0.1 µF

10 nF

10 Ω

3 k

STROBE 8 V+

–

VFAULT

VIN HIGH TO LOW

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

0.1 µF

5 V

VOUT 0.1 µF

10 nF

10 Ω3 k

+–

RAMP

18

Figure 56. Desat, VOUT , Fault, Reset Delay Waveforms.

Figure 54. VOUT Propagation Delay Waveforms,Noninverting Configuration.

Figure 55. VOUT Propagation Delay Waveforms, InvertingConfiguration.

VIN+

VOUT

tPHLtPLH

tftr

10%

50%

90%

VIN-

2.5 V 2.5 V

0 V

VIN+

VOUT

tPHLtPLH

tftr

10%

50%

90%

VIN-

2.5 V 2.5 V

5.0 V

VOUT

tRESET (FAULT)

50% (2.5 V)

50%

10%

7 V

50%

tDESAT (FAULT)

VDESAT

FAULT

RESET

tDESAT (90%)

tDESAT (LOW)

tDESAT (10%)

90%

19

Figure 57. ICH Test Circuit. Figure 58. ICH Test Circuit.

Figure 59. ICL Test Circuit. Figure 60. IEH Test Circuit.

Figure 61. IEL Test Circuit.

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V650 µA

0.1 µF

IC

+–

0.1 µF5 V

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V0.1 µF

IC

+–

0.1 µF5 V

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V0.1 µF

IC

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V0.1 µF

IE

+–

0.1 µF5 V

0.1 µF

0.1 µF

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

+–

+–

30 V

30 V0.1 µF

IE

+–

0.1 µF5 V

20

Typical Application/OperationIntroduction to FaultDetection and ProtectionThe power stage of a typical threephase inverter is susceptible toseveral types of failures, most ofwhich are potentially destructiveto the power IGBTs. These failuremodes can be grouped into fourbasic categories: phase and/orrail supply short circuits due touser misconnect or bad wiring,control signal failures due tonoise or computational errors,overload conditions induced bythe load, and component failuresin the gate drive circuitry. Underany of these fault conditions, thecurrent through the IGBTs canincrease rapidly, causingexcessive power dissipation andheating. The IGBTs becomedamaged when the current loadapproaches the saturation currentof the device, and the collector toemitter voltage rises above thesaturation voltage level. Thedrastically increased powerdissipation very quickly overheatsthe power device and destroys it.To prevent damage to the drive,fault protection must beimplemented to reduce orturn-off the overcurrents during afault condition.

A circuit providing fast local faultdetection and shutdown is anideal solution, but the number ofrequired components, boardspace consumed, cost, andcomplexity have until now limitedits use to high performancedrives. The features which thiscircuit must have are high speed,low cost, low resolution, lowpower dissipation, and small size.

The HCPL-316J satisfies thesecriteria by combining a highspeed, high output current driver,high voltage optical isolationbetween the input and output,local IGBT desaturation detectionand shut down, and an opticallyisolated fault status feedbacksignal into a single 16-pin surfacemount package.

The fault detection method,which is adopted in theHCPL-316J, is to monitor thesaturation (collector) voltage ofthe IGBT and to trigger a localfault shutdown sequence if thecollector voltage exceeds apredetermined threshold. A smallgate discharge device slowlyreduces the high short circuitIGBT current to preventdamaging voltage spikes. Beforethe dissipated energy can reachdestructive levels, the IGBT isshut off. During the off state ofthe IGBT, the fault detectcircuitry is simply disabled toprevent false ‘fault’ signals.

The alternative protectionscheme of measuring IGBTcurrent to prevent desaturation iseffective if the short circuitcapability of the power device isknown, but this method will fail ifthe gate drive voltage decreasesenough to only partially turn onthe IGBT. By directly measuringthe collector voltage, theHCPL-316J limits the powerdissipation in the IGBT even withinsufficient gate drive voltage.Another more subtle advantage ofthe desaturation detectionmethod is that power dissipationin the IGBT is monitored, whilethe current sense method relies

on a preset current threshold topredict the safe limit ofoperation. Therefore, an overly-conservative overcurrentthreshold is not needed to protectthe IGBT.

Recommended ApplicationCircuitThe HCPL-316J has bothinverting and non-inverting gatecontrol inputs, an active low resetinput, and an open collector faultoutput suitable for wired ‘OR’applications. The recommendedapplication circuit shown inFigure 62 illustrates a typicalgate drive implementation usingthe HCPL-316J.

The four supply bypasscapacitors (0.1 µF) provide thelarge transient currents necessaryduring a switching transition.Because of the transient nature ofthe charging currents, a lowcurrent (5 mA) power supplysuffices. The desat diode and 100pF capacitor are the necessaryexternal components for the faultdetection circuitry. The gateresistor (10 Ω) serves to limitgate charge current and indirectlycontrol the IGBT collectorvoltage rise and fall times. Theopen collector fault output has apassive 3.3 kΩ pull-up resistorand a 330 pF filtering capacitor.A 47 kΩ pulldown resistor onVOUT provides a more predictablehigh level output voltage (VOH).In this application, the IGBT gatedriver will shut down when a faultis detected and will not resumeswitching until themicrocontroller applies a resetsignal.

Applications Information

21

Figure 62. Recommended Application Circuit.

Description of Operation/TimingFigure 63 below illustrates inputand output waveforms under theconditions of normal operation, adesat fault condition, and normalreset behavior.Normal OperationDuring normal operation, VOUT ofthe HCPL-316J is controlled byeither VIN+ or VIN-, with the IGBTcollector-to-emitter voltage beingmonitored through DDESAT. The

FAULT output is high and theRESET input should be held high.See Figure 63.

Fault ConditionWhen the voltage on the DESATpin exceeds 7 V while the IGBT ison, VOUT is slowly brought low inorder to “softly” turn-off the IGBTand prevent large di/dt inducedvoltages. Also activated is aninternal feedback channel whichbrings the FAULT output low for

Figure 63. Timing Diagram.

the purpose of notifying themicro-controller of the faultcondition. See Figure 63.

ResetThe FAULT output remains lowuntil RESET is brought low. SeeFigure 63. While asserting theRESET pin (LOW), the input pinsmust be asserted for an outputlow state (VIN+ is LOW or VIN- isHIGH). This may beaccomplished either by softwarecontrol (i.e. of themicrocontroller) or hardwarecontrol (see Figures 73 and 74).

VOUT

VDESAT

VIN+

FAULT

RESET

NORMAL OPERATION

FAULT CONDITION

RESET

VIN+

VIN-

VIN-

5 V

0 V

5 V

5 V

7 V

NON-INVERTING CONFIGURED

INPUTS

INVERTING CONFIGURED

INPUTS

+ –

+ –

100 pF

DDESAT

0.1 µF

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

+ –µC

3.3 kΩ

0.1 µF

5 V

330 pF

Rg

VCC2 = 18 V

VEE = -5 V

47 kΩ

3-PHASE OUTPUT

0.1 µF

0.1 µF

VF+ –

Q1

Q2

VCE

+

–

VCE

+

–

100 Ω

22

Slow IGBT GateDischarge During FaultConditionWhen a desaturation fault isdetected, a weak pull-downdevice in the HCPL-316J outputdrive stage will turn on to ‘softly’turn off the IGBT. This deviceslowly discharges the IGBT gateto prevent fast changes in draincurrent that could causedamaging voltage spikes due tolead and wire inductance. Duringthe slow turn off, the large outputpull-down device remains off untilthe output voltage falls below VEE+ 2 Volts, at which time the largepull down device clamps theIGBT gate to VEE.

DESAT Fault DetectionBlanking TimeThe DESAT fault detectioncircuitry must remain disabled fora short time period following theturn-on of the IGBT to allow thecollector voltage to fall below theDESAT theshold. This timeperiod, called the DESATblanking time, is controlled bythe internal DESAT chargecurrent, the DESAT voltagethreshold, and the externalDESAT capacitor. The nominalblanking time is calculated interms of external capacitance(CBLANK), FAULT thresholdvoltage (VDESAT), and DESATcharge current (ICHG) astBLANK = CBLANK x VDESAT / ICHG.The nominal blanking time withthe recommended 100 pFcapacitor is 100 pF * 7 V / 250 µA= 2.8 µsec. The capacitance

value can be scaled slightly toadjust the blanking time, thougha value smaller than 100 pF is notrecommended. This nominalblanking time also represents thelongest time it will take for theHCPL-316J to respond to aDESAT fault condition. If theIGBT is turned on while thecollector and emitter are shortedto the supply rails (switching intoa short), the soft shut-downsequence will begin afterapproximately 3 µsec. If the IGBTcollector and emitter are shortedto the supply rails after the IGBTis already on, the response timewill be much quicker due to theparasitic parallel capacitance ofthe DESAT diode. Therecommended 100 pF capacitorshould provide adequate blankingas well as fault response times formost applications.

Under Voltage LockoutThe HCPL-316J Under VoltageLockout (UVLO) feature isdesigned to prevent theapplication of insufficient gatevoltage to the IGBT by forcingthe HCPL-316J output low duringpower-up. IGBTs typically requiregate voltages of 15 V to achievetheir rated VCE(ON) voltage. Atgate voltages below 13 Vtypically, their on-voltageincreases dramatically, especiallyat higher currents. At very lowgate voltages (below 10 V), theIGBT may operate in the linear

region and quickly overheat. TheUVLO function causes the outputto be clamped wheneverinsufficient operating supply(VCC2) is applied. Once VCC2exceeds VUVLO+ (the positive-going UVLO threshold), theUVLO clamp is released to allowthe device output to turn on inresponse to input signals. AsVCC2 is increased from 0 V (atsome level below VUVLO+), firstthe DESAT protection circuitrybecomes active. As VCC2 isfurther increased (aboveVUVLO+), the UVLO clamp isreleased. Before the time theUVLO clamp is released, theDESAT protection is alreadyactive. Therefore, the UVLO andDESAT FAULT DETECTIONfeatures work together to provideseamless protection regardless ofsupply voltage (VCC2).

23

Behavioral CircuitSchematicThe functional behavior of theHCPL-316J is represented by thelogic diagram in Figure 64 whichfully describes the interaction andsequence of internal and externalsignals in the HCPL-316J.

Input ICIn the normal switching mode, nooutput fault has been detected,and the low state of the faultlatch allows the input signals tocontrol the signal LED. The faultoutput is in the open-collectorstate, and the state of the Resetpin does not affect the control ofthe IGBT gate. When a fault isdetected, the FAULT output and

Figure 64. Behavioral Circuit Schematic.

signal input are both latched. Thefault output changes to an activelow state, and the signal LED isforced off (output LOW). Thelatched condition will persist untilthe Reset pin is pulled low.

Output ICThree internal signals control thestate of the driver output: thestate of the signal LED, as well asthe UVLO and Fault signals. If nofault on the IGBT collector isdetected, and the supply voltageis above the UVLO threshold, theLED signal will control the driveroutput state. The driver stagelogic includes an interlock toensure that the pull-up and pull-down devices in the output stage

are never on at the same time. Ifan undervoltage condition isdetected, the output will beactively pulled low by the 50xDMOS device, regardless of theLED state. If an IGBTdesaturation fault is detectedwhile the signal LED is on, theFault signal will latch in the highstate. The triple darlington ANDthe 50x DMOS device aredisabled, and a smaller 1x DMOSpull-down device is activated toslowly discharge the IGBT gate.When the output drops below twovolts, the 50x DMOS device againturns on, clamping the IGBT gatefirmly to Vee. The Fault signalremains latched in the high stateuntil the signal LED turns off.

VIN+ (1)VIN– (2)

VCC1 (3)

GND (4)

FAULT (6)

RESET (5)

DELAY

R S

Q

FAULT

LED

12 V+

–VCC2 (13)

7 V–

+DESAT (14)

VE (16)250 µA

VC (12)

VOUT (11)

VEE (9,10)50 x

1 x

FA

UL

T

UVLO

24

DESAT Pin ProtectionThe freewheeling of flybackdiodes connected across theIGBTs can have largeinstantaneous forward voltagetransients which greatly exceedthe nominal forward voltage ofthe diode. This may result in alarge negative voltage spike onthe DESAT pin which will drawsubstantial current out of the IC ifprotection is not used. To limitthis current to levels that will notdamage the IC, a 100 ohmresistor should be inserted inseries with the DESAT diode. Theadded resistance will not alter theDESAT threshold or the DESATblanking time.

value of 15 kV/µs. The addedcapacitance does not increase thefault output delay when adesaturation condition isdetected.

Pull-up Resistor on FAULT PinThe FAULT pin is an open-collector output and thereforerequires a pull-up resistor toprovide a high-level signal.

Capacitor on FAULT Pin forHigh CMRRapid common mode transientscan affect the fault pin voltagewhile the fault output is in thehigh state. A 330 pF capacitor(Fig. 66) should be connectedbetween the fault pin and groundto achieve adequate CMOS noisemargins at the specified CMR

Other RecommendedComponentsThe application circuit in Figure62 includes an output pull-downresistor, a DESAT pin protectionresistor, a FAULT pin capacitor(330 pF), and a FAULT pin pull-up resistor.

Output Pull-Down ResistorDuring the output high transition,the output voltage rapidly rises towithin 3 diode drops of VCC2. Ifthe output current then drops tozero due to a capacitive load, theoutput voltage will slowly risefrom roughly VCC2-3(VBE) to VCC2within a period of severalmicroseconds. To limit the outputvoltage to VCC2-3(VBE), a pull-down resistor between the outputand VEE is recommended to sinka static current of several 650 µAwhile the output is high. Pull-down resistor values aredependent on the amount ofpositive supply and can beadjusted according to theformula, Rpull-down =[VCC2-3 * (VBE)] / 650 µA.

16

15

14

13

12

11

10

9

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

HCPL-316J

Rg

RPULL-DOWN

Figure 65. Output Pull-Down Resistor.

Driving with Standard CMOS/TTL for High CMRCapacitive coupling from theisolated high voltage circuitry tothe input referred circuitry is theprimary CMR limitation. Thiscoupling must be accounted forto achieve high CMR perform-ance. The input pins VIN+ andVIN- must have active drivesignals to prevent unwantedswitching of the output underextreme common mode transientconditions. Input drive circuitsthat use pull-up or pull-downresistors, such as open collectorconfigurations, should beavoided. Standard CMOS or TTLdrive circuits are recommended.

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

+ –µC

330 pF

3.3 kΩ

Figure 66. DESAT Pin Protection. Figure 67. FAULT Pin CMR Protection.

16

15

14

13

12

11

10

9

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

100 Ω

HCPL-316J

100 pF

DDESAT

Rg

25

User-Configuration of theHCPL-316J Input SideThe VIN+, VIN-, FAULT andRESET input pins make a widevariety of gate control and faultconfigurations possible,depending on the motor driverequirements. The HCPL-316Jhas both inverting and non-inverting gate control inputs, anopen collector fault outputsuitable for wired ‘OR’applications and an active lowreset input.

Driving Input pf HCPL-316J inNon-Inverting/Inverting ModeThe Gate Drive Voltage Output ofthe HCPL-316J can beconfigured as inverting ornon-inverting using the VIN– andVIN+ inputs. As shown in Figure68, when a non-inverting

configuration is desired, VIN– isheld low by connecting it toGND1 and VIN+ is toggled. Asshown in Figure 69, when aninverting configuration is desired,VIN+ is held high by connecting itto VCC1 and VIN– is toggled.

Figure 68. Typical Input Configuration, Non-Inverting. Figure 69. Typical Input Configuration, Inverting.

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

+ –µC

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

+ –µC

26

gate control signal is acontinuous PWM signal, the faultlatch will always be reset by thenext time the input signal goeshigh. This configuration protectsthe IGBT on a cycle-by-cyclebasis and automatically resetsbefore the next ‘on’ cycle. Thefault outputs can be wire ‘OR’edtogether to alert themicrocontroller, but this signalwould not be used for controlpurposes in this (Auto-Reset)configuration. When theHCPL- 316J is configured forAuto-Reset, the guaranteedminimum FAULT signal pulsewidth is 3 µs.

Resetting Following a FaultConditionTo resume normal switchingoperation following a faultcondition (FAULT output low),the RESET pin must first beasserted low in order to releasethe internal fault latch and resetthe FAULT output (high). Prior toasserting the RESET pin low, theinput (VIN) switching signals mustbe configured for an output (VOL)low state. This can be handleddirectly by the microcontroller orby hardwiring to synchronize theRESET signal with theappropriate input signal. Figure73a shows how to connect theRESET to the VIN+ signal for safeautomatic reset in the non-inverting input configuration.Figure 73b shows how toconfigure the VIN+/RESET signalsso that a RESET signal from themicrocontroller causes the inputto be in the “output-off” state.Similarly, Figures 73c and 73dshow automatic RESET andmicrocontroller RESET safeconfigurations for the invertinginput configuration.

Local Shutdown, Local ResetAs shown in Figure 70, the faultoutput of each HCPL-316J gatedriver is polled separately, andthe individual reset lines areasserted low independently toreset the motor controller after afault condition.

Global-Shutdown, GlobalResetAs shown in Figure 71, whenconfigured for invertingoperation, the HCPL-316J can beconfigured to shutdownautomatically in the event of afault condition by tying theFAULT output to VIN+. For highreliability drives, the opencollector FAULT outputs of eachHCPL-316J can be wire ‘OR’edtogether on a common fault bus,forming a single fault bus forinterfacing directly to the micro-controller. When any of the sixgate drivers detects a fault, thefault output signal will disable allsix HCPL-316J gate driverssimultaneously and therebyprovide protection against furthercatastrophic failures.

Auto-ResetAs shown in Figure 72, when theinverting VIN- input is connectedto ground (non-invertingconfiguration), the HCPL-316Jcan be configured to resetautomatically by connectingRESET to VIN+. In this case, thegate control signal is applied tothe non-inverting input as well asthe reset input to reset the faultlatch every switching cycle.During normal operation of theIGBT, asserting the reset inputlow has no effect. Following afault condition, the gate driverremains in the latched fault stateuntil the gate control signalchanges to the ‘gate low’ stateand resets the fault latch. If the

Figure 71. Global-Shutdown, GlobalReset Configuration.

Figure 72. Auto-Reset Configuration.

Figure 70. Local Shutdown, LocalReset Configuration.

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

+ –µC

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

+ –µC

CONNECT TO OTHER

FAULTS

CONNECT TO OTHER

RESETS

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

+ –µC

27

RC + RG = [VCC2 – VOH – (VEE)] IOH,PEAK

= [4 V – (-5 V)] 0.5 A

= 18 Ω

RC = 8 Ω

See “Power and LayoutConsiderations” section for moreinformation on calculating valueof RG.

Figure 73a. Safe Hardware Reset for Non-InvertingInput Configuration (Automatically Resets for EveryVIN+ Input).

User-Configuration of theHCPL-316J Output SideRG and Optional Resistor RC:The value of the gate resistor RG(along with VCC2 and VEE)determines the maximum amountof gate-charging/dischargingcurrent (ION,PEAK and IOFF,PEAK)and thus should be carefullychosen to match the size of theIGBT being driven. Often it isdesirable to have the peak gatecharge current be somewhat less

Figure 73b. Safe Hardware Reset for Non-Inverting InputConfiguration.

Figure 73d. Safe Hardware Reset for Inverting InputConfiguration (Automatically Resets for Every VIN-Input).

Figure 73c. Safe Hardware Reset for Inverting InputConfiguration.

than the peak discharge current(ION,PEAK < IOFF,PEAK). For thiscondition, an optional resistor(RC) can be used along with RGto independently determineION,PEAK and IOFF,PEAK withoutusing a steering diode. As anexample, refer to Figure 74.Assuming that RG is alreadydetermined and that the designIOH,PEAK = 0.5 A, the value of RCcan be estimated in the followingway:

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

µC

VCC

VIN+/ RESET

FAULT

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

µC

VCC

RESET

FAULT

VIN+

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

µC

VCC

RESET

FAULT

VIN-

VCC

1

2

3

4

5

6

7

8

VIN+

VIN-

VCC1

GND1

RESET

FAULT

VLED1+

VLED1-

HCPL-316J

µC

VCC

RESET

FAULT

VIN-

VCC

28

Figure 75. Current Buffer for Increased Drive Current.

Power/LayoutConsiderationsOperating Within theMaximum Allowable PowerRatings (Adjusting Value ofRG):

When choosing the value of RG,it is important to confirm that thepower dissipation of theHCPL-316J is within themaximum allowable powerrating.

The steps for doing this are:1. Calculate the minimum desired

RG;2. Calculate total power

dissipation in the partreferring to Figure 77.

Figure 74. Use of RC to Further LimitION,PEAK.

Higher Output Current Usingan External Current Buffer:To increase the IGBT gate drivecurrent, a non-inverting currentbuffer (such as the npn/pnpbuffer shown in Figure 75) maybe used. Inverting types are notcompatible with the desaturationfault protection circuitry andshould be avoided. To preservethe slow IGBT turn-off featureduring a fault condition, a 10 nFcapacitor should be connectedfrom the buffer input to VEE anda 10 Ω resistor inserted betweenthe output and the common npn/pnp base. The MJD44H11 /MJD45H11 pair is appropriatefor currents up to 8A maximum.The D44VH10 / D45VH10 pair isappropriate for currents up to 15A maximum.

DESAT Diode and DESATThresholdThe DESAT diode’s function is toconduct forward current,

16

15

14

13

12

11

10

9

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

10 Ω

HCPL-316J

100 pF

RC 8 Ω

10 nF

-5 V15 V

allowing sensing of the IGBT’ssaturated collector-to-emittervoltage, VCESAT, (when the IGBTis “on”) and to block highvoltages (when the IGBT is “off”).During the short period of timewhen the IGBT is switching, thereis commonly a very high dVCE/dtvoltage ramp rate across theIGBT’s collector-to-emitter. Thisresults in ICHARGE (= CD-DESAT xdVCE/dt) charging current whichwill charge the blankingcapacitor, CBLANK. In order tominimize this charging currentand avoid false DESAT triggering,it is best to use fast responsediodes. Listed in the below tableare fast-recovery diodes that aresuitable for use as a DESAT diode(DDESAT). In the recommendedapplication circuit shown inFigure 62, the voltage on pin 14(DESAT) is VDESAT = VF + VCE,(where VF is the forward ONvoltage of DDESAT and VCE is theIGBT collector-to-emittervoltage). The value of VCE whichtriggers DESAT to signal aFAULT condition, is nominally 7V– VF. If desired, this DESATthreshold voltage can bedecreased by using multipleDESAT diodes in series. If n isthe number of DESAT diodesthen the nominal threshold valuebecomes VCE,FAULT(TH) = 7 V – nx VF. In the case of using twodiodes instead of one, diodes withhalf of the total requiredmaximum reverse-voltage ratingmay be chosen.

Max. Reverse VoltagePart Number Manufacturer trr (ns) Rating, VRRM (Volts) Package Type

MUR1100E Motorola 75 1000 59-04 (axial leaded)MURS160T3 Motorola 75 600 Case 403A (surface mount)

UF4007 General Semi. 75 1000 DO-204AL (axial leaded)BYM26E Philips 75 1000 SOD64 (axial leaded)BYV26E Philips 75 1000 SOD57 (axial leaded)BYV99 Philips 75 600 SOD87 (surface mount)

16

15

14

13

12

11

10

9

VE

VLED2+

DESAT

VCC2

VC

VOUT

VEE

VEE

10 Ω

HCPL-316J

100 pF

10 nF

MJD44H11 or D44VH10

4.5 Ω

2.5 Ω

MJD45H11 or D45VH10

15 V -5 V

29

(Average switching energysupplied to HCPL-316J percycle vs. RG plot);

3. Compare the input and outputpower dissipation calculated instep #2 to the maximumrecommended dissipation forthe HCPL-316J. (If themaximum recommended levelhas been exceeded, it may benecessary to raise the value ofRG to lower the switchingpower and repeat step #2.)

As an example, the total inputand output power dissipation canbe calculated given the followingconditions:

• ION, MAX ~ 2.0 A• VCC2 = 18 V• VEE = -5 V• fCARRIER = 15 kHz

Step 1: Calculate RG minimumfrom IOL peak specification:To find the peak charging lOLassume that the gate is initiallycharged the steady-state value ofVEE. Therefore apply thefollowing relationship:

RG = [VOH@650 µA – (VOL+VEE)]

IOL,PEAK

= [VCC2 – 1 – (VOL + VEE )]IOL,PEAK

18 V – 1 V – (1.5 V + (-5 V))2.0 A

= 10.25 Ω

≈ 10.5 Ω (for a 1% resistor)

(Note from Figure 76 that thereal value of IOL may vary fromthe value calculated from thesimple model shown.)

Step 2: Calculate total powerdissipation in the HCPL-316J:

Figure 76. Typical Peak ION and IOFFCurrents vs. Rg (for HCPL-316JOutput Driving an IGBT Rated at600 V/100 A.

Figure 77. Switching Energy Plot forCalculating Average Pswitch (forHCPL-316J Output Driving an IGBTRated at 600 V/100 A).

Ess

(µ

J)

00

Rg (Ω)

200

8

5

9

50 100

3

150

1

4

7

Ess (Qg = 650 nC)

6

2

SWITCHING ENERGY vs. GATE RESISTANCE (VCC2 / VEE2 = 25 V / 5 V

I ON

, IO

FF

(A)

0-3

Rg (Ω)

200

3

1

4

20 100

-1

140

-2

0

2

IOFF (MAX.)

MAX. ION, IOFF vs. GATE RESISTANCE (VCC2 / VEE2 = 25 V / 5 V

40 60 80 120 160 180

ION (MAX.)

The HCPL-316J total powerdissipation (PT) is equal to thesum of the input-side power (PI)and output-side power (PO):

PT = PI + PO

PI = ICC1 * VCC1

PO = PO(BIAS) + PO,SWTICH

= ICC2 * (VCC2–VEE ) + ESWITCH * fSWITCH

where, PO(BIAS) = steady-state power dissipation in the HCPL-316J due to biasing the device.

PO(SWITCH) = transient power dissipation in the HCPL-316J due to charging and discharging power device gate.

ESWITCH = Average Energy dissipated in HCPL-316J due to switching of the power device over one switching cycle (µJ/cycle).

fSWITCH = average carrier signal frequency.

For RG = 10.5, the value readfrom Figure 77 is ESWITCH =6.05 µJ. Assume a worst-caseaverage ICC1 = 16.5 mA (which isgiven by the average of ICC1H andICC1L ). Similarly the averageICC2 = 5.5 mA.

PI = 16.5 mA * 5.5 V = 90.8 mW

PO= PO(BIAS) + PO,SWITCH

= 5.5 mA * (18 V – (–5 V)) + 6.051 µJ * 15 kHz

= 126.5 mW + 90.8 mW

= 217.3 mW

Step 3: Compare thecalculated power dissipationwith the absolute maximumvalues for the HCPL-316J:

For the example,

PI = 90.8 mW < 150 mW(abs. max.) OK

PO= 217.3 mW < 400 mW(abs. max.) OK

Therefore, the power dissipationabsolute maximum rating has notbeen exceeded for the example.

Please refer to the followingThermal Model section for anexplanation on how to calculatethe maximum junctiontemperature of the HCPL-316Jfor a given PC board layoutconfiguration.

30

Figure 78. HCPL-316J Thermal Model.

Tji = junction temperature of input side ICTjo = junction temperature of output side ICTP4 = pin 4 temperature at package edgeTP9,10 = pin 9 and 10 temperature at package edgeθI4 = input side IC to pin 4 thermal resistanceθI9,10 = output side IC to pin 9 and 10 thermal resistanceθ4A = pin 4 to ambient thermal resistanceθ9,10A = pin 9 and 10 to ambient thermal resistance

*The θ4A and θ9,10A values shown here are for PCB layouts shown in Figure 78 withreasonable air flow. This value may increase or decrease by a factor of 2 dependingon PCB layout and/or airflow.

TP4 TP9,10

θ4A = 50°C/W* θ9,10A = 50°C/W*

TA

θi4 = 60°C/W θO9,10 = 30°C/W

Tji Tjo

Thermal ModelThe HCPL-316J is designed todissipate the majority of the heatthrough pins 4 for the input ICand pins 9 and 10 for the outputIC. (There are two VEE pins onthe output side, pins 9 and 10,for this purpose.) Heat flowthrough other pins or through thepackage directly into ambient areconsidered negligible and notmodeled here.

In order to achieve the powerdissipation specified in theabsolute maximum specification,it is imperative that pins 4, 9, and10 have ground planes connectedto them. As long as the maximumpower specification is notexceeded, the only other limita-tion to the amount of power onecan dissipate is the absolutemaximum junction temperaturespecification of 125°C. Thejunction temperatures can becalculated with the followingequations:

Tji = Pi(θi4 + θ4A) + TATjo = Po(θo9,10 + θ9,10A) + TA

where Pi = power into input ICand Po = power into output IC.

Since θ4A and θ9,10A aredependent on PCB layout andairflow, their exact number maynot be available. Therefore, amore accurate method of calcu-lating the junction temperature iswith the following equations:

Tji = Piθi4 + TP4Tjo = Poθo9,10 + TP9,10

These equations, however,require that the pin 4 and pins9,10 temperatures be measuredwith a thermal couple on the pinat the HCPL-316J package edge.

From the earlier powerdissipation calculationexample:

Pi = 90.8 mW, Po = 314 mW, TA= 100°C, and assuming thethermal model shown in Figure77 below.

Tji = (90.8 mW)(60°C/W+ 50°C/W) + 100°C = 110°C

Tjo = (240 mW)(30°C/W+ 50°C/W) + 100°C = 119°C

both of which are within theabsolute maximum specificationof 125°C.

If we, however, assume a worstcase PCB layout and no air flowwhere the estimated θ4A andθ9,10A are 100°C/W. Then thejunction temperatures become

Tji = (90.8 mW)(60°C/W+ 100°C/W) + 100°C = 115°C

Tjo = (240 mW)(30°C/W+ 100°C/W) + 100°C = 131°C

The output IC junctiontemperature exceeds the absolutemaximum specification of 125°C.In this case, PCB layout andairflow will need to be designedso that the junction temperatureof the output IC does not exceed125°C.

If the calculated junctiontemperatures for the thermalmodel in Figure 78 is higher than125°C, the pin temperature forpins 9 and 10 should bemeasured (at the package edge)under worst case operatingenvironment for a more accurateestimate of the junctiontemperatures.

31

Printed Circuit BoardLayout ConsiderationsAdequate spacing should alwaysbe maintained between the highvoltage isolated circuitry and anyinput referenced circuitry. Caremust be taken to provide thesame minimum spacing betweentwo adjacent high-side isolatedregions of the printed circuitboard. Insufficient spacing willreduce the effective isolation andincrease parasitic coupling thatwill degrade CMR performance.

The placement and routing ofsupply bypass capacitors requiresspecial attention. During switch-ing transients, the majority of thegate charge is supplied by the

bypass capacitors. Maintainingshort bypass capacitor tracelengths will ensure low supplyripple and clean switchingwaveforms.

Ground Plane connections arenecessary for pin 4 (GND1) andpins 9 and 10 (VEE) in order toachieve maximum powerdissipation as the HCPL-316J isdesigned to dissipate the majorityof heat generated through thesepins. Actual power dissipationwill depend on the applicationenvironment (PCB layout, airflow, part placement, etc.) Seethe Thermal Model section for

details on how to estimatejunction temperature.

The layout examples below havegood supply bypassing andthermal properties, exhibit smallPCB footprints, and have easilyconnected signal and supplylines. The four examples coversingle sided and double sidedcomponent placement, as well asminimal and improvedperformance circuits.

Figure 79. Recommended Layout(s).

Figure 80. Minimum LED Skew for Zero Dead Time. Figure 81. Waveforms for Dead Time Calculation.

tPHLMAXtPLHMIN

PDD* MAX = (tPHL- tPLH)MAX = tPHLMAX - tPLHMIN

*PDD = PROPAGATION DELAY NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

VOUT1

VIN+2

VOUT2

VIN+1

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

tPLHMIN

MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHLMAX - tPHLMIN) + (tPLHMAX - tPLHMIN) = (tPHLMAX - tPLHMIN) – (tPHLMIN - tPLHMAX) = PDD*MAX – PDD*MIN

*PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

VOUT1

VIN+2

VOUT2

VIN+1

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

tPHLMINtPHLMAX

tPLHMAX

= PDD*MAX(tPHL-tPLH)MAX

System ConsiderationsPropagation Delay Difference(PDD)The HCPL-316J includes aPropagation Delay Difference(PDD) specification intended tohelp designers minimize “deadtime” in their power inverterdesigns. Dead time is the timeperiod during which both thehigh and low side powertransistors (Q1 and Q2 inFigure 62) are off. Any overlap inQ1 and Q2 conduction will resultin large currents flowing throughthe power devices between thehigh and low voltage motor rails,a potentially catastrophic condi-tion that must be prevented.

To minimize dead time in a givendesign, the turn-on of theHCPL-316J driving Q2 should be

delayed (relative to the turn-offof the HCPL-316J driving Q1) sothat under worst-case conditions,transistor Q1 has just turned offwhen transistor Q2 turns on, asshown in Figure 80. The amountof delay necessary to achieve thiscondition is equal to the maxi-mum value of the propagationdelay difference specification,PDDMAX, which is specified to be400 ns over the operatingtemperature range of -40°C to100°C.

Delaying the HCPL-316J turn-onsignals by the maximumpropagation delay differenceensures that the minimum deadtime is zero, but it does not tell adesigner what the maximum dead

time will be. The maximum deadtime is equivalent to thedifference between the maximumand minimum propagation delaydifference specifications asshown in Figure 81. Themaximum dead time for theHCPL-316J is 800 ns (= 400 ns -(-400 ns)) over an operatingtemperature range of -40°C to100°C.

Note that the propagation delaysused to calculate PDD and deadtime are taken at equal tempera-tures and test conditions sincethe optocouplers under consider-ation are typically mounted inclose proximity to each other andare switching identical IGBTs.

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