HBD FEM

• the block diagram

• preamp – FEM cable

• Status

• Stuffs need to be decided….

Global Organization

• 32 channels per FEM• 2 VME-style 6U crates for the detector

– Custom dataway (backplane)– 21 slots per crate, 1U=1.75 inch– 20 FEM per crate

• 20*32*2= 1280 channels

– FEM cable plug in the front of FEM– Trigger primitives output from the back

• 1 local trigger crate(?)

differential receiver

FEM

8 channels65 MHZ 12 bits

Serial ADC(6X beam

clock)

ALTERA 10K30FPGA

(L1 delay buffer, data format, generating L1

trigger output etc.)

32 channelsSignals

( 12 samples ADC data per channel per

L1 trigger)

preamp

OutputTo

DCM60MHz(5 FEMs per fiber)

4 bits per

Channel(1.28 Gbits)

System Block Diagram

720 MHz Serial data

We will use half of the ADC range (i.e. + +, - -)Assume 8 bits for 1 e-, 8 e- will reach full scale.

Cable (connector) choice

3M shield twist pair cable1785/34 (17 pair 16 signal + grounds)

connector 3431

size = 62.6mm + 9.4mm(ejector) 80 signals => 36 cm

3M MDR (Mini D Ribbon) cablesNeed to have custom build

50 pins cable example 14150-ezbb-xxx-0lcconnector

40 position 10226-1210 VE 47.1mm for 16 pairs

235.5 mm for 80pairs. 25mm for power and test pulse.

Detector has 8 panels

Readout both side of the panel

Panel size 23x26 cm

(possible) cable pinout

Pin 40 pair 16+Pin 20 pair 16-Pin 39 (pair 16+15) drainPin 19 pair 15+Pin 38 pair 15-Pin 18 pair 14+Pin 37 pair 14-Pin 17 (pair 14+13) drainPin 36 pair 13+Pin 16 pair 13-Pin 35 pair 12+Pin 15 pair 12-Pin 34 (pair 12+11) drainPin 14 pair 11+Pin 33 pair 11-Pin 13 pair 10+Pin 32 pair 10-Pin 12 (pair 10+9) drainPin 31 pair 9+Pin 11 pair 9-

Pin 30 pair 8+Pin 10 pair 8-Pin 29 (pair 8+7) drainPin 9 pair 7+Pin 28 pair 7-Pin 8 pair 6+Pin 27 pair 6-Pin 7 (pair 6+5) drainPin 26 pair 5+Pin 6 pair 5-Pin 25 pair 4+Pin 5 pair 4-Pin 24 (pair 4+3) drainPin 4 pair 3+Pin 23 pair 3-Pin 3 pair 2+Pin 22 pair 2-Pin 2 (pair 2+1) drainPin 21 pair 1+Pin 1 pair 1-

16 differential shielded twisted pairs (100 ohms).

Overall shield is connected to the chassis

Need to be revised.

3M only have (20 pairs and 6 drain) cable..

Status• Major Block of the FPGA code is done

– (serial download, ADC data receiving, data alignment, trigger output generators (16 threshold per channel) etc.)

• Work out internal serial download protocol• Work out clock distribution/generators

• 4X beam clock from GTM• 4X beam clock go to all FEM• 1X, 6X, 8X beam clocks generated inside the FEM

• We ask 3M to work out budgetary code for the detector ->FEM cable– 2 piece prototype, 100 piece production

• Working on backplane connectors– High speed signal pass through connectors.

• Working on the ARCNET replacement chipset– For slow download

• Start to look at new DCM issues– The FEM only can be readout through new protocol/optical chipsets

• Proceed with prototype component purchasing and layout before end of the year

Issue need to be addressed

• Cable choice

• Channel count

• How many bits per channel is really needed in L1

• What L1 trigger board suppose to do