ECE 368 Basic VHDL Shantanu Dutt UIC Acknowledgement: Extracted from RASSP
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Transcript of Hasan Arslan and Shantanu Dutt Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University...
Hasan Arslan and Shantanu DuttHasan Arslan and Shantanu Dutt
Electrical & Computer Eng.Electrical & Computer Eng.
University of Illinois at ChicagoUniversity of Illinois at Chicago
DATE 2006DATE 2006
Efficient Timing-Driven Incremental Routing for VLSI Circuits Using
DFS and Localized Slack-Satisfaction Computations
Dutt & Arslan, UIC
OutlineOutline IntroductionIntroduction
• Importance of Incremental RoutingImportance of Incremental Routing• Previous WorkPrevious Work• Our GoalsOur Goals
A DFS-Based TD Incr Routing A DFS-Based TD Incr Routing Algorithm (TIDE) Algorithm (TIDE) • Previous work on global TD routingPrevious work on global TD routing• Global Routing with slack tolerance Global Routing with slack tolerance
conceptsconcepts• Detailed Routing with DFS-based B&RDetailed Routing with DFS-based B&R
Experimental ResultsExperimental Results ConclusionConclusion
Dutt & Arslan, UIC
Incremental RoutingIncremental Routing
• After chip layout is completedAfter chip layout is completed Time/noise/thermal violationTime/noise/thermal violation One or more optimization metrics (speed/power/area) One or more optimization metrics (speed/power/area)
unsatisfactoryunsatisfactory• Need correcting changes to the circuit/systemNeed correcting changes to the circuit/system
Engineering Change Order (ECO) processEngineering Change Order (ECO) process• Enormous resources and time already spentEnormous resources and time already spent• Time to meet market requirementsTime to meet market requirements• Most ECOs lead to a requirement of routing Most ECOs lead to a requirement of routing
changes after various design changes at earlier changes after various design changes at earlier levelslevels
• The ECO could also be at the routing levelThe ECO could also be at the routing level• Incremental routing & interconnects criticalIncremental routing & interconnects critical
Need a time-efficient & effective TD-incremental Need a time-efficient & effective TD-incremental routing algorithmrouting algorithm
Dutt & Arslan, UIC
Incremental Routing ProblemIncremental Routing Problem• Set of existing routed nets Set of existing routed nets R = E – D, ER = E – D, E = =
original nets before ECO, original nets before ECO, DD = deleted nets = deleted nets• Set of new nets Set of new nets SS (resulting from correcting re-(resulting from correcting re-
synthesis at different levels of the VLSI design synthesis at different levels of the VLSI design flow)flow)
Quality metricsQuality metrics• Time-efficient near-optimal incr solns for Time-efficient near-optimal incr solns for SS
subject to given constraints (slack satisfaction, subject to given constraints (slack satisfaction, crosstalk bounding, etc.)crosstalk bounding, etc.)
• Minimal changes to previous routing results Minimal changes to previous routing results • Complete incr routing in the available metal Complete incr routing in the available metal
layers (if such a soln exists)layers (if such a soln exists)
Incremental Routing (Cont.)Incremental Routing (Cont.)
Dutt & Arslan, UIC
Prior Work on Incremental RoutingPrior Work on Incremental Routing
1)1) Emmert and BhatiaEmmert and Bhatia, , “Incremental Routing in FPGA”,“Incremental Routing in FPGA”, IEEE IEEE Int. ASIC Conference, 1998Int. ASIC Conference, 1998..
2)2) Cong and SarrafzadehCong and Sarrafzadeh, , “Incremental Physical Design”,“Incremental Physical Design”, ISPD 2000ISPD 2000..
3)3) Dutt, Shanmugavel and TrimbergerDutt, Shanmugavel and Trimberger, , “Efficient Incremental “Efficient Incremental Rerouting for Fault Reconfiguration in FPGAs”,Rerouting for Fault Reconfiguration in FPGAs”, ICCAD 1999ICCAD 1999..
4)4) Dutt, Verma and ArslanDutt, Verma and Arslan “A Search-Based Bump and Refit “A Search-Based Bump and Refit Approach to Incremental Routing for ECO Applications in Approach to Incremental Routing for ECO Applications in FPGAs”,FPGAs”, TODAES 2002TODAES 2002
5)5) Xiang, Chao, Wong Xiang, Chao, Wong “An ECO Algorithm for Eliminating “An ECO Algorithm for Eliminating Crossalk Violations”,Crossalk Violations”, ISPD 2004 ISPD 2004
6) S. Raman, et al., 6) S. Raman, et al., “A Timing-Constrained Incremental “A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs “,Routing Algorithm for Symmetrical FPGAs “, DATE 1996 DATE 1996
7) H. Arslan and S. Dutt, 7) H. Arslan and S. Dutt, “A Depth-First Search Controlled “A Depth-First Search Controlled Gridless incremental routing Algorithm for VLSI Circuits”Gridless incremental routing Algorithm for VLSI Circuits”, , ICCD 2004.ICCD 2004.
No work on TD incremental routing for ASICsNo work on TD incremental routing for ASICs
Dutt & Arslan, UIC
Emmert-BhatiaEmmert-Bhatia (ASIC’98) (ASIC’98)
Nets connected to faulty PLB, deleted and reroutedNets connected to faulty PLB, deleted and rerouted StandardStandard single-net routing mode (global then single-net routing mode (global then
detailed)detailed) Do not perturb or move existing netsDo not perturb or move existing nets
Standard Net Routing :Standard Net Routing : Route new nets without Route new nets without perturbing existing netsperturbing existing nets
Rip & Reroute :Rip & Reroute : If some nets cannot be routed, rip- If some nets cannot be routed, rip-up “blocking” existing nets. Reroute the ripped up up “blocking” existing nets. Reroute the ripped up netsnets..
Cong-SarrafzadehCong-Sarrafzadeh (ISPD’00) (ISPD’00)
Prior Work (Cont.)
Dutt & Arslan, UIC
Our GoalsOur Goals TD-incremental routing for VLSI (ASIC) TD-incremental routing for VLSI (ASIC)
circuitscircuits Address quality metrics of incr. routing Address quality metrics of incr. routing
and satisfy constraintsand satisfy constraints Satisfy slack constraints on new and existing nets Satisfy slack constraints on new and existing nets
that may be affected by new net routingthat may be affected by new net routing Fast near-WL,via-optimal incr solutionsFast near-WL,via-optimal incr solutions Min. changes to existing routing-bounded WL, via Min. changes to existing routing-bounded WL, via
increaseincrease Complete incr routing in the available metal layersComplete incr routing in the available metal layers
—aggressive exploration of routing space within —aggressive exploration of routing space within above constraintsabove constraints
Dutt & Arslan, UIC
n1n2
n3
n2
Adj-via
Adj-via
nj
Bumped seg.
High-Level ApproachHigh-Level Approach
Global Routing of new net based on:1) A new iterative slack-satisfaction algorithm IntAl for connecting next pin on the netbased on local slack tolerances2) Congestion + WL + efficiency-basedmin-cost on a grid-graph for each 2-pin path
Detailed routing of new net based on:1) WL + via + bumping (degree of bumped net) min-cost path for each global route 2) Constraint-satisfying DFS-based partial-B&R process for “overlapped” or “bumped”existing nets so that: a) slacks not violated,b) WL-increment bounded
V1
V0
Vm
Vj
Vi V2
V2
Dutt & Arslan, UIC
Our Approach – TD Global RoutingOur Approach – TD Global Routing• In an iterative connections of pins on routing tree, most imp.Q: Where to connect the next pin for slack-satisfaction of allpins and min-WL? v0
v1
v2
v3
vu
• Simplified rule of thumb:• Closer is the connection to CC, more interconnect sharing there is w/ partial tree T & less additional delay seen by other sinks. But more “baggage” (accumulated delay) for new pin vu.• Higher up and away from CC the connection is, lesser is the accumulated delay of T seen by vu, but less sharing and more delay seen by other sinks due to more wire-cap load
• Classic Prim-Dijkstra tradeoffs discussed in [Alpert et al., TCAD’95]• Optimal solution (even just slack-satisfying soln. somewhere in between• No one has solved it exactly (satisfying all slacks) or optimally (w/ min-WL)• We provide a near-min-WL all-slack-satisfying solution here
CC
(closestconnection)
vi
New pin
Dutt & Arslan, UIC
Various Approaches to TD Global RoutingVarious Approaches to TD Global Routing
• In [Boese, et al., TCAD-95] (SERT/ERT algorithm):– The delay on any sink is a concave function of lx the distance from CC of the connection point– Same for weighted sum of all sink delays (obj. func)—min. @ either vi or CC– Choose vi or CC based on min-WL
v0
v1
v2
v3
vuCC
vi
lx
vx
New pin
CCvi
del
ay
lx
• Does not solve the core TD problem of slack satisfaction
Dutt & Arslan, UIC
Various Approaches to TD Global Routing Various Approaches to TD Global Routing (contd)(contd)
• In [Hou & Sapatnekar, ISPD’98] (MVERT):– Constraint satisfaction of all sinks vk is explicitly considered:d(vk) - slack(vk) <= 0 (LHS is also concave); uses non-Hanan points– The technique involves navigating max[slack(vk)– d(vk)] via intersection points of the various concave curves– Use binary search to find min-WL point for constr. satisfaction
v0
v1
v2
v3
vuCC
vi
lx
vx
New pin
CCvi
del
ay
- sl
ack
lx
0
vk
Optimal slack-satisfying conn.point
Max envelope
• Time complex— , where k = # sink pins (our analysis)• Misses some slack satisfaction solutions from initial SERT/ERT handoff
Dutt & Arslan, UIC
Various Approaches to TD Global Routing Various Approaches to TD Global Routing (contd)(contd)
• As our competitor, we consider a mix of SERT [Boese, TCAD’95] and SOAR [Wang and Kuh, MCMC’97] (SERT/SOAR):
– Check if connection to CC satisfies all slacks– Else make a connection to driver v0
– Rationale: If connection to CC violates slack to vu, then this is most likely due to the “baggage” delay of shared interconnects. This can be avoided maximally by routing directly to vo
Classical Prim-Dijkstra tradeoff Fast v0
v1
v2
v3
vuCC
vi
lx
vx
New pin
Dutt & Arslan, UIC
Our Approach to TD Global RoutingOur Approach to TD Global Routing• Exact slack satisfaction of all sinks in “constant” time by checking satisfaction of derived slacks (called tolerances) as a function of lx ofonly 3 classes of sinks:
– vu
– sinks in T(CC), where T(u) is routing subtree rooted at u (e.g., v3)– sinks below T(vi)/T(CC) (e.g., v1, v2)
• For this we need tolerance concepts discussed nextv0
v1
v2
v3
vuCC
vi
lx
vx
New pin
Derivedtolerances
Dutt & Arslan, UIC
Elmore Delay ModelElmore Delay Modelv0
vi
vj
lij
Cdnj
• D(vj) = D(vi) + (r.c.l2ij)/2 + r.lij.Cdn
j
• Cdnj = gate + wiring capacitance of
subtree rooted at vj
• If vj is a sink pin, Cdnj = Cg(vj)
[gate cap of vj]
• r, c = unit wire cap, res• Has good fidelity
Dutt & Arslan, UIC
( ) maxdel jTol v delay increase D
jcan be tolerated at v
( ) maxdel jTol v delay increase D
( ) maxdel jTol v delay increase D
( )
( ) min ( )m j
del j del mv children v
Tol v Tol v
Tolerance Concepts—Delay ToleranceTolerance Concepts—Delay Tolerance
Dutt & Arslan, UIC
( ) max .
j
j
cap j
v
v
Tol v cap incr
downstream in the subtree T such that
sink pin on T will not be violated
31
1 3( ) ( )j j
upupvv
cap capup upv v
RRTol v Tol v
R R
( )( ) min ( ) m
m jj
upv
cap j cap m upv children vv
RTol v Tol v
R
Tolerance Concepts—Capacitance Tolerance Concepts—Capacitance TolerancesTolerances
Min
= upstreamres. from vo
To vj
Dutt & Arslan, UIC
Intersection
Vi
Global Routing: Connecting a New Pin—Global Routing: Connecting a New Pin—Interval Intersection (IntAl) AlgorithmInterval Intersection (IntAl) Algorithm
V2 V3 V4
Vj
Set2
CC
Vu
Δcap
x
V’
V6
V5
Set1
V0 Set3
V1
Optimalpoint
h(x) = c.x + l <= 0
g(x)= -r.c.x2+ex+m <= 0
• Determine valid intervals for each inequality• If all intervals are non-empty, take intersection• If intersection non-empty
– then take bottom point of intersection as min-WL slack-satisfaction point– else prune tree and repeat process with next nearest pruned-tree branch
f(x)= -r.c.x2+bx+d <= 0
IntA
l Alg
ori
thm
Theorem 1: The tree truncation method in the IntAl algorithm will always find a slack-satisfying connection point for new pin nearest valid edge, if one exists, of the partial routing tree T
Updates of tolerances done on an as-needed basis. E.g., change in delay at a sink pin due to re-routing is only propagated to ancestors’ tolerances. Later when a node’s tolerance is needed, it may not be updated but this is accomplished by scanning all its ancestors.
(h) time complexity per re-routing of T, h is T’s height
Properties
Tolcap(v’) = Tolcap(vj).Rup(vj)/Rup(v’)
Concave functionx
del
ay
Dutt & Arslan, UIC
Timing-Driven Incremental Detailed Timing-Driven Incremental Detailed RoutingRouting
If a portion of net nIf a portion of net nii is overlapped is overlapped Length of overlapped portion might be increased.Length of overlapped portion might be increased. Increase the capacitance.Increase the capacitance. Slack of sink pins might be violated.Slack of sink pins might be violated.
Possible overlapping:Possible overlapping: With leaf interconnectWith leaf interconnect Interior edgeInterior edge Steiner pointSteiner point
Our goal: Our goal: Satisfy source to sink delay requirement for all sink pins (slack)Satisfy source to sink delay requirement for all sink pins (slack)
Slack:Slack: The amount of delay can be added on a net connecting the sink pinThe amount of delay can be added on a net connecting the sink pin
without increasing the maximum delay requirement of that sink pin.without increasing the maximum delay requirement of that sink pin.
Detailed routing of new net based on:1) WL + via + bumping min-cost path foreach global route 2) Constraint-satisfying DFS-based partial-B&R process for “overlapped” or “bumped”existing nets so that: a) slacks not violated,b) WL-increment bounded
n1n2
n3
n2
Adj-via
Adj-via
nj
Bumped seg.
Dutt & Arslan, UIC
TD Incr. Detailed Routing—Overlapping a Leaf TD Incr. Detailed Routing—Overlapping a Leaf InterconnectInterconnect
Self Test:Self Test:
Downstream Test:Downstream Test:
Upstream TestUpstream Test
2 2( ) ( )D v S v
( )cap jcap Tol v
_ ( )cap jcap Anc Tol v
n2
n2
Δcap
V6
V5 V1
V2
Vj
V4
Vi
TV0
n1
Dutt & Arslan, UIC
TD Incr. Detailed Routing—Overlapping an TD Incr. Detailed Routing—Overlapping an Interior InterconnectInterior Interconnect
1) D(v’j) <= Toldel(v’j) = Toldel(vj)2) For each child vk (sink pin or
Steiner node):• D(vk) <= Toldel(vk) [e.g., D(v2) <= Toldel(v2), D(vm) <= Toldel(vm) ]
D(v’j)
D(v2)
D(vm)
Do these checks only
V2
Vm
Vj
n2
n2
Vi
V’’j
V6
TV0
n1
V3 V4 V5
V’j
Δcap
Upstream Test:Upstream Test:
Downstream Test:Downstream Test:
_ ( )cap jcap Anc Tol v i
Dutt & Arslan, UIC
(a) (b) (c)(a) (b) (c)(b) moving v(b) moving vjj upwards will increase capacitance and upwards will increase capacitance and
resistanceresistance(c) moving v(c) moving vjj downwards decrease cap. change Steiner node downwards decrease cap. change Steiner node
V1 V2 V3 V4
Vj Vk
n2
n2
V5 T
Vn n1
V1 V2 V3 V4
n2
n2
V5 T
Vn n1
Δcap Δcap
V’j
V1 V2 V3 V4
Vj
V’k
n2
n2
V5 T
Vn n1
V’j
TD Incr. Detailed Routing—Overlapping Steiner TD Incr. Detailed Routing—Overlapping Steiner PointPoint
Vi Vi Vi
Dutt & Arslan, UIC
Constraint Satisfying DFS-Controlled Constraint Satisfying DFS-Controlled Routing with Partial B&RRouting with Partial B&R
n1
njn2
n3
n1..b-segn3..h1
n3. .v
1 nj
n1.b-seg
nj
n2..h1
Pi= i-via path is explored
n2..h2n1..b-seg
n2.pinor
obs
P1
n1..b-seg
n2..h2 n2.h2
P2
DFS retractions:• pin or logic as obstacles• ancestor nets bumped• slack violation of current net• WL of currently re-routed net excessive• other constraints
• Exploring a richer solution space viapartial bump-&-reroute (B&R) of existing nets• Constraint of minimal effect on B&R’ednets need to be satisfied: slack staisfaction, min-WL
• Adapted from [Arslan & Dutt, ICCD’04]
Dutt & Arslan, UIC
n1
njn2
n3
n3..h1
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
n2..h1
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n2..h2
n1..b-seg
n2..h2
DFS-Controlled Routing with Partial DFS-Controlled Routing with Partial B&RB&R
Dutt & Arslan, UIC
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
n2..h1
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n1..b-seg
n2..h2
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3..h1
n3. .v
1
n2..h2
DFS-Controlled Routing with Partial DFS-Controlled Routing with Partial B&RB&R
Dutt & Arslan, UIC
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
n2..h1
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n1..b-seg
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3.h1
P2-P3
n2..h2
obs
P1
obs oranc.n1 or
anc.nj
P2-P4
n3..h1
n3. .v
1
n2..h2
DFS-Controlled Routing with Partial DFS-Controlled Routing with Partial B&RB&R
Dutt & Arslan, UIC
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n1..b-seg
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3.h1
P2-P3
obs
P1
obs oranc.n1 or
anc.nj
P2-P4
n3..h1
n3. .v
1
n2..h2
n2.h1
P2
n2..h1
obs
P1
n1..b-seg
DFS-Controlled Routing with Partial DFS-Controlled Routing with Partial B&RB&R
Dutt & Arslan, UIC
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3.h1
P2-P3
obs
P1
obs oranc.n1 or
an.nj
P2-P4
n3..h1
n3. .v
1
n2..h2
n2.h1
P2
obs
P1
VGL
P2
n2..h1
DFS-Controlled Routing with Partial DFS-Controlled Routing with Partial B&RB&R
• net lenghts and # of vias of all modified/bumped nets unchanged
Dutt & Arslan, UIC
Benchmark CircuitsBenchmark Circuits
Benchmarks:Benchmarks: 10 circuits ranging from 1643 to 10435 nets & 7200 to 47520 10 circuits ranging from 1643 to 10435 nets & 7200 to 47520
pinspins Base 2x2 tile of Mcc1 bench. is repl. with diff. cell sizes and diff. # Base 2x2 tile of Mcc1 bench. is repl. with diff. cell sizes and diff. #
of pinsof pins Nets randomly generated & routed using SERT/SOARNets randomly generated & routed using SERT/SOAR Net distribution: 2-pin: 30%, 3-4 pins: each 20%, 5 pins: 10%, 6-7 Net distribution: 2-pin: 30%, 3-4 pins: each 20%, 5 pins: 10%, 6-7
pins: each 5%, 8-10 pins: each 2%, 11-14 pins: each 1%pins: each 5%, 8-10 pins: each 2%, 11-14 pins: each 1% Pin slacks normally distributed in range [0,5% max delay on net]Pin slacks normally distributed in range [0,5% max delay on net] Ran on 2.6 Ghz Pentium Linux machines, 1GB RAMRan on 2.6 Ghz Pentium Linux machines, 1GB RAM
Simulation: Randomly deleted 10% nets & rand. gen. 10% new Simulation: Randomly deleted 10% nets & rand. gen. 10% new netsnets
Evaluation: Crash Test—routing as many nets as possible Evaluation: Crash Test—routing as many nets as possible under the constraint of only 2 metal layers & slack satisfactionunder the constraint of only 2 metal layers & slack satisfaction
((TD-S, TD-R, TIDETD-S, TD-R, TIDE)) TD-S TD-S ((TD-RTD-R) is SERT/SOAR overlaid on ) is SERT/SOAR overlaid on StdStd ( (R&RR&R))
ResultsResults
Slack viols
0
100
200
300
400
500
Ckt11.6k
Ckt22.3k
Ckt32.9k
Ckt43.6k
Ckt54.3k
Ckt64.9k
Ckt75.6k
Ckt86.3k
Ckt97.6k
Ckt1010.4k
Avg5.0k
Globnets
Ckts
Slac
k viol
s
TD-S
TD-R
TIDE
Sl ack vi ol s
0
20
40
60
80
100
Avg Gl ob nets
Slac
k vi
ols
TD- STD- RTI DE
5.6x
4.7x5.3x
4.2x
% Unrt.nets
0
20
40
60
80
Ckt11.6k
Ckt22.3k
Ckt32.9k
Ckt43.6k
Ckt54.3k
Ckt64.9k
Ckt75.6k
Ckt86.3k
Ckt97.6k
Ckt1010.4k
Avg5.0k
Globnets
Ckts
% Un
rt.nets
TD-S
TD-R
TIDE
% Unrt . net
05
1015202530354045
Avg Gl ob nets
% Un
rt.n
et TD- STD- RTI DE
9.8x 9.5x
7x6.7x
Times TIDE is better1) % Unrouted Nets
2) Slack Violations
Dutt & Arslan, UIC
Av rout net l ength
05
1015202530354045
Avg Gl ob nets
Av r
out
net
leng
th
TD- STD- RTI DE
ResultsResults
Vi as per new net
0
20
40
60
80
Ckt11. 6k
Ckt22. 3k
Ckt32. 9k
Ckt43. 6k
Ckt54. 3k
Ckt64. 9k
Ckt75. 6k
Ckt86. 3k
Ckt97. 6k
Ckt1010. 4k
Avg5. 0k
Gl obnet s
Ckt s
Vias
per
new
net TD- S
TD- RTI DE
Vias per new net
01020304050607080
Avg Glob netsVi
as p
er n
ew n
et TD-S
TD-R
TIDE
3x
6.7x
Times TIDE is better
2.6x
4.4x
3) Average Routed Net Length
4) Vias per New Net
Av rout net l ength
05
1015202530354045
Ckt11. 6k
Ckt22. 3k
Ckt32. 9k
Ckt43. 6k
Ckt54. 3k
Ckt64. 9k
Ckt75. 6k
Ckt86. 3k
Ckt97. 6k
Ckt1010. 4k
Avg5. 0k
Gl obnets
Av r
out
net
leng
th
TD-STD-RTI DE
Dutt & Arslan, UIC
Modi f nets per new net
05
101520253035
Ckt11. 6k
Ckt22. 3k
Ckt32. 9k
Ckt43. 6k
Ckt54. 3k
Ckt64. 9k
Ckt75. 6k
Ckt86. 3k
Ckt97. 6k
Ckt1010. 4k
Avg5. 0k
Gl obnets
Ckts
Modi
f ne
ts p
er n
ew n
et
TD-STD-RTI DE
Runti me
0
500
1000
1500
2000
Ckt11. 6k
Ckt22. 3k
Ckt32. 9k
Ckt43. 6k
Ckt54. 3k
Ckt64. 9k
Ckt75. 6k
Ckt86. 3k
Ckt97. 6k
Ckt1010. 4k
Avg5. 0k
Ckts
Runt
ime
(sec
s)
TD-STD-RTI DE
ResultsResults
modi f nets per new net
0
5
10
15
20
25
30
35
Avg Gl ob nets
modi
f ne
ts p
er n
ew n
et
TD- STD- RTI DE2x
9.5x
Runt i me
0
200
400
600
800
1000
AvgRu
ntim
e (s
ecs) TD- S
TD- RTI DE0.5x
2.4x
5) Modified Nets per New Net
6) Runtime
Times TIDE is better
Dutt & Arslan, UIC
ConclusionsConclusions New TD Incremental Routing Algorithm New TD Incremental Routing Algorithm TIDETIDE
Uses new concepts of Uses new concepts of derived tolerancesderived tolerances @ Steiner nodes @ Steiner nodes to:to:
a) In global routing—quickly determine slack-satisfying near-a) In global routing—quickly determine slack-satisfying near-min-WL connection of the next pin for a new net routingmin-WL connection of the next pin for a new net routing
b) In detailed routing—quickly determine slack satisfaction of b) In detailed routing—quickly determine slack satisfaction of B&R’ed netsB&R’ed nets
In global routing, the In global routing, the IntAlIntAl algorithm is the first in algorithm is the first in pruning pruning treestrees (proven correct) for determining the next nearest (proven correct) for determining the next nearest connection point after the recent attempt failed.connection point after the recent attempt failed.
In detailed routing, high-level DFS control In detailed routing, high-level DFS control good routing good routing soln. for new nets with min. impact on existing nets soln. for new nets with min. impact on existing nets
Produces significant improvement over TD-Std and Produces significant improvement over TD-Std and TD-R&R in all important metrics of interest and is TD-R&R in all important metrics of interest and is reasonably fastreasonably fast
Future WorkFuture Work TD incremental placement and integration with TIDETD incremental placement and integration with TIDE
Dutt & Arslan, UIC
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