Harmonic Load Pull of High-Power Microwave Devices using
Transcript of Harmonic Load Pull of High-Power Microwave Devices using
Harmonic Load Pull of High-Power Microwave
Devices using Fundamental-Only Load Pull Tuners John Hoversten, Student Member, IEEE, Michael Roberg, Student Member, IEEE, Zoya Popovic, Fellow, IEEE
Ahstract-This paper presents a high-power high-efficiency PA design method using traditional fundamental-frequency load pull tuners. Harmonic impedance control at the virtual drain is accomplished through the use of tunable pre-matching circuits and full-wave FEM modeling of package parasitics. A 10-mm gate periphery GaN transistor from TriQuint is characterized using the method, and load-pull contours are presented illustrating the dramatic impact of varying 2nd harmonic termination. A 3rd harmonic termination is added to satisfy conditions for classF-1 load pull, resulting in an 8 % efficiency improvement over the best-case 2nd harmonic termination. The method is verified by design and measurement of a 36-W class-F-1 PA prototype at 2.14 GHz with 81 % drain efficiency and 14.5 dB gain (78 % PAE) in pulsed operation.
Index Terms-harmonic load pull, class-F-inverse
I. INTRODUCTION
High-efficiency microwave power amplification is achieved
by shaping transistor voltage and current waveforms across the
active device [1]. For example, odd-harmonic open circuit and
even-harmonic short circuit terminations result in squaring of
the drain voltage waveform and peaking of the drain current
waveform [2]. Class-F (voltage squaring) operation has been
used to achieve more than 80 % PAE at 2 GHz with 16.5 W
output power [3] by controlling impedance at the 2nd, 3rd, and
4th harmonic. [4] suggests that Class-F-1 (current squaring)
operation provides benefits including higher fundamental load
impedance and reduced sensitivity to transistor on-resistance.
Class-F-1 also benefits from strong 3rd harmonic drain current
components generated when the drain voltage descends below
the knee voltage [5].
Most non-linear transistor models fail to accurately repro
duce transistor behavior at harmonic frequencies and under
heavy gain compression. In other cases nonlinear models are
not available. Therefore, load pull [6] is commonly used in
conjunction with analytical methods in the design of high
power PAs. Traditional load pull makes use of mechanical
tuners to vary drain and gate impedance. Transistor per
formance is measured over a constellation of fundamental
frequency impedances while harmonic impedances are allowed
to vary arbitrarily. Elaborate active and passive harmonic load
pull techniques [7] are available but are less common and
significantly more expensive.
In this paper we describe a simple, low cost method for con
trol and systematic variation of harmonic impedances based
on the block diagram of Fig. I. By convention, fundamental
frequency output impedance is referenced to plane P3 and
harmonic frequency impedances are referenced to plane PI.
This reference plane is intrinsic to the device at the output of
978-1-4244-6366-4/10/$26.00 ©201 0 IEEE
Drain Transition Analysis
Harmonic Prematch
Circuit
Fundamental Power LoadPull Meas.
Tuner
Fig. I. Block diagram of the output side of a load-pull system. Transistor virtual drain (PI) is a critical reference plane for high-efficiency operation. The package reference plane (P3) is most frequently used for load pull and PA design. Finite element method (FEM) transition analysis is used to model only the output half of the transistor.
the transconductance, and is referred to as the virtual drain.
Harmonic terminations must be referenced to this plane to
achieve the high-efficiency modes described in the literature.
Fig. 2 shows the position of reference planes P2 and P3 from
Fig. I for two packaging configurations. Full-wave electro
magnetic analysis of these configurations, presented in Section
2, is used to calculate the impedance at the unmeasurable plane
PI based on the measured impedance at P3.
The harmonic load pull method and accuracy verification is
described in Section 3. Results from load pull under varying
harmonic conditions, presented in Section 4, are used to design
a prototype PA which validates the method.
(a)
(b)
Fig. 2. Photograph and FEM model for the transformation incurred for a (a) microwave power transistor package (Zentrix RF70 I) and (b) chip/wire construction for a typical 50 W GaN transistor. Both models include eight bond wires of 1.25-mil diameter.
• Plane P3 • Plane P I. No Package • Plane P I. Package • Plane PI. Chip and Wire
(a)
(c)
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Reflection Coefficient Phase at P3
(b)
al -180 • Plane PI, No Package Solid: 2f =4 28GHz Dashed: �fo=6 42GHz � • Plane PI, Chip and Wire
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Reflection Coefficient Phase at P3
(d)
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Fig. 3. Impedance transformation from P3 to PI for DUTI (a, b) and DUT2 (c, d) for different package configurations represented by different colors. Rectangular plots are a clear indicator of phase sensitivity at PI relative to phase at P3. Sensitivity increases with Cout and package parasitics making harmonic termination at PI difficult. Red and green arcs (a,c) and bands (b,d) indicate regions of approximately short and open harmonic termination. Plots are normalized to the load line impedance of each device.
II. HIGH-POWER TRANSISTORS AND PACKAGING
The abiLity to terminate harmonics at the virtuaL drain is
determined by device and package characteristics. In this sec
tion two transistors are compared. The TGF-2023-1O (DUTl)
is a SO-W I O-mm-gate-periphery GaN HEMT from TriQuint
with up to 8 dB gain at 18 GHz [8]. DUTl has Gout = 2.7pF
output capacitance [9], and a theoreticaL Load Line impedance
of 6.6 n [S]. A non-Linear modeL is not currentLy avaiLabLe
for this device. DUT2 is a simiLar device intended for use at
S-band with Gout = 7.4 pF and a S.I n Load Line impedance.
DUTI and DUT2 are characterized in the two package
configurations shown in Fig. 2. The first is a standard pack
age used for medium-power (SO W) S-band appLications [10]
(shown in Fig. 2(a)). The second is a chip/wire construction in
which the die is eutectic-attached to a IS-miL-thick goLd-pLated
copper-moLybdenum pedestaL, and the pedestaL soLdered to an
underlying copper block. The die pads are connected to the
input and output matching circuits (built with 30-miL Rogers
43S0B) by eight I.2S-miL-diameter wire bonds.
Both configurations are simulated using Ansoft's HFSS
FEM software. Ports are de-embedded to pLanes PI and P3
of Fig. 1. The goal of the analysis is to determine what
impedance must be presented by the prematch circuit at P3 to
achieve a harmonic short or open (reactive boundaries defined
by X < 0.3RL and X > 3RL [2]) at the virtuaL drain
(PI). A meaningfuL comparison between two devices in both
packaged and chip/wire configurations is shown by Fig. 3 with
the following conclusions:
• It is important to normalize these harmonic impedances to
the load line impedance. When presenting an approximate
open termination, a reactance of jSn is unimportant
compared to a son Load line, but unacceptably large
compared to a sn Load line. Plots of Fig. 3 are therefore
normalized to the load line impedance.
• Considering only the transformation of Gout (magenta),
both devices have a reasonable range of phase angle at
P3 which resuLt in an approximate short or open at PI
(indicated by red and green bands of Fig. 3(b,d).
• Addition of the chip/wire transformation to Gout (blue)
has a large impact for DUT2 angle sensitivity at the 3rd
harmonic. This corresponds to the significantly smaller
and more irregularLy spaced constellation of Fig. 3(c).
Also, the slope of the dashed blue line in Fig. 3(d) is
quite steep, indicating a narrower range of angles at P3
which result in an approximate short or open at Pl.
• The standard package with Gout (black) makes an ap
proximate short or open termination impossible at the
3rd, and difficuLt at the 2nd harmonic for DUT2.
Fig. 4. (top) Photograph of the load pull equipment: A-Agilent ESG4438C Synthesizer, B-Agilent PSA4440A VSA, C-Agilent 4419B Power Meter, DTektronix DS02023 Oscilloscope, E- Focus CCMT-1816 Mechanical Tuners, F-Custom MatIab instrument and tuner control software. (bottom) Photograph of the load pull fixture and detail of the harmonic tuning stub: G-Input prematch transformer to 5 n and bias network, H-Output prematch transformer to 5 n with bias network, I-Detail of 2nd harmonic tuning stub.
Conclusions of the analysis have clear implications for load
pull methodology. Package parasitics and Cout can clearly
restrict the ability to enforce harmonic terminations at the
virtual drain. The harmonic terminations of DUT2 in the
standard package are nearly fixed under traditional load pull
(fundamental frequency only) due to large parasitic reactances
at harmonic frequencies. In chip/wire configuration harmonic
impedance of DUn can be easily controlled at a 2.14 GHz
fundamental frequency.
III. HARMONIC LOAD PULL MEASUREMENTS
High-power fundamental-frequency load pull [6] is carried
out with the addition of pulsed power measurement and
harmonic impedance tuning using the measurement setup
shown in Fig. 4. CW input and output power is measured
using an average power sensor and an offset is calculated to
calibrate a spectrum analyzer in zero-span mode. The zero
span measurement requires no offset when transitioning to
pulsed measurements. The RF power measurement is calcu
lated as the average power over the pulse duration. RMS drain
voltage and current are measured over the whole pulse using
an oscilloscope. The pulse duty cycle is S % and the period is
I msec.
In the block diagram of Fig. I the harmonic prematch circuit
[II] performs the following functions:
• Transforms the son fundamental constellation to a lower
impedance (in this case Sn),
Fig. 5. Small-signal gain contours for six prematch harmonic terminations are used for validating load pull calibration. Disagreement of dashed red contour indicates a calibration error.
• Supplies DC bias near the device drain to avoid large
signal oscillation,
• Constrains 2nd harmonic impedance to a single high re
flection coefficient for the whole fundamental impedance
constellation, and
• Increases the angle of the 2nd harmonic termination by
decreasing length of a tuning stub, labeled "I" in Fig. 4,
with only a small impact on the fundamental frequency
impedance transformation.
Two-port S-parameters of the output prematch, mechanical
tuner, and output attenuators are separately measured to allow
de-embedding of resistive and reflection loss at each funda
mental impedance in the load pull constellation. The input
and output prematch blocks are built as break-apart fixtures
[II], allowing S-parameter measurement using a microstrip
TRL calibration kit.
Two identical prematch circuits are constructed, one for S
parameter measurement (CKTA) and one to remain perma
nently wire bonded to the device (CKTB) thus eliminating
parasitic variations and limiting potential for damage to the
device. Both circuits' 2nd harmonic stubs are tuned identically
so that S-parameters from CKTA can be de-embedded from
the load pull measurements using CKTB. The accuracy of this
method is verified after tuning the 2nd harmonic termination
by measuring small-signal gain contours as shown in Fig. S. Varying harmonic termination should change large-signal
transistor performance, but small-signal gain should remain
constant. Five of the contours are tightly grouped, indicat
ing that the measured S-parameters of CKTA match the S
parameters of CKTB, and power measurement error is accept
ably small. The dashed-red curve shows an instance where the
calibration check failed, indicating that CKTA measurements
did not match that of CKTB and must be repeated.
IV. LOAD PULL AND PA P ROTOTY PE RESULTS
DUn was biased at 28 V drain supply with a class-AB bias
of 300 rnA. Source pull was first performed to optimize small
signal gain, followed by large-signal load pull measurements at
the six 2nd harmonic termination angles shown by colored dots
in Fig. 6, referenced to the virtual drain. At each impedance
point input power was increased until gate current measured
20 rnA, corresponding to an approximately consistent level of
gain compression. Fig. 6 shows power and drain efficiency
achieved at each harmonic termination. The figure also il
lustrates the required modification to the prematch circuit
Fig. 6. Fundamental frequency constant drain efficiency contours (referenced to P3) shown in colors that correspond to six 2nd harmonic terminations (dots, referenced to PI). Efficiency and maximum power of each contour is indicated next the corresponding harmonic termination dot.
Fig. 7. Power (dashed) and drain efficiency (solid) load pull contours with two different harmonic environments (red and blue, referenced to P3). Both sets of 2nd (0) and 3rd (x) harmonic terminations are shown referenced to plane PI.
to achieve each harmonic termination. The highest efficiency
region (77 %) is achieved with 2nd harmonic nearest an open
circuit (blue). In this case the 3rd harmonic was not explicitly
controlled, but was fixed at a capacitive impedance.
Next we investigate the impact of 3rd harmonic control.
Another output prematch circuit was designed to terminate 2nd
and 3rd harmonics in an open and short at PI, respectively
(the class-F-1 condition). Fig.7 compares results from this
measurement to the 2nd-harmonic-only measurement of Fig. 6.
Intentional termination of the 3rd harmonic increases transistor
drain efficiency by 8 % without reducing output power.
A prototype PA was designed using results of the measure
ments in Fig. 7, shown in shown in Fig. 8. A fundamental
load impedance of 10.2 + j6.20 was presented at plane P3
Fig. 8. Photograph of the fabricated 36-W class-F-l PA prototype with 81 % drain efficiency at 2.14GHz.
with 0.27 dB insertion loss in the output matching circuit.
2nd and 3rd harmonic impedances approximate an open and
short at plane PI similar to those shown Fig. 7. Output power
of 36 W was measured with 14.5 dB gain and 81 % drain
efficiency, or 78 % PAE at 2.14 GHz, consistent with load pull
characterization results.
V. CONCLUSION
The analysis in Section 2 shows that harmonic termina
tions of high-performance devices can be impacted by output
matching. In such cases the results of Section 4 indicate
that transistor performance will change significantly based on
the harmonic environment. A method has been presented to
systematically sweep harmonic termination, resulting in a very
high-efficiency class-F-1 PA prototype.
VI. ACKNOWLEDGEMENTS
The authors are grateful for collaboration with Bill McCalpin and Bob Crispell of TriQuint Semiconductor.
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