Hardware-Software Co-Design and Prototyping on SoC FPGAs · Design Challenges for Soc FPGA’s FPGA...

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1 © 2015 The MathWorks, Inc. Hardware-Software Co-Design and Prototyping on SoC FPGAs Puneet Kumar Prateek Sikka Application Engineering Team

Transcript of Hardware-Software Co-Design and Prototyping on SoC FPGAs · Design Challenges for Soc FPGA’s FPGA...

Page 1: Hardware-Software Co-Design and Prototyping on SoC FPGAs · Design Challenges for Soc FPGA’s FPGA Designers not familiar with programming processors DSP/Processor programmers not

1© 2015 The MathWorks, Inc.

Hardware-Software Co-Design and Prototyping on SoC

FPGAs

Puneet Kumar

Prateek Sikka

Application Engineering Team

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Agenda

Integrated Hardware / Software Top down Workflow for SoC

FPGA’s, highlighting:

– Model Based Design Workflow for SoC FPGA’s

– Automatic Code Generation: HDL code generation for the FPGA fabric and C-Code generation for the ARM MCU

– Automatic Interface Logic Generation: Generation of the interface logic and software between the FPGA and ARM.

– Integrated Verification: Integrated HDL Verification using HDL Co-simulation and FPGA-in-Loop

Next Steps, Q&A

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Agenda

Integrated Hardware / Software Top down Workflow for SoC

FPGA’s, highlighting:

– Model Based Design Workflow for SoC FPGA’s

– Automatic Code Generation: HDL code generation for the FPGA fabric and C-Code generation for the ARM MCU

– Automatic Interface Logic Generation: Generation of the interface logic and software between the FPGA and ARM.

– Integrated Verification: Integrated HDL Verification using HDL Co-simulation and FPGA-in-Loop

Next Steps, Q&A

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Edge Detection Demo – Behavioral Model

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Edge Detection Demo – Implementation

Model

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You May Have Some Questions?

How can we:

– Implement designs on SoC FPGA’s?

– Partition the HW and SW?

– Generate the Interface Logic?

MATLAB/Simulink

Algorithm Design

FPGA ASICFPGA ASICFPGA ASICMCU DSPSoC FPGA’s

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Design Challenges for Soc FPGA’s

FPGA Designers not familiar with programming processors

DSP/Processor programmers not familiar with FPGAs

What should run on the FPGA vs. what should run on the ARM?

No established rules for hooking up the interface between FPGA

and ARM processor

ARM

ProcessorC-Code

Software

InterfaceFPGAHDL Code

Hardware

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8© 2015 The MathWorks, Inc.

Model-Based Design

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Why Model-Based Design?

Requirements Development

Simulation

Code Generation

Continuous Verification

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Model-Based Design:

From Concept to Production

• Automate regression testing

• Detect design errors

• Support certification and standards

• Generate efficient code

• Explore and optimize implementation tradeoffs

• Model multi-domain systems

• Explore and optimize system behavior in floating

point and fixed point

• Collaborate across teams and continents

INTEGRATION

IMPLEMENTATION

DESIGN

TE

ST

& V

ER

IFIC

AT

ION

RESEARCH REQUIREMENTS

ARM FPGA

VHDL, VerilogC, C++

Environment Models

Physical Components

Algorithms

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IMPLEMENTATION

SoC FPGA Design Flow

SoC FPGA Template

Xilinx/Altera Embedded System Integration

DESIGN

Rea

l-Tim

e P

ara

me

ter T

un

ing

an

d V

erific

atio

n

RESEARCH REQUIREMENTS

ARM FPGA

HDL Coder™Embedded

Coder®

Top-Level System Model

Software Model Hardware Model

User defines partitioning

MathWorks automates code and

interface-model generation

MathWorks automates the build

and download through the FPGA

tools

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Model-Based Design for SoC FPGA

VHDL, Verilog

ASICFPGA

Boards

HDL

CoderEmbedded

Coder

C, C++

INTEGRATION

IMPLEMENTATION

DESIGN

TE

ST

& V

ER

IFIC

AT

ION

RESEARCH REQUIREMENTS

ARM DSP FPGA ASIC

Structured TextVHDL, VerilogC, C++

Environment Models

Physical Components

Algorithms

PLC

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Solution: C and HDL Code Generation

Design, execute, and verify algorithms in MATLAB

Automatically generate C or HDL code

Deploy generated code on hardware

MATLAB

Algorithm Design

FPGA ASIC

HDL Coder

FPGA ASIC

VHDL/Verilog

Gen

era

te

FPGA ASIC

MATLAB Coder

MCU DSP

C

Gen

era

te

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Code Generation Products for VHDL/Verilog

MATLAB® Coder™

Automatically generate C and C++ from

MATLAB codeMATLAB Coder

HDL CoderHDL Coder™

Automatically generate VHDL or Verilog

from MATLAB code and Simulink Model

Fixed-Point DesignerFixed-Point Designer™

provides fixed-point data types and

arithmetic

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Code Generation Products for C/C++

MATLAB® Coder™

Automatically generate C and C++ from

MATLAB code

Simulink® Coder™

Automatically generate C and C++ from

Simulink models and Stateflow charts

Embedded Coder™

Automatically generate C and C++

optimized for embedded systems

Simulink

Coder

Embedded Coder

MATLAB Coder

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Edge Detection Demo – Behavioral Model

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Workflow for Video Image Processing

Concept Development

Algorithm Development

PrototypingArchitecture

designPrototyping

Chip design

Frame based

Image/Video Engineer

Pixel based

HW Engineer

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Vision HDL ToolboxDesign and prototype video image processing systems

Modeling hardware behavior of

the algorithms

– Pixel-based functions and blocks

– Conversion between frames and

pixels

– Standard and custom frame sizes

Prototyping algorithms on

hardware

– Efficient and readable HDL code

– FPGA-in-the-loop testing and

acceleration

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Agenda

Integrated Hardware / Software Top down Workflow for SoC

FPGA’s, highlighting:

– Model Based Design Workflow for SoC FPGA’s

– Automatic Code Generation: HDL code generation for the FPGA fabric and C-Code generation for the ARM MCU

– Automatic Interface Logic Generation: Generation of the interface logic and software between the FPGA and ARM.

– Integrated Verification: Integrated HDL Verification using HDL Co-simulation and FPGA-in-Loop

Next Steps, Q&A

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HW-SW Co-Design: It’s all about the Workflow

VHDL or Verilog

HW-SW Co-design

HW-SW

Co-Design

Workflow

Prepare model for IP core

generation

Configure Interface Logic

RTL Code Generation for IP Core

Generate Software/Hardware Model

Deployment

Synthesis/ Bit File GenerationC/C++

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Model-Based Design flow using MATLAB/Simulink from Algorithm to FPGA Implementation

HDL Verifier

FPGA in the Loop

MATLAB® and Simulink®

Algorithm and System Design

Implement Design

Map

Place & Route

Synthesis

Back Annotation

Verification

Static Timing Analysis

Timing Simulation

Functional Simulation

HDL Verifier

HDL Co-Simulation

HDL Coder

RTL Creation

RTL

DESIGN

Algorithm

Development

MATLAB

Simulink

Stateflow

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SoC FPGA Model-Based Design Workflow

MATLAB® and Simulink®

Algorithm and System Design

ARM

FPGAAXI AXI

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SoC FPGA Model-Based Design Workflow

MATLAB® and Simulink®

Algorithm and System Design

Simulink Model

SW

HW

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Configure Interface Logic

Prepare model for IP core

generation

Configure Interface Logic

RTL Code Generation for IP Core

Generate Software/Hardware Model

Deployment

Synthesis/ Bit File Generation

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RTL Code Generation for IP Core

Prepare model for IP core

generation

Configure Interface Logic

RTL Code Generation for IP Core

Generate Software/Hardware Model

Deployment

Synthesis/ Bit File Generation

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Full Bidirectional traceability

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SoC FPGA Model-Based Design Workflow

HDL IP Core

Generation

MATLAB® and Simulink®

Algorithm and System Design

Simulink Model

SW

HW

Programmable Logic IP Core

Algorithm

from

MATLAB/

Simulink

AXI Lite

Accessible

Registers

AXI4-Stream Video In

AXI4-Stream Video Out

External

Ports

HDL IP Core

Generation

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SoC FPGA Model-Based Design Workflow

HDL IP Core

Generation

MATLAB® and Simulink®

Algorithm and System Design

EDK Integration

Zynq Platform

FPGA Bitstream

Programmable Logic IP Core

Algorithm

from

MATLAB/

Simulink

AXI Lite

Accessible

Registers

AXI4-Stream Video In

AXI4-Stream Video Out

External

Ports

EDK Project

AX

I4-L

ite

Processing

System

Programmable Logic IP Core

Algorithm

from

MATLAB/

Simulink

AXI Lite

Accessible

Registers

AXI

Video

DMA

AXI4-Stream Video In

AXI4-Stream Video Out

External

Ports

EDK Integration

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Generate Software/Hardware model

Prepare model for IP core

generation

Configure Interface Logic

RTL Code Generation for IP Core

Generate Software/Hardware Model

Deployment

Synthesis/ Bit File Generation

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SoC FPGA Model-Based Design Workflow

HDL IP Core

Generation

MATLAB® and Simulink®

Algorithm and System Design

EDK Integration

Zynq Platform

FPGA Bitstream

SW Interface

Model Generation

SW Build

Simulink Model

SW

HW

SW Interface Model

SW

SW I/O

Driver

Blocks

SW Interface

Model Generation

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SoC FPGA Model-Based Design Workflow

HDL IP Core

Generation

MATLAB® and Simulink®

Algorithm and System Design

EDK IntegrationSW Interface

Model Generation

Zynq Platform

SW BuildFPGA Bitstream

External Mode

PIL

Real-time Parameter

Tuning and Verification

– External Mode

– Processor-in-the-loop

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Fast Prototyping and Iteration

TCP/IP

Fast prototyping,

iteration, and live

probing/tuning directly

on SoC FPGA

hardware

IP Core

Registers

FPGA

IPCoreARM Cortex-A9 MP

(Running Linux)

AX

I4-L

ite

AXI4-Lite

Blocks

C Algorithm

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Zynq HW/SW Co-design Workflow Summary

Embedded System Project

Simulink Model

SW

HWDesign IP Core

Generation

FPGA IP Core

Algorithm

from

MATLAB and

Simulink

AXI Lite

Accessible

registers

External

Ports

AX

I4-L

ite

Bu

s

Processor

Em

be

dd

ed

Sys

tem

Inte

gra

tio

n

External

Ports

Generate SW

Interface Model

SW Interface Model

SW

SW I/ODriverBlocks

FPGA

BitstreamSW

Build

FPGA IP Core

Algorithm from

MATLAB and

Simulink

AXI Lite

Accessible

registers

Page 34: Hardware-Software Co-Design and Prototyping on SoC FPGAs · Design Challenges for Soc FPGA’s FPGA Designers not familiar with programming processors DSP/Processor programmers not

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Agenda

Integrated Hardware / Software Top down Workflow for SoC

FPGA’s, highlighting:

– Model Based Design Workflow for SoC FPGA’s

– Automatic Code Generation: HDL code generation for the FPGA fabric and C-Code generation for the ARM MCU

– Automatic Interface Logic Generation: Generation of the interface logic and software between the FPGA and ARM.

– Integrated Verification: Integrated HDL Verification using HDL Co-simulation and FPGA-in-Loop

Next Steps, Q&A

Page 35: Hardware-Software Co-Design and Prototyping on SoC FPGAs · Design Challenges for Soc FPGA’s FPGA Designers not familiar with programming processors DSP/Processor programmers not

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Enroll in Upcoming Training Courses

NoStart Date Course Name City

01 02nd-03rd May Signal Processing with MATLAB Bangalore

02 04th -05th May Image Processing with MATLAB Bangalore

03 06th May Computer Vision with MATLAB Bangalore

04 16th -17th June Machine Learning with MATLAB Bangalore

05 11th -12th July Generating HDL Code from Simulink Bangalore

06 13th -14th July Programming Xilinx Zynq SoCs with MATLAB and Simulink Bangalore

www.mathworks.in/training

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MathWorks India – Services and Offerings

Technical Evangelist

Product Training:

www.mathworks.in/training

Application Engineering

Technical Support local for India: www.mathworks.in/myservicerequests

Customer Service for non-technical questions: [email protected]

Knowledge and marketing resources: www.mathworks.in, webinars, seminars, conferences

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Contact MathWorks India

URL: http://www.mathworks.in

E-mail: [email protected]

Technical Support: www.mathworks.in/myservicerequests

Tel: +91-80-6632 6000

Fax: +91-80-6632 6010

• MathWorks India Private Limited9th Floor, ‘B’ Wing, Etamin BlockPrestige Technology Park IIMarathahalli – Sarjapur Ring RoadBangalore – 560103, KarnatakaIndia

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