HARDWARE DESCRIPTION LANGUAGE (HDL) - …portal.unimap.edu.my/portal/page/portal30/Lecturer...
Transcript of HARDWARE DESCRIPTION LANGUAGE (HDL) - …portal.unimap.edu.my/portal/page/portal30/Lecturer...
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HARDWARE DESCRIPTION
LANGUAGE (HDL)
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Introduction of development of digital IC technology
The following slides are adapted from “Digital
Integrated Circuits - A Design Perspective,”
2003.
J. M. Rabaey, A. Chandrakasan, B. Nikolic
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ENIAC - The first electronic computer (1946)
10 feet tall;
1,000 square feet of floor- space;
30 tons;
More than 70,000 resistors;
10,000 capacitors;
6,000 switches;
18,000 vacuum tubes;
Requires 150 kilowatts of power;
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Transistor Age
1951: Shockley develops junction transistor which can be manufactured in quantity.
1947: Bardeen and Brattain create point-contact transistor
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Early Integration
Jack Kilby, working at Texas Instruments, invented a monolithic
“integrated circuit” in July 1959.
He had constructed the flip-flop shown in the patent drawing above.
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Planar transistors
In mid 1959, Noyce develops the first
true IC using planar transistors,
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Practice Makes Perfect
1961: TI and Fairchild introduced first logic IC’s
1963: Densities and yields improve. This circuit has four flip-flops.
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Continues development
1967: Fairchild markets the first semi-custom chip.
Transistors (organized in columns) can be easily rewired
to create different circuits. Circuit has ~150 logic gates.
1968: Noyce and Moore leave Fairchild to form Intel. By 1971 Intel had
500 employees;
By 2004, 80,000 employees in 55 countries and $34.2B in sales.
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Continues development
1970: Intel starts selling a 1k bit RAM.
1971: Ted Hoff at Intel designed the first microprocessor. The
4004 had 4-bit busses and a clock rate of 108 KHz. It had
2300 transistors and was built in a 10 um process.
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Exponential Growth
1972: 8088 introduced.
Had 3,500 transistors supporting a byte-wide data path.
1974: Introduction of the 8080.
Had 6,000 transistors in a 6 um process.
The clock rate was 2 MHz.
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Today
Many disciplines have contributed to the current state-of-the-art in VLSI Design:
•Solid State Physics
•Materials Science
•Lithography and fab
•Device modeling
•Circuit design and
layout
•Architecture design
•Algorithms
•CAD tools
To come up with chips like:
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Pentium 4 – 0.18 um t
0.18-micron process technology
– Introduction date: November 20, 2000 (1.5, 1.4 GHz)
– Level Two cache: 256 KB Advanced Transfer Cache
– System Bus Speed: 400 MHz
– SSE2 SIMD Extensions
– Transistors: 42 Million
– Typical Use: Desktops and entry-level workstations
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0.13-micron process technology (2.53, 2.2, 2 GHz)
»Introduction date:
January 7, 2002
»Level Two cache:
512 KB Advanced
»Transistors: 55 Million
Pentium 4
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Pentium Pro - multichip module (MCM)
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• IBM chip has nine processor cores
• 192 billion floating-point operations per second (192 G)
• Typical Use: multimedia
Supercomputer for Sony's PlayStation 3
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Moore’s Law
In 1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that semiconductor
technology will double its effectiveness every
18 months
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Moore’s Law
16
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2
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0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LO
G2 O
F T
HE
NU
MB
ER
OF
CO
MP
ON
EN
TS
PE
R IN
TE
GR
AT
ED
FU
NC
TIO
N
Source: Electronics, April 19, 1965.
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Technology Directions: SIA Roadmap
Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 70 50 35
Logic trans/cm 2 6.2M 18M 39M 84M 180M 390M
Cost/trans (mc) 1.735 .580 .255 .110 .049 .022
#pads/chip 1867 2553 3492 4776 6532 8935
Clock (MHz) 1250 2100 3500 6000 10000 16900
C hip size (mm 2 ) 340 430 520 620 750 900
Wiring levels 6 - 7 7 7 - 8 8 - 9 9 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5
High - perf pow (W) 90 130 160 170 175 183
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Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs (std cell)
User
Programmable
PLD FPGA
PAL PLA PML LUT (Look-Up Table)
MUX Gates
World of Integrated Circuits
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• designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
• bought off the shelf
and reconfigured by
designers themselves
ASIC
Application Specific
Integrated Circuit
FPGA
Field Programmable
Gate Array
• designed all the way
from behavioral description
to physical layout
• no physical layout design;
design ends with a bitstream
used to configure a device
ASIC versus FPGA
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Off-the-shelf
Low development cost
Short time to market
Reconfigurability
High performance
ASICs FPGAs
Low power
Low cost in
high volumes
Which Way to Go?
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What is an ASIC Chip ? • Application Specific
Integrated Circuit
• A chip that is produced to
perform a specific function
i.e. microcontroller
• Limited interconnect layers,
dedicated routing channels
• Intellectual Properties for
timing and performance.
DLLs, PLLs, DDRs, RAMs
• Fabricated System-On-Chip
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ASIC Design Flow (Overview)
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Source: [Brown99]
What is an FPGA Chip ? • Field Programmable Gate
Array
• A chip that can be configured
by user to implement
different digital hardware
• Configurable Logic Blocks
(CLB) and Programmable
Switch Matrices. Sea-of-
gates
• Bitstream to configure:
function of each block & the
interconnection between
logic blocks
I/O Block
I/O B
lock
I/O Block
I/O B
lock
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FPGA Design Flow (Overview)
HDL SOURCE
LOGIC SYNTHESIS
TO GATES
MAPPING
PLACEMENT
ROUTING
BITSTREAM
GENERATION
AND PROGRAMMING
(UNIQUE TO FPGAs)
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What is HDL?
• A type of programming language for sampling and modeling of electronic & logic circuit designs
• It can describe the circuit’s operation, design and organization
• By using CAD tools, it can be used for test and verify through simulations
• Also used to model the intended piece of device like ASICs, FPGAs CPLDs and others
• Various kinds : VHDL, Verilog HDL, AHDL etc
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Why HDL?
• Software solution due to : – Limits in hardware solutions
– Increasing design complexity – Increasing cost in time and investment – Increasing knowledge requirement – Inadequacy of other existing languages
• Text-based rather than schematic design
– Easier development – faster time-to-market – synthesis and analysis – Documentation
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• Programming languages such as C or Java cannot serve as HDLs (unless modified significantly).
• Programming languages are modeled after a sequential process, where operations are performed in a sequential order (order matters).
– This is amenable to the human thinking process, in which an algorithm is unfolded into a recipe or step-by-step process
– This process matches the basic operation of a hardware computing platform.
• HDLs such as VHDL (VHSIC (Very High Speed Integrated Circuit) HDL) and Verilog were developed to support the underlying characteristics of hardware
– Connections of parts
– Concurrent operations
– Concept of propagation delay and timing
These characteristics cannot be captured by traditional PLs
Programming Language (PL) vs Hardware Description Language (HDL)
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A Dataflow Language
DATAFLOW CONTROLFLOW EX: C language assignment EX: VHDL signal assignment
X = A & B; X <= A and B;
X is computed out of A and
B ONLY each time this
assignment is executed
A PERMANENT link is created
between A, B, and X
X is computed out of A and B
WHENEVER A or B changes
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A Dataflow Language (cont’d)
DATAFLOW CONTROLFLOW
EX: C language assignment EX: VHDL signal assignment
X = A & B;
------
X = C & D;
X <= A and B;
------
X <= C and D;
YES NO
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• VHSIC Hardware Description Language – VHSIC stands for Very High Speed Integrated
Circuit
• Jointly developed in 1983 by Intermetrics, IBM & Texas Instruments
• Initially used by the US Dept. of Defense
• IEEE Standard in 1987 then enhanced and restandardized in 1993
Intro to VHDL
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• Near-approach to industry
– High density electronic design
– Multidisciplinary – electronics, microelectronics, communications, instrumentations and control
• Technology related
– Reconfigurable
– Actual implementation
• System Design
– System throughput recognition
– problem solving ability
– debugging techniques
Using VHDL as UniMAP’s OBE and PBL
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VHDL CAD tool in this subject
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VHDL Main Features
Timing Dataflow
Structure
Behavior
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VHDL Main Features
• Supports the whole design process from high to low abstraction
levels :
• System and algorithmic level
• Register Transfer Level
• Logic level
• Circuit level (to some extent)
• Suitable for specifications either in behavioral or structural domain
• Precise simulation semantics is associated with the language
definition :
• Timing simulations specified
• Output simulation is uniquely identified and independent of the
VHDL implementation
VHDL specifications are accepted by hardware synthesis tools
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Case Sensitivity
• VHDL is not case sensitive
Example:
Names or labels
databus
Databus
DataBus
DATABUS
are all equivalent
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Free Format
• VHDL is a “free format” language
No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example:
if (a=b) then
or if (a=b) then
or if (a =
b) then
are all equivalent
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Comments
• Comments in VHDL are indicated with
a “double dash”, i.e., “--”
Comment indicator can be placed anywhere in the line
Any text that follows in the same line is treated as
a comment
Carriage return terminates a comment
No method for commenting a block extending over a couple of lines
Examples:
-- main subcircuit
Data_in <= Data_bus; -- reading data from the input FIFO
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VHDL Architectures
• Does not allow a layout description
Behavioral
Structural
Algorithmic
FSM
RTL
Gate
Layout
Abstraction Levels VHDL Architectures
How it works
How it is connected
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VHDL WRITTEN FORMAT
Library / Package Declaration
Entity Declaration
Architecture Flow
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Example VHDL Code • 3 sections to a piece of VHDL code
• File extension for a VHDL file is .vhd
• Name of the file is usually the entity name (nand_gate.vhd)
LIBRARY DECLARATION
ENTITY
ARCHITECTURE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
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LIBRARY / PACKAGE DECLARATION
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_signed.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Library work;
Use work.my_package.entity_name;
Use work.my_package.function_name;
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Library Declarations
Use all definitions from the package
std_logic_1164
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
Library declaration
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Library Declarations - Syntax
LIBRARY library_name;
USE library_name.package_name.package_parts;
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Commonly Used Libraries • ieee
– Specifies multi-level logic system including STD_LOGIC, and STD_LOGIC_VECTOR data types
• std
– Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.
• work
– User-created designs after compilation
Needs to be
explicitly declared
Visible by default
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Design Entity
Design Entity - most basic
building block of a design.
One entity can have many different architectures.
entity declaration
architecture 1
architecture 2
architecture 3
design entity
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ENTITY DECLARATION
• Specifies the input and output signals of the entity
• modes : in, out, inout, buffer
• Format :
Entity name is
port (port_name : mode data_type);
End name;
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Rules for Entity Name General rules of thumb (according to VHDL-87)
1. All names should start with an alphabet character (a-z or
A-Z) 2. Use only alphabet characters (a-z or A-Z) digits (0-9) and
underscore (_) 3. Do not use any punctuation or reserved characters within
a name (!, ?, ., &, +, -, etc.) 4. Do not use two or more consecutive underscore
characters (__) within a name (e.g., Sel__A is invalid) 5. All names and labels in a given entity and architecture
must be unique
6. Cannot end with an ‘_’ underscore
7. Cannot have a blank space to separate words
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Common Data Type
• Std_logic data
– bit logic
– std_logic
– std_logic_vector (b downto a) or std_logic_vector (a to b) : array of bit logic
• Signed, Unsigned
• Integer
• Boolean
• Legal values for std_logic : 0,1,Z,-,L,H,U,X,W
– Only the first 4 are used in synthesis
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Port Modes: Summary The Port Mode of the interface describes the direction in which data
travels with respect to the component
– In: Data comes in this port and can only be read within the entity. It can appear
only on the right side of a signal or variable assignment.
– Out: The value of an output port can only be updated within the entity. It
cannot be read. It can only appear on the left side of a signal assignment.
– Inout: The value of a bi-directional port can be read and updated within the
entity model. It can appear on both sides of a signal assignment.
– Buffer: Used for a signal that is an output from an entity. The value of the
signal can be used inside the entity, which means that in an assignment
statement the signal can appear on the left and right sides of the <= operator
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Example 1
Full Adder A
B
Cin
SUM
Cout
Entity Full_Adder is
Port ( A,B,Cin : in std_logic;
SUM, Cout : out std_logic
);
End Full_Adder;
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Example 2
4 bit Full Adder
A[3..0]
Cin
SUM[3..0]
Cout
B[3..0]
Entity Full_Adder is
Port ( A,B : in std_logic_vector(3 downto 0);
Cin : in std_logic;
SUM : out std_logic_vector(3 downto 0);
Cout : out std_logic );
End Full_Adder;
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ARCHITECTURE • The Internal Aspect of a Design Unit
• Can be behavioral (RTL) or structural
• Always associated with single entity
• Single entity can have multiple architectures
architecture architecture_name of entity_name is
{architecture_declarative_part}
begin
{architecture_descriptive_part}
end [architecture_name];
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Behavioral vs Structural Full Adder process (a,b,cin) behavioral
begin
s <= (a xor b) xor cin;
c <= ((a xor b) and cin) or (a and b);
end process;
-- component declaration structural
component FA
port ( inA, inB, inC : in std_logic;
Sum, Carry : out std_logic );
end component;
-- component instantiation
U1 : FA port map : (a=>inA, b=>inB, c=>inC, s=>Sum, c=>Carry);
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• Two architecture flavors: Behavioral & Structural
architecture TWO of MUX2 is
component MX2 -- a macro from a library
port (A, B, S:in std_logic;
Y :out std_logic);
end component;
begin
-- instantiate MX2
U1: MX2
port map(A=>AIN, B=>BIN, S=>SIN, Y=>YOUT);
end TWO;
architecture ONE of MUX2 is
begin
YOUT <= (AIN and not SIN) or (BIN and SIN);
end ONE;
Declarative part
Behavioral
Structural
Descriptive part
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ARCHITECTURE DATA OBJECTS
• 3 kinds of data object :
1. Signal
2. Constant
3. Variable
• Signal is the most common form of data object used in describing the logic signals (wires) in a circuit
• The value of an individual signal is described in apostrophes
• The value of multiple signal is described in double quotes
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Operators
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Single Wire Versus Bus
wire
a
bus
b
1
8
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 downto 0);
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Standard Logic Vectors SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….
a <= '1';
b <= "0000"; -- Binary base assumed by default
c <= B"0000"; -- Binary base explicitly specified
d <= "0110_0111"; -- You can use '_' to increase readability
e <= X"AF67"; -- Hexadecimal base
f <= O"723"; -- Octal base
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Single versus Double Quote
• Use single quote to hold a single bit signal
– a <= '0', a <='Z'
• Use double quote to hold a multi-bit signal – b <= "00", b <= "11"
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Priority Dataflow
position of parenthesis
RTL netlist layout
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Vectors and Concatenation
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= "0000";
b <= "1111";
c <= a & b; -- c = "00001111"
d <= '0' & "0001111"; -- d <= "00001111"
e <= '0' & '0' & '0' & '0' & '1' & '1' &
'1' & '1'; -- e <= "00001111"
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Exercise
1. Generate the VHDL code for a logic circuit of a Half Adder and simulate in Quartus II
2. Using the Half Adder in Question 1, generate and simulate the VHDL code for a logic circuit of a Full Adder.
3. What do you think a VHDL code representation for a 4-bit logic circuit of a 2-to-1 Multiplexer looks like? Simulate your VHDL code in Quartus II to show the dataflow operation.
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Next Chapter
• VHDL Architecture writing design styles
– Concurrent Statements
– Sequential Statements
– Behavioral vs Structural