Hall D Online Meeting27 June 2008

Fast Electronics R. Chris Cuevas

Jefferson LabExperimental Nuclear Physics Division

12 GeV Trigger System Status Update

-- New module design progress-- Updates to System drawings-- Testing activities

Project Status

• 15 weeks until the end of FY08• Identified FY09 PED activities are defined for the ‘Test Stand’:

• FADC250 –

-- Nine modules fully assembled and all required modifications have been added

-- 8 channel 12 bit version delivered to IU.

-- Test crate and CPU that is on loan to G. Vissar at IUCF has been moved to IU

-- LabView test routines have been completed to fully test each FADC250

-- The LabView test programs will provide a nice platform for troubleshooting and repair

-- CODA driver has been completed and is in use for testing with the Trigger Interface

-- Development to download firmware through VME has started (Hai)• Trigger Interface –

-- 4 modules fully assembled and functional

-- Successful synchronization of trigger and latency adjustment for 150m and 50m fiber

-- Plans underway to test multiple FADC250 modules in two VXS crates

- Trigger rate performance testing for FADC250

- Does FADC250 pipeline trigger readout meet specifications?

- Data throughput testing

-- Test stand software – Ben has created very useful routines to configure and display

readout data.

Signal Distribution module – -- Functional specifications completed for May Review-- Schematics are behind ‘schedule’ - New circuits to regulate power to the module - FPGA has been selected-- Must begin component placement and routing by July

Crate Trigger Processor – -- Functional specification has been completed for May Review-- Schematics are complete-- Significant progress with placement of components and routing of circuit

board-- CNU Student working with Hai on interface firmware for CTP to TI

communication

SubSystem Processor – Global Trigger Processor – Trigger Supervisor –

-- Functional specification document completed for May Review-- Design activities scheduled for FY09

Project Status

CTP Circuit Board Place & Route

2 Gigabit ‘Lanes’ from each FADC250

More updates,,

• Detailed System Drawings – -- Started converting the logical drawings to detailed rack drawings

- Include ALL equipment ‘chassis’- Drawings for each platform have been started

-- Work closely with Mechanical Engineering to identify best cable routing method for each sub-system (platform)

Tagger Area: Instrumentation Racks

Crates and other equipmentchassis shown. Need to add details to show AC mains panel assignments& Network hardware.

Testing updates,,

• Many tests are planned for multiple FADC250 boards in a crate• Must test token passing scheme, and measure any noise and jitter effects with up to 8 FADC in a crate.

• Two crate trigger latency tests have been performed, and we have the fiber optic patch panels that will be used in the final installation. The test stand is a very good platform to simulate the final configuration in the Hall and to measure total system effects on clock jitter and other critical timing parameters

• Data display and GUIs to configure the test station have been developed by Ben.