GSA 3D Working Group eSilicon MoZAIC 2.5D Activities...eSilicon • Ideas to ICs CONFIDENTIAL 3 What...

CONFIDENTIAL

GSA 3D Working Group

eSilicon MoZAIC™ 2.5D Activities

Business Model

- Update July 2012

eSilicon • Ideas to ICs CONFIDENTIAL 2

Business Unit Synergy

2

Supply

Chain

Worldwide Engineering and Manufacturing Operations

IP ASIC

Customized IP Processes Scale

Systems

Customer

eSilicon

SMS


What We Do

Physical

Place & Route

Power: Analysis & Optimization

DFT

Formal verification

3

Functioning, High-Yielding, Cost-Effective Silicon, On Time

Design/IP

RTL

Netlist

SMS

En

gag

em

en

t L

evel

Design

& IP IP Creation Design (through

Design Partners)

IP

customization IP

customization IP

Customization

Operations Quality & Reliability

Assembly & Test Assembly & Test Assembly & Test Wafer fab Wafer fab Wafer Fab

Yield Enhancement

GDS-II

Logic Synthesis Simulation Verification

Timing: Analysis & Optimization

Product Engineering

Packagin

g Involv

em

ent

eSilicon • Ideas to ICs CONFIDENTIAL

Current Large ASIC

Architecture

Why push to a smaller

node?

Speed

Area

Memory capacity

What happens to yield

and cost with large die?

Doesn’t the IP work in

existing nodes already?

4

Logic

&

Routing

1T

Memory

1T

Memory

serdes serdes serdes serdes


DD

R

DD

R

DD

R

DD

R

mP mP

1T

Memory

1T

Memory

SOC

Low

speed

interfaces

not

shown


Possible Alternative One of many…

Very high number of connections between ASIC die and other tiles – handled by interposer

Connections to PCB greatly reduced

Lower cost, cheaper PCBs, less power etc.

5

Memory tile or stack

• Up to 16GB capacity

• 2 Tbps

• Die stack

ASIC • Smaller

• without embedded memory

• Serdes removed

• Older wafer node

• Processors would be

embedded or on top


serd

es

serd

es

serd

es

serd

es


Interposer

CPU


Basic 2.5D Structure

Silicon Interposer Example

6

Tiles such as logic, FPGA,

memory-stacks, IPD, etc.

Passive Silicon Interposer

Organic Laminate

Balls

Bumps

Microbumps


Interposer Solutions

Silicon Interposer

• Range of options

• Foundry/OSATs

• TSMC-only

• MEMS-type

• Limited interposer size

• Limited layers today

• Trace/space


Interposer Alternatives

Silicon Interposer Organic Interposer

Technology 100-400um thick wafers with TSVs and 4+1 metal layers

Organic-based materials, evolution of

PCB-technology. Multiple layers possible

Advantages Very fine pitch of 1um traces Compatible with silicon die

Larger sizes of 55x55mm possible

Compatible with underlying substrate

Issues Usually limited to max. reticle sizes of 32x26mm

Currently 8um trace/space, cannot (yet)

interface directly to finest-pitch 55um

pillars

Supply Chain TSMC if everything comes from them. Foundry/OSAT combinations if not.

Japanese suppliers in the forefront of

interposers, no foundry involved

Timeline Few designs so far but limited production starting (e.g. Xilinx).

Available now for 8um designs in 2012.

Production in 2013, expected to handle

5um at this point

Status Limited suppliers, some with restrictions (e.g. TSMC)

Many suppliers at coarse pitches, few at

fine.

Costs NREs not yet clear ~$80k? Will come down to


MoZAIC 2.5D/3D Concept

MoZAIC – “Modular Z-Axis IC”

New Custom Logic design approach keeps key, proven blocks unchanged

Only the base layer is customized

NRE is low because the base layer can be built in an older process

Top-layer functions reused and already proven in silicon

Best of both worlds: access to leading-edge functions with trailing-edge NRE

9

3D Si Stack

Si or Organic

Interposer

Package Substrate

IPD


MoZAIC Approach

Pick tiles from a menu

Enable partners access broad

customer base for tile reuse

Use smaller nodes only for higher

frequency

Low cost tapeout for silicon

interposer and lower speed

customization

FPGA tile for lower NRE entry

Adequately tested

Methodology for integration

10


Tile Example: Serdes Bar

40nm 28G-VSR Serdes

Can be cut into 1xX array

Requires 2um trace/space

on Si Interposer

40um microbump pitch

11

se

rde

s

AS

IC

HB

M

se

rde

s

se

rde

s

serdes serdes


Two Main Customer Types

Mobile/Handheld 3DIC

Low power

Smallest real-estate

Infrastructure/Networking 2.5D

Limitation on IO count

High Capacity/Bandwidth Memory

System Cost

High power handling

Low risk – silicon proven tiles

Reusability

12

CONFIDENTIAL

Bandwidth and Power

Trends in Memory Usage


What’s Out there?

14

WideIO

WideIO2

HBM High Bandwidth

Memory

HMC Hybrid Memory

Cube

LPDDR3

G4M

DDR3

DDR4

LPDDR2


Where do They Play?

15

pJ/bit

1

60

30

10

0 4 2

Bandwidth (Tb/s)

DDR3 DIMM

DDR4 DIMM

LPDDR3

WideIO

WideIO2

WideIO

Module

WideIO2

Module

HMC HBM

G4M


High Bandwidth Memory

(HBM)

Will completely change much of ASIC

architecture

Meant for interposer solutions such as

2.5D MoZAIC™

Early stage of standards formation

55um (tentative) bump pattern conducive to

Si-Interposer MoZAIC

Standard completion targeted at end on

2012

Likely availability in 2013/2014

1 Terabit per second initial target total

bandwidth

Targeting 2 Terabit total bandwidth later

16

Sig

nal

Supplie

s

Pro

be

DRAM Layers

CMOS Logic

Layer


Tezzaron G4M

Ultimate push to high bandwidth/low power

Similar to HBM purpose, but available much

sooner

Gen 2 parts available this year

Gen 4 parts available H1 2013

1-4 Terabit per second bandwidth per stack

Depends on port count

Usable on organic interposer at lower cost*

Available for immediate design start

17

* With reduced pin/port count accessible on memory


Current Issues

Non-Standardized Supply Chain

1. DIY Model with high complexity (KGD, KGS, Interposers, etc.)

2. Aggregated (TSMC) model

3. MoZAIC-style Model

Silicon interposer foundry availability slipped

Organic Interposer fine pitch readiness mid-2013

Lack of reliability data

Blurring of the lines

Earlier package interaction

Who tests what?

Who owns final yield?

Test infrastructure

Partial Probe or Full Probe

Both sides of interposer

Consignment of 3rd party “Tiles”

18


Summary

Significant progress over last 12 months

Both silicon and organic interposer technology ready

Memories ideal for 2.5D available/becoming available

Assembly, test, warranty, ownership issues need

real projects to drive discovery

eSilicon ready for the challenge!

19

CONFIDENTIAL

GSA 3D Working Group eSilicon MoZAIC 2.5D Activities...eSilicon • Ideas to ICs CONFIDENTIAL 3 What...

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