www.elsevier.com/locate/apsusc

Applied Surface Science 252 (2006) 7347–7351

Short communication

Growth of single-walled carbon

nanotubes on porous silicon

Rui Wang, Huaming Xu, Liqiu Guo, Ji Liang *

Department of Mechanical Engineering, Tsinghua University, Beijing 100084, China

Received 31 May 2005; accepted 27 August 2005

Available online 28 September 2005

Abstract

Porous silicon is an important and versatile material in the semiconductor industry, and can be achieved by electrochemically

etching silicon wafers. Employing porous silicon as substrates, this article presents a new approach to grow single-walled carbon

nanotubes on wafers for device applications. Free from support materials, this method is a clean one. At the same time it is

feasible and robust, as porous silicon is remarkably superior to polished surface in facilitating the nucleation of catalyst. The

superiority of porous silicon over polished surface is attributed to their different dewetting manners.

# 2005 Elsevier B.V. All rights reserved.

Keywords: Single-walled carbon nanotubes; Porous silicon; Synthesis; Silicon wafers; Dewetting

1. Introduction

Chemical vapor deposition (CVD) of single-

walled carbon nanotubes (SWNTs) on wafers is a

promising approach to integrate nanotubes into

electronic devices and structural systems. In many

instances, the key to success lies in the nano-scale

size of catalyst particles [1]. Thus it is essential to

develop novel methods to form catalyst nanopar-

itcles on substrates and prevent them from migrating

and sintering at elevated temperature. Various

approaches have so far been presented, classified

* Corresponding author. Tel.: +86 010 62782413.

E-mail address: wrui98@mails.tsinghua.edu.cn (J. Liang).

0169-4332/$ – see front matter # 2005 Elsevier B.V. All rights reserved

doi:10.1016/j.apsusc.2005.08.067

into dry methods and wet methods. In the case of

dry methods, very thin film of catalyst is sputtered

or deposited onto substrates [2]. And in the case of

wet methods, catalyst precursors are prepared in the

form of solution. Support materials such as Al2O3

are employed in many wet methods [3]. They make

these methods feasible and reliable, but possibly

lead to contamination. In order to avoid contamina-

tion from support materials, investigators have taken

efforts to search for new wet methods recently. For

example, laborious measures are taken to achieve

catalyst particles of the same size in solvents before

delivery [4]. In comparison, directly reducing the

thickness of the liquid films covered on wafers

seems to be a simpler one [5]. However, in demand

.

R. Wang et al. / Applied Surface Science 252 (2006) 7347–73517348

of smooth surface, this method is difficult to carry

out in practical device manufacture.

Here we focus on the modification of substrates and

present a new wet method to grow SWNTs on wafers

without support materials. In this method, Si wafers

are electrochemically etched before impregnation in

the solution of catalyst precursors, and porous silicon

(PS) rather than polished surface is employed as

substrates. Porous silicon is compatible with silicon

technology. As an important and versatile material in

the semiconductor industry, it has been intensely

investigated since 1990 [6]. With porous silicon as

substrates, the approach described here is as robust as

those using support materials, and can be directly

applied to wafers after patterning.

Fig. 1. Schematic process flow for the synthesis of SWNTs on

porous silicon.

2. Experiments

Porous silicon samples were prepared by electro-

chemical etching of n+ type Si(1 0 0) wafers

(resistivity 0.001–0.005 V cm). Etching was carried

out without illumination for 15 min. The electrolyte

contained one portion of hydrogen fluoride (50%

aqueous solution), one portion of ethanol and two

portions of water. The anodization current density was

kept constant at 30 mA/cm2. The resulting substrates

were then annealed in air at 300 8C overnight to

protect their porous structure from collapsing later in

the high-temperature CVD process.

As-grown porous silicon substrates were impreg-

nated in the ethanol or aqueous solution of Fe(NO3)3

for a few minutes. Excess solution was removed and

the substrates were dried in ambient air. Subsequently,

the samples were placed in a quartz boat and inserted

into the center of 1 in. tube reactor housed in a furnace.

The furnace was heated to 900 8C in flowing Ar. The

reaction began as Ar was replaced by CH4 (flow rate

1000 sccm). After 15 min, the flow was switched to Ar

and the furnace was cooled to room temperature. The

whole process is sketched out in Fig. 1.

The results were characterized with SEM and

TEM. Electron-transparent samples for TEM were

prepared by direct cleavage from the porous wafer

surface [7]. In details, a sharp scalpel blade was

drawn carefully across the surface, causing the

porous layer to fracture and yield fragments of many

sizes. These fragments were collected and sonicated

in ethanol. A few drops of ethanol containing

sufficient material were dropped onto specimen grids

for TEM analysis.

3. Result and discussion

The typical images of porous silicon are shown in

Fig. 2. The cross section (Fig. 2a) indicates that porous

silicon layers have the dendrite morphology for

heavily doped n wafers. According to the plan view

(Fig. 2b), micropores are exposed on wafer surface.

The diameter of pores depends on etching parameters

such as electrolyte composition, dopant concentration

and anodization current density. Under the condition

described above, most pores have the diameter of

�10 nm. In our experiments, the pore diameter was

varied within a wide range by controlling etching

parameters. However, the variation in the pore size has

been found to have little effect on the growth of

SWNTs. The cause will be discussed in the latter

paragraph.

R. Wang et al. / Applied Surface Science 252 (2006) 7347–7351 7349

Fig. 2. TEM micrographs of porous silicon. (a) Cross section. (b)

Plan view.Fig. 3. SWNTs attached to the fragments of porous silicon.

Fig. 4. The SEM micrograph of SWNTs grown on porous silicon

layers.

After the CVD process, wafers with CNTs were

carefully observed under SEM and TEM. TEM

analysis has proved almost all nanotubes to be

single-walled. Typical images are given in Fig. 3. In

these figures, SWNTs extend from the surface of

porous silicon. SWNTs are straight and have a good

quality. Only a little amorphous carbon sticks to them.

The SEM images present the distribution of SWNTs

on porous silicon layers, as shown in Fig. 4. The

Fe(NO3)3 concentration corresponding to this figure is

15 mg/ml. Here the white lines are SWNTs or thin

SWNT bundles, and the bright dots represent catalyst

nanoparticles. A gap was purposely created to show

nanotubes more clearly. Dark shadow is artificial and

caused by magnetism of catalyst. SWNTs go through

catalyst particles, close to the surface. Most SWNTs

are several micrometers in length. In contrast to the

web-like morphology previously reported, as-grown

SWNTs (or bundles) have free ends and are isolated

with one another. All these features are beneficial to

the application of SWNT devices.

Investigation into the dominant factors indicates

that this approach is a reliable one. Various growth

R. Wang et al. / Applied Surface Science 252 (2006) 7347–73517350

conditions adopted in the traditional approaches,

for example CH4 1080 sccm/H2 125 sccm/900 8Cor C2H4 10 sccm/Ar 600 sccm/H2 400 sccm/750 8C[8,9], are applicable to this method. The remarkably

different concentration of Fe(NO3)3 solution will

lead to the growth of SWNTs. Moreover, the

morphology is similar except that the density of

SWNTs is varied from the Fe(NO3)3 concentration.

A wide range from 150 mg/ml to 25 mg/ml has been

tested to prove it. Compared with this, as polished

wafers are directly used as substrates, a very low

concentration of catalyst solution is required [10].

Besides ferric salts, other catalyst systems such as

Fe/Mo and Co/Mo are being tried for this approach,

and feasibility is expected.

In the following paragraphs, the function that

porous silicon layers perform during the formation

of catalyst nanoparticles will be discussed. To

understand it, wafers with catalyst were observed in

a higher magnification under SEM. The resulting

figures (such as Fig. 5) indicate that only a few

catalyst nanoparticles are embedded in pores, and

the others are dispersed on surface. That is to say, in

this approach porous silicon layers function as

support materials rather than templates, which is

similar to Al2O3 or MgO in the mass-production of

SWNTs. Thus catalyst nanoparticles are not

identical to the pores in dimension. This point

would explain why the pore diameter of porous

silicon layers has little effect on the growth of

SWNTs.

Fig. 5. Catalyst nanoparticles dispersed on porous silicon.

As support materials, porous silicon is superior to

polished surface because of different dewetting

manners. In the case of polished wafers, liquid film

will shrink across the whole surface, probably leading

to residual solution and large-size particles. Thus in

order to form catalyst nanoparticles with the uniform

distribution on silicon wafers, perfect surface is

required and additional measures should be taken.

In contrast, in the case of porous silicon, the manner of

dewetting is from surface to interior. As wafers are

dried, liquid film on surface would shrink into the

nearby pores. That means dewetting is restricted

within a very small area. This dewetting manner

inhibits the growth of catalyst particles, so it is

favorable to the formation of nanoparticles.

4. Conclusion

In conclusion, we present a new wet method to

grow separated SWNTs on wafers for device

applications. In this method, silicon wafers are

electrochemically etched and the resulting porous

silicon layers are employed as substrates to grow

SWNTs. Porous silicon is a developed material in

semiconductor industry and compatible with prac-

tical silicon technology. Compared with polished

surface, porous silicon layers are more beneficial to

the formation of catalyst nanoparticles with the

uniform distribution. Different dewetting manners

would be responsible for it. With porous silicon as

substrates, the method described here is simple and

robust, and can be directly applied to wafers after

patterning.

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