Government Polytechnic Muzaffarpur. Name of the Lab: Computer Organization & Architecture

Practical: Computer Organization &Architecture

Subject Code: 1618308

1. Write a program in C-language to implement the digital gates. The program

should give the truth table of the gate, which is selected by the user from the menu

displayed by the program.

#include<stdio.h>

int And(int a, int b);

int Or(int a, int b);

int Not(int a);

void main()

{

///where main body of code will go

}

int And(int a, int b)

{

int output;

if(a==0 && b==0)

output=0;

if(a==1 && b==0)

output=0;

if(a==0 && b==1)

output=0;

if(a==1 && b==1)

output=1;

return (output);

}

int Or(int a, int b)

{

int output;

if(a==0 && b==0)

output=0;

if(a==1 && b==0)

output=1;

if(a==0 && b==1)

output=1;

if(a==1 && b==1)

output=1;

return (output);

}

int Not(int a)

{

int output;

if(a==0 )

output=1;

if(a==1 )

output=0;

return (output);

}

Logic gates

Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT,

NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with the aid of truth

tables.

AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are

high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is

sometimes omitted i.e. AB

OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs

are high. A plus (+) is used to show the OR operation.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It

is also known as an inverter. If the input variable is A, the inverted output is known as NOT

A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams

below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can

also be done using NOR logic gates in the same way.

2. Write a program in C-language to implement division algorithm.

#include <stdio.h>

int main(){

int dividend, divisor, quotient, remainder;

printf("Enter dividend: ");

scanf("%d", &dividend);

printf("Enter divisor: ");

scanf("%d", &divisor);

// Computes quotient

quotient = dividend / divisor;

// Computes remainder

remainder = dividend % divisor;

printf("Quotient = %d\n", quotient);

printf("Remainder = %d", remainder);

return 0;

}

3. Give the presentation on 74xx series IC for gates.

PROCEDURE:

Part 1 Examine the breadboard. The breadboard can be set up with both switches (for inputs) and Light

Emitting Diodes, LEDs (for outputs). This board is used when for testing circuit designs. The circuit

designs and programs should be created prior to coming to lab. Investigate the breadboard and

determine where the lines of continuity are (what lines of holes are connected to other lines of holes). Part 2 Identify the 7400 Series TTL gates and look up their data sheets; 7400, 7404, 7408 and 7432

find the gate pin outs for each chip. Describe in your lab report each of their functions. Also show their

logic symbol, use the function in an equation and show the Truth Table for one gate in each of the

integrated circuits. This needs to be done for each of the four integrated circuits (ICs) (chips). Part 3 Gate testing: Test each gate in the simulator (MultiSim). Verify the truth table of each gate.

Create a truth table base on the information gathered in part 2, have a columns for both inputs (count in binary), a column for the output based on gate specification, another for the simulator results, and the last output column for the lab results.

After testing each gate in the simulator, build up each gate on the breadboard. Use the components from

the lab kit. Select the 7404 (a package of six INVERTERs – usually called a hex INVERTER package).

Place the 7404 chip across the center line (horizontal line) of your white breadboard and seat the device

firmly (push down) on the breadboard. Find the dot that marks Pin 1 (most device have a notch at one end

– if so, Pin 1 is to the left of the notch and on the corner of the device.) Viewed from the top, pin numbers

always go counter-clockwise. Using RED wire, connect Pin 14 to +5 volts. Using BLACK wire, connect

Pin 7 to GROUND. One of the six INVERTERS has its input pin on Pin 1, and its corresponding output

on Pin 2. Connect the INVERTER’s input to a switch and the output to an LED. Test to see if the function

works properly. Compare this output data to the truth table for this device. Go on and test to the other five

“gates” as we call them. When you complete the 7404 IC, continue testing the other three Integrated

Circuits (ICs). The 7400 is a quad NAND gate, the 7408 is a quad AND gate, and the 7432 is a quad OR

gate. Test each gate of each Integrated Circuit (IC). Record your results for your lab report. Since each

gate had two inputs, you must use two switches for each gate. You still only need one LED for the one

output of each gate. Part 4 Test all four chips together, there should be two inputs and four outputs, there should be an

output for each function or gate type. Before building the circuit on the breadboard test the circuit in the

simulator (MultiSim). Wire up one LED to each of the gate function’s output. ALL the LEDs are connected at the same time.

There should be 4 LEDs used: one for the NAND (7400), one for the NOT or Inverter (7404), one for the

AND (7408), and one for the OR (7432). That takes care of the outputs. For the inputs you only need two

switches that will connect to each gate. {note: the 7404 (inverter) only needs one switch connected to the

input}. Your complete the circuit; it will have a total of 4 LEDS, and 2 switches (along with 4 ICs). Test

and record the functions by observing the 4 outputs when you place the 4 possible input patterns – 00, 01,

10, 11 on the switches. Create a schematic for this Part and put it in your lab report.

Breadboard example 7400 IC Chip Circuit Diagram 7400 package and

pins showing pin outs

Here is some information about the 7400 Series TTL Integrated Circuits:

Dot near pin 1 or Notch at top center

PIN 1 PIN 14, +5 volts

PIN 2 PIN 13

PIN 3 PIN 12

PIN 4 PIN 11

PIN 5 PIN 10

PIN 6 PIN 9

PIN 8

Ground, PIN 7

Top View of a 14 pin 74xx device

Dual In-Line Package (DIP)

1. The transistor and inverter

Exhibit 1.2: Breadboard Exhibit 1.3: Common

connections The breadboard In order to build the circuit, a digital design kit that contains a power supply, switches for

input, light emitting diodes (LEDs), and a breadboard will be used. Make sure to follow your

instructor's safety instructions when assembling, debugging, and observing your circuit. You

may also need other items for your lab such as: logic chips, wire, wire cutters, a transistor,

etc. Exhibit 1.2 shows a common breadboard, while Exhibit 1.3 shows how each set of pins

are tied together electronically. Exhibit 1.4 shows a fairly complex circuit built on a

breadboard. For these labs, the highest voltage used in your designs will be five volts or +5V

and the lowest will be 0V or ground.

A few words of caution regarding the use of the breadboard:

• Keep the power off when wiring the circuit.

• Make sure to keep things neat, as you can tell from Exhibit 1.4, it is easy for designs

to get complex and as a result become difficult to debug.

• Do not strip more insulation off of the wires used than is necessary. This can cause

wires that are logically at different levels to accidentally touch each other. This

creates a short circuit.

• Do not push the wires too far into each hole in the breadboard as this can cause two

different problems.

• The wire can be pushed so far that only the insulation of the wire comes

into contact with the breadboard, causing an open circuit.

• Too much wire is pushed into the hole; it curls under and ends up touching

another component at a different logical level. This causes a short circuit.

• Use the longer outer rows for +5V on one side and ground on the other side.

• Wire power to the circuit first using a common color (say red) for +5V and another

(black) for ground.

• Always make sure to have a clearly documented circuit diagram before you start

wiring the circuit.

4. Give the presentation on combinational circuits such as multiplexer,

decoder, encoder etc. Multiplexer

In electronics, a multiplexer or mux is a device that selects one of several analog or digital

input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has

n select lines, which are used to select which input line to send to the output. An electronic

multiplexer can be considered as a multiple-input, single-output switch i.e. digitally

controlled multi-position switch. The digital code applied at the select inputs determines

which data inputs will be switched to output.

A common example of multiplexing or sharing occurs when several peripheral devices share

a single transmission line or bus to communicate with computer. Each device in succession is

allocated a brief time to send and receive data. At any given time, one and only one device is

using the line. This is an example of time multiplexing since each device is given a specific

time interval to use the line.

In frequency multiplexing, several devices share a common line by transmitting at different

frequencies.

.

Table : Truth Table of 8:1 MUX

Fig : Logic Diagram of 8:1 MUX

Demultiplexer

A demultiplexer (or demux) is a device taking a single input signal and selecting one of many

data-output-lines, which is connected to the single input. A multiplexer is often used with a

complementary demultiplexer on the receiving end. A demultiplexer is a single-input,

multiple-output switch. Demultiplexers take one data input and a number of selection inputs,

and they have several outputs. They forward the data input to one of the outputs depending

on the values of the selection inputs.

Demultiplexers are sometimes convenient for designing general purpose logic, because if the

demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any

function of the selection bits can be constructed by logically OR-ing the correct set of

outputs. Demultiplexer is called as a ‘distributro’, since it transmits the same data to different

destinations.

Table : Truth Table of 1:8 DEMUX

Fig : Logic Diagram of 1:8 DEMUX

Decoder

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic

circuit that converts coded inputs into coded outputs, where the input and output codes are

different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in applications

such as data multiplexing, 7 segment display and memory address decoding.

The example decoder circuit would be an AND gate because the output of an AND gate is

"High" (1) only when all its inputs are "High." Such output is called as "active High output".

If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when

all its inputs are "High". Such output is called as "active low output".

A slightly more complex decoder would be the n-to-2n type binary decoders. These types of

decoders are combinational circuits that convert binary information from 'n' coded inputs to a

maximum of 2n unique outputs. In case the 'n' bit coded information has unused bit

combinations, the decoder may have less than 2n outputs. 2-to-4 decoder, 3-to-8 decoder or

4-to-16 decoder are other examples.

The input to a decoder is parallel binary number and it is used to detect the presence of a

particular binary number at the input. The output indicates presence or absence of specific

number at the decoder input.

Let us suppose that a logic network has 2 inputs A and B. They will give rise to 4 states A,

A’, B, B’ . The truth table for this decoder is shown below:

Table : Truth Table of 2:4 decoder

Fig : Logic Diagram of 2:4 decoder

Fig : Representation of 2:4 decoder

For any input combination only one of the outputs is low and all others are high. The low

value at the output represents the state of the input.

Decoder expansion

Combine two or more small decoders with enable inputs to form a larger decoder e.g. 3-to-8-

line decoder constructed from two 2-to-4-line decoders.

Decoder with enable input can function as demultiplexer.

3:8 decoder

It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs,

NAND gates are used. It has 3 input lines and 8 output lines. It is also called as binary to

octal decoder it takes a 3-bit binary input code and activates one of the 8(octal) outputs

corresponding to that code. The truth table is as follows:

Table : Truth Table of 3:8 decoder

Fig : Logic Diagram of 3:8 decoder

Encoder

An encoder is a device, circuit, transducer, software program, algorithm or person that

converts information from one format or code to another. The purpose of encoder is

standardization, speed, secrecy, security, or saving space by shrinking size. Encoders are

combinational logic circuits and they are exactly opposite of decoders. They accept one or

more inputs and generate a multibit output code.

Encoders perform exactly reverse operation than decoder. An encoder has M input and N

output lines. Out of M input lines only one is activated at a time and produces equivalent

code on output N lines. If a device output code has fewer bits than the input code has, the

device is usually called an encoder.

Octal to binary encoder

Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-

to-8 decoder does. At any one time, only one input line has a value of 1. The figure below

shows the truth table of an Octal-to-binary encoder.

Table : Truth Table of octal to binary encoder

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2

are:

Y0 = I1 + I3 + I5 + I7

Y1= I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 +I7

Fig : Logic Diagram of octal to binary encoder

Priority encoder

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a

smaller number of outputs. The output of a priority encoder is the binary representation of the

ordinal number starting from zero of the most significant input bit. They are often used to

control interrupt requests by acting on the highest priority request. It includes priority

function. If 2 or more inputs are equal to 1 at the same time, the input having the highest

priority will take precedence. Internal hardware will check this condition and priority is set.

Table : Truth Table of 4 bit priority encoder/p>

Fig : Logic Diagram of 4 bit priority encoder

IC 74148 is an 8-input priority encoder. 74147 is 10:4 priority encoder

5. Give the presentation on sequential circuits such as registers, counters

etc.

1. Registers

When a group of the flip flop is used to store a word ( a group of bits) then it is called

register. To store n bits, n flip flops are cascaded in the register. If in a register, the

binary information can be moved from stage to stage, this type of registers is called

shift registers. According to data movement in a register, shift registers can be

classified as

Serial Input Serial Output (SISO)

Serial Input Parallel Output (SIPO)

Parallel Input Serial Output (PISO)

Parallel Input Parallel Output (PIPO)

Serial Input Serial Output (SISO)

In registers edge trigger circuit used to make circuit synchronous.

If no clock is applied then get same data which is stored.

In N bits SISO registers to provide N bits data, Serially in require N clock

pulse, and Serially out require (N-1) clock pulse.

Serial Input Parallel Output (SIPO)

To provide N-bit data: Serial in requires N clock pulse, and Serial out requires

no clock pulse.

SISO can provide n × tCIK delay to the input.

SISO can convert serial data or temporal code to parallel or serial code.

Parallel Input Serial Output (PISO)

If control = 0 then it acts as parallel input;

If control = 1 then it acts as serial output;

To provide parallel input, one clock pulse is required.

To provide N bits serial output, it requires (N-1) clock pulse.

PISO can convert special code to temporal code.

Parallel Input Parallel Output (PIPO)

In PIPO register for parallel input number of pulse required is 1 clock pulse.

In PIPO register for parallel output number of pulse required is 0 clock pulse.

PIPO register cannot be used as a shift register.

It is used for temporal storage of data in microcontroller, DSP, CPU etc.

Summary of Registers

2. Counter

A counter is a sequential logic circuit capable of counting the number of clock

pulses arriving at its clock input.

The sequence of count may be ascending, descending or non-sequence.

For a counter circuit having n flip flops, Maximum possible states (N) = 2n

If N = 2n , the counter acts as a binary counter.

If N < 2n , the counter the non-binary counter.

It counter is capable to count from 0 to 2n-1.

MOD number is the Number of states present in a counter is known as modulus

count or MOD number.

For n-flip flops, the counter will have 2n different states then this counter is

said MOD- 2n counter.

MOD-M Counter

MOD number indicates frequency division obtained from the last flip flops.

Cascaded two counters:

MOD-MN counter:

o Overall states of combined counter = MN

o Input frequency = f

o Output frequency f = f/(MN)

3. Classification of Counters

Based upon the applying clock pulse, counters are classified into two categories.

Synchronous counter

Asynchronous counter (ripple counter)

4. Toggle Mode Circuit

These are frequency dividers circuit.

Other Toggle Mode Circuit

5. Asynchronous Counter (Ripple counter)

A different clock pulse is applied to different flip flops.

All flip flops are operating in toggle mode.

In asynchronous counter flip flop applied with external clock acts as LSB bit.

3-bit Ripple Up Counter

Input clock is applied at LSB bit.

It n-bit ripple counter maximum possible states are 2n.

Bit ripple up counter counts from 0 to 2n - 1.

If all states are used then with input frequency f, then output frequency will be

f/2n

Calculation of Time Period of Flip Flop: In n-bit ripple counter if propagation

delay of each flip flop is tpd(FF), then the time period of the clock is:

TCLK ≥ ntpd(FF)

Maximum Clock Frequency:

Due to propagation delays of flip flops decoding errors are present.

Clear and preset are known as asynchronous input to flip flop.

In any ripple counter, the following conditions will fulfil

o Negative edge trigger and Q as clock ⇒ up counter

o Positive edge trigger and Q as clock ⇒ up counter

3-bit Ripple Down Counter

Positive edge trigger and Q as clock ⇒ down counter

Negative edge trigger and Q as clock ⇒ down counter

Non-binary Ripple Counter

Decode counter or BCD counter is an example of a non-binary counter. It requires 4

flip flops.

Used state = 10 and unused states = 6 → (24 -10)

Output frequency of BCD counter = f/10

For making non-binary counter clear (clr) signal is used.

c1r is active high, and (clr)' is active low.

6. Synchronous Counters

In this type of counter, there are no connections of first flip flop output to a

clock input of the next flip flop.

Ring Counter: It is a circular shift register with only flip flop being set at any

particular time, all others are cleared. It is a shift register with feedback.

In ring counter, if feedback is used the number of states is reduced.

With n flip flops maximum states = n.

Number of unused states in ring counter = 2n – n

Maximum Clock Frequency: If input frequency is f , then at the output of every

flip flop we get f/N frequency. In ring counter, if propagation delay of each flip

flop is tpd(FF) then

TCLK ≥ tpd(FF);

Jhonson Ring Counter: Jhonson ring counter is also called as a Twisted ring counter,

Switch tail counter, Creeping counter, or Mobies counter.

In n - bit Jhonson counter maximum used states = 2n, unused states = 2n - 2n.

If input clock frequency is f, the output frequency of each flip flop is f /2n and

the duty cycle is 50%.

A disadvantage of Jhonson Ring Counter: Lockout may occur. To decode each

state one, two input AND or NOR gate is used.

There are mainly four types of flip flops that are used in electronic circuits. They are

1. The basic Flip Flop or S-R Flip Flop

2. Delay Flip Flop [D Flip Flop]

3. J-K Flip Flop

4. T Flip Flop

1. S-R Flip Flop

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND

gates. These flip flops are also called S-R Latch.

S-R Flip Flop using NOR Gate

The design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There

are also two outputs, Q and Q’. The diagram and truth table is shown below.

S-R Flip Flop using NOR Gate

From the diagram it is evident that the flip flop has mainly four states. They are

S=1, R=0—Q=1, Q’=0

This state is also called the SET state.

S=0, R=1—Q=0, Q’=1

This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the

value of Q follows the value of S.

S=0, R=0—Q & Q’ = Remember

If both the values of S and R are switched to 0, then the circuit remembers the value of S and

R in their previous state.

S=1, R=1—Q=0, Q’=0 [Invalid]

This is an invalid state because the values of both Q and Q’ are 0. They are supposed to be

compliments of each other. Normally, this state must be avoided.

S-R Flip Flop using NAND Gate

The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.

S-R Flip Flop using NAND Gate

Like the NOR Gate S-R flip flop, this one also has four states. They are

S=1, R=0—Q=0, Q’=1

This state is also called the SET state.

S=0, R=1—Q=1, Q’=0

This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the

value of Q follows the compliment value of S.

S=0, R=0—Q=1, & Q’ =1 [Invalid]

If both the values of S and R are switched to 0 it is an invalid state because the values of both

Q and Q’ are 1. They are supposed to be compliments of each other. Normally, this state must

be avoided.

S=1, R=1—Q & Q’= Remember

If both the values of S and R are switched to 1, then the circuit remembers the value of S and

R in their previous state.

Clocked S-R Flip Flop

It is also called a Gated S-R flip flop.

The problems with S-R flip flops using NOR and NAND gate is the invalid state. This

problem can be overcome by using a bistable SR flip-flop that can change outputs when

certain invalid states are met, regardless of the condition of either the Set or the Reset inputs.

For this, a clocked S-R flip flop is designed by adding two AND gates to a basic NOR Gate

flip flop. The circuit diagram and truth table is shown below.

Clocked S-R Flip Flop

A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse

is ‘0’, the outputs of both the AND Gates remain ‘0’. As soon as a pulse is given the value of

CP turns ‘1’. This makes the values at S and R to pass through the NOR Gate flip flop. But

when the values of both S and R values turn ‘1’, the HIGH value of CP causes both of them

to turn to ‘0’ for a short moment. As soon as the pulse is removed, the flip flop state becomes

intermediate. Thus either of the two states may be caused, and it depends on whether the set

or reset input of the flip-flop remains a ‘1’ longer than the transition to ‘0’ at the end of the

pulse. Thus the invalid states can be eliminated.

2. D Flip Flop

The circuit diagram and truth table is given below.

D Flip Flop

D flip flop is actually a slight modification of the above explained clocked SR flip-flop. From

the figure you can see that the D input is connected to the S input and the complement of the

D input is connected to the R input. The D input is passed on to the flip flop when the value

of CP is ‘1’. When CP is HIGH, the flip flop moves to the SET state. If it is ‘0’, the flip flop

switches to the CLEAR state.

To know more about the triggering of flip flop click on the link below.

TAKE A LOOK : TRIGGERING OF FLIP FLOPS

TAKE A LOOK : MASTER-SLAVE FLIP FLOP CIRCUIT

3. J-K Flip Flop

The circuit diagram and truth-table of a J-K flip flop is shown below.

J-K Flip Flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference

is that the intermediate state is more refined and precise than that of a S-R flip flop.

The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J

stands for SET and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement

state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.

The circuit includes two 3-input AND gates. The output Q of the flip flop is returned back as

a feedback to the input of the AND along with other inputs like K and clock pulse [CP].

So, if the value of CP is ‘1’, the flip flop gets a CLEAR signal and with the condition that the

value of Q was earlier 1. Similarly output Q’ of the flip flop is given as a feedback to the

input of the AND along with other inputs like J and clock pulse [CP]. So the output becomes

SET when the value of CP is 1 only if the value of Q’ was earlier 1.

The output may be repeated in transitions once they have been complimented for J=K=1

because of the feedback connection in the JK flip-flop. This can be avoided by setting a time

duration lesser than the propagation delay through the flip-flop. The restriction on the pulse

width can be eliminated with a master-slave or edge-triggered construction.

4. T Flip Flop

This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected

together and thus are also called a single input J-K flip flop. When clock pulse is given to the

flip flop, the output begins to toggle. Here also the restriction on the pulse width can be

eliminated with a master-slave or edge-triggered construction. Take a look at the circuit and

truth table below.

T Flip F

6. Give the presentation on Von Neumann Architecture of a computer

system.

Von Neumann architecture

In the 1940s, a mathematician called John Von Neumann described the basic arrangement (or

architecture) of a computer. Most computers today follow the concept that he described

although there are other types of architecture. When we talk about the Von Neumann

architecture, we are actually talking about the relationship between the hardware that makes

up a Von Neumann-based computer.

A Von Neumann-based computer is a computer that:

Uses a single processor.

Uses one memory for both instructions and data. A von Neumann computer cannot

distinguish between data and instructions in a memory location! It ‘knows’ only

because of the location of a particular bit pattern in RAM.

Executes programs by doing one instruction after the next in a serial manner using a

fetch-decode-execute cycle.

In this chapter, we are going to build upon and refine the ideas introduced in an earlier

chapter. You should re-read the relevant chapter on CPUs before you start this one. We have

already said that the CPU was made up of 4 important components:

The ALU.

The registers.

The control unit.

The IAS (otherwise known as RAM or memory).

Because the IAS is so important, we are definitely going to move it to its own section in our

model of a computer. (We discussed this previously). We need to get data into and out of the

computer so we will include this as a separate section as well. We will also introduce the idea

of a clock and clock cycles in the CPU. Our new model of a computer now looks like this:

Von Neumann Component 1 - The CPU The CPU, or Central Processing Unit, is the name given to the component that controls the

computer and works on the data. It can be split up into four sub-components:

We know a few things from before about the Von Neumann CPU

1) The ALU, or Arithmetic Logic Unit A Von Neumann CPU has an ALU. This is the part of the CPU that performs arithmetic

and logic operations on data and acts as the revolving for the CPU, letting data enter and

leave the CPU. We also know that CPUs have a ‘word size’. This is the number of bits

that can be added, for example, in one go. The bigger a CPU’s word size, the more bits it

can work on in one clock cycle and the more work you can get done.

2) The Control Unit A Von Neumann CPU has a control unit. The control unit is in charge of ‘fetching’ each

instruction that needs to be executed in a program by issuing control signals to the

hardware. It then decodes the instruction and finally issues more control signals to the

hardware to actually execute it.

3) Registers A Von Neumann CPU has registers. These are very fast memory circuits. They hold

information such as the address of the next instruction (Program Counter), the current

instruction being executed (Current Instruction Register), the data being worked on and

the results of arithmetic and logical operations (Accumulators), information about the

last operation (Status Register) and whether an interrupt has happened (Interrupt

Register). Registers are covered in a lot more detail later in this chapter.

4) The clock Instructions are carried out to the beat of the clock! Some instructions take one beat and

others more than one beat. Very roughly speaking, the faster the clock, the more clock

beats you have per second so the more instructions per section you can do and the faster

your computer will go.

Von Neumann Component 2 - IAS We also know that the Von Neumann computer has an IAS, or Immediate Access Store,

where it puts both programs and data. We often commonly refer to this memory as RAM.

RAM is made up of lots of boxes that can store a bit pattern. Each box has a unique

address. A memory address might store an instruction (which is made up of an operator and

an operand) or it might store just a piece of data. A Von Neumann computer can’t tell the

difference between the bit patterns as such, but ‘knows’ indirectly because of where the bit

pattern is stored in RAM. Pre-Von Neumann computers used to split up memory into

program memory and data memory and this made computers relatively complex. Von

Neumann was the first to realise that there was actually no difference between the nature of

an instruction and the nature of a piece of data. One important function of an operating

system is to manage memory and to keep track of the RAM addresses of applications as well

as any data.

We also know that computers have an address bus, so that the CPU can address each

individual memory location in the IAS, for example, when it wants to store a piece of data or

retrieve a piece of data. The data itself is moved about between devices on a data bus. There

is also a control bus, to generate signals to manage the whole process.

Von Neumann Component 3 - I/O A computer needs peripherals for inputting and outputting data. It needs to be able to read

data into itself and send data out. It reads data in and sends data out through its I/O ports. A

port is simply a gateway, like a port used for shipping. Just like every port used for ships

needs its own harbour master, so every I/O port needs to be managed. An I/O controller is the

term used to describe the I/O port along with the circuits that manage data into and out of the

port. It allows you to connect up any I/O device to the PC and transfer data in to or out of the

computer. You wouldn’t want to connect an I/O device directly to a CPU because you would

have to redesign the CPU every time a new type of device came along. Besides, a new type of

device might need different voltages and control signals from the CPU, again necessitating a

CPU redesign. The I/O controller acts as an interface to overcome these problems. Refining

the diagram we saw in the previous chapter on CPUs, we now have:

A computer system showing the I/O controllers. Of course, there are a whole range of other I/O controllers we could have included. We could

have shown ones for devices such as a mouse, a MIDI device, a printer, a DVD player, a

SCSI device as used with many scanners or a network card, to name just a few.

Von Neumann bottleneck Whatever you do to improve performance, you cannot get away from the fact that

instructions can only be done one at a time and can only be carried out sequentially. Both of

these factors hold back the efficiency of the CPU. This is commonly referred to as the 'Von

Neumann bottleneck'. You can provide a Von Neumann processor with more RAM, more

cache or faster components but if real gains are to be made in CPU performance then a major

review needs to take place of CPU design.

7. Give the presentation on money management i.e. virtual memory, cache

memory, paging etc.

Memory Management

Memory management is an important activity done effectively in the kernel. Memory

management is the process of managing the computer memory. ie, This includes assigning

memory to various running programs to keep the performance of the system stable. The

memory should be allocated dynamically according to the requirement and it should be freed

up when no longer used, so that it can be reallocated when needed. Memory management

depends on effective configuration in hardware, operating system, and programs or

applications. In hardware, memory management involves physical devices that store the data.

The Random-Access Memory is an example for this. This also includes memory caches and

flash based Solid-State Drives. In the case of OS, memory management involves allocation of

specific memory blocks to individual programs as user demand changes. At the application

level, memory management ensures the memory demanded by the objects and data structures

of each running program is available always. Modern computers manage memory at two

levels; at the system levels and at the application level. The application level memory

management is categorized as either automatic or manual memory management. In this

article, we are going to see the memory management based on virtual memory and demand

paging.

Virtual Memory

Virtual memory is a memory management technique that can be implemented using both

hardware and software. As the name indicates, it adds virtual memory to available memory,

so that your system will appear to have more memory than what actually exists. Virtual

memory is a layer of memory addresses (virtual addresses) that map to physical addresses.

The memory addresses used by a program is the virtual addresses. These virtual address

spaces and the assignment of real memory to the virtual memory are managed by the

operating system. The working of virtual memory is as follows. The computer system has a

limited amount of Static RAM. When a program gets executed, an instance of the program is

loaded into the RAM. This is the process of allocating the memory for the instructions to

execute.

When the program demands more RAM than available, it will be allocated to the virtual

memory. This prevents the program from lacking the necessary RAM to execute. This virtual

memory is actually the memory of the hard disk and it is then mapped into the physical

memory.

Demand Paging

Demand paging is a type of swapping done in virtual memory systems. In demand paging,

the data is not copied from the disk to the RAM until they are needed or being demanded by

some program. The data will not be copied when the data is already available on the memory.

This is otherwise called a lazy evaluation because only the demanded pages of memory is are

swapped from the secondary storage (disk space) to the main memory. In contrast during

pure swapping all the memory for a process is swapped from secondary storage to main

memory during the process startup.

Anticipatory Paging

The anticipatory paging is another type of swapping in virtual memory systems. Here, the

operating system attempts to anticipate the data that will be needed next and copies it to

RAM before it is actually required.

Demand Paging Working

The demand paging working is based on a page table implementation. The page table maps

logical memory to physical memory. The page table uses a bitwise operator to mark if a page

is valid or invalid. A valid page is one that currently resides in main memory. An invalid

page can be defined as the one that currently resides in secondary memory. When a process

tries to access a page, the following will happen.

1) Attempt to access page

2) The page is valid. Page processing instruction continues as normal.

3) If the page is invalid one, then a page-fault trap occurs.

4) The memory reference is then checked to determine if it is a valid reference to a location

on secondary memory or not. If not, the process is terminated (illegal memory access).

Otherwise, the required page is paged in.

5) Now the disk operation to read the desired page into main memory is scheduled.

6) Finally the instruction that was interrupted by the operating system trap is restarted.

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cache memory

Cache memory: It is also called CPU memory, is random access memory (RAM) that a

computer microprocessor can access more quickly than it can access regular RAM.

This memory is typically integrated directly with the CPU chip or placed on a

separate chipthat has a separate bus interconnect with the CPU.

The basic purpose of cache memory is to store program instructions that are frequently re-

referenced by software during operation. Fast access to these instructions increases the

overall speed of the software program.

As the microprocessor processes data, it looks first in the cache memory; if it finds the

instructions there (from a previous reading of data), it does not have to do a more time-

consuming reading of data from larger memory or other data storage devices.

Most programs use very few resources once they have been opened and operated for a time,

mainly because frequently re-referenced instructions tend to be cached. This explains why

measurements of system performance in computers with slower processors but larger caches

tend to be faster than measurements of system performance in computers with faster

processors but more limited cache space.

Multi-tier or multilevel caching has become popular in server and desktop architectures,

with different levels providing greater efficiency through managed tiering. Simply put, the

less frequently access is made to certain data or instructions, the lower down the cache level

the data or instructions are written.

Cache memory levels explained

Cache memory is fast and expensive. Traditionally, it is categorized as "levels" that describe

its closeness and accessibility to the microprocessor:

Level 1 (L1) cache is extremely fast but relatively small, and is usually embedded in the

processor chip (CPU).

Level 2 (L2) cache is often more capacious than L1; it may be located on the CPU or on

a separate chip or coprocessor with a high-speed alternative system bus interconnecting

the cache to the CPU, so as not to be slowed by traffic on the main system bus.

Level 3 (L3) cache is typically specialized memory that works to improve the

performance of L1 and L2. It can be significantly slower than L1 or L2, but is usually

double the speed of RAM. In the case of multicore processors, each core may have its

own dedicated L1 and L2 cache, but share a common L3 cache. When an instruction is

referenced in the L3 cache, it is typically elevated to a higher tier cache.

Memory cache configurations

Caching configurations continue to evolve, but memory cache traditionally works under three

different configurations:

Direct mapping, in which each block is mapped to exactly one cache location.

Conceptually, this is like rows in a table with three columns: the data block or cache line

that contains the actual data fetched and stored, a tag that contains all or part of the

address of the fetched data, and a flag bit that connotes the presence of a valid bit of data

in the row entry.

Fully associative mapping is similar to direct mapping in structure, but allows a block to

be mapped to any cache location rather than to a pre-specified cache location (as is the

case with direct mapping).

Set associative mapping can be viewed as a compromise between direct mapping and

fully associative mapping in which each block is mapped to a subset of cache locations. It

is sometimes called N-way set associative mapping, which provides for a location in main

memory to be cached to any of "N" locations in the L1 cache.

Specialized caches

In addition to instruction and data caches, there are other caches designed to provide

specialized functions in a system. By some definitions, the L3 cache is a specialized cache

because of its shared design. Other definitions separate instruction caching from data caching,

referring to each as a specialized cache.

8. Write an assembly language program to covert the binary number into hexadecimal

number.

MODEL SMALL

.STACK 1000h

.DATA

HEX_Map DB '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'

HEX_Out DB "00", 13, 10, '$' ; string with line feed and '$'-terminator

.CODE

main PROC

mov ax, @DATA ; Initialize DS

mov ds, ax

; Example No. 1 with output

mov di, OFFSET HEX_Out ; First argument: pointer

mov ax, 10101100b ; Second argument: Integer

call IntegerToHexFromMap ; Call with arguments

mov ah, 09h ; Int 21h / 09h: Write string to STDOUT

mov dx, OFFSET HEX_Out ; Pointer to '$'-terminated string

int 21h ; Call MS-DOS

; Example No. 2 with output

mov di, OFFSET HEX_Out ; First argument: pointer

mov ax, 10101100b ; Second argument: Integer

call IntegerToHexCalculated ; Call with arguments

mov ah, 09h ; Int 21h / 09h: Write string to STDOUT

mov dx, OFFSET HEX_Out ; Pointer to '$'-terminated string

int 21h ; Call MS-DOS

mov ax, 4C00h ; Int 21h / 4Ch: Terminate program (Exit code = 00h)

int 21h ; Call MS-DOS

main ENDP

IntegerToHexFromMap PROC

mov si, OFFSET Hex_Map ; Pointer to hex-character table

mov bx, ax ; BX = argument AX

and bx, 00FFh ; Clear BH (just to be on the safe side)

shr bx, 4 ; Isolate high nibble (i.e. 4 bits)

mov dl, [si+bx] ; Read hex-character from the table

mov [di+0], dl ; Store character at the first place in the output string

mov bx, ax ; BX = argument AX (just to be on the safe side)

and bx, 00FFh ; Clear BH (just to be on the safe side)

and bl, 0Fh ; Isolate low nibble (i.e. 4 bits)

mov dl, [si+bx] ; Read hex-character from the table

mov [di+1], dl ; Store character at the second place in the output string

ret

IntegerToHexFromMap ENDP

IntegerToHexCalculated PROC

mov si, OFFSET Hex_Map ; Pointer to hex-character table

mov bx, ax ; BX = argument AX

shr bl, 4 ; Isolate high nibble (i.e. 4 bits)

cmp bl, 10 ; Hex 'A'-'F'?

jl .1 ; No: skip next line

add bl, 7 ; Yes: adjust number for ASCII conversion

.1:

add bl, 30h ; Convert to ASCII character

mov [di+0], bl ; Store character at the first place in the output string

mov bx, ax ; BX = argument AX (just to be on the safe side)

and bl, 0Fh ; Isolate low nibble (i.e. 4 bits)

cmp bl, 10 ; Hex 'A'-'F'?

jl .2 ; No: skip next line

add bl, 7 ; Yes: adjust number for ASCII conversion

.2:

add bl, 30h ; Convert to ASCII character

mov [di+1], bl ; Store character at the second place in the output string

ret

IntegerToHexCalculated ENDP

END main ; End of assembly with entry-procedure

9. Write an assembly language program to convert binary number to decimal number.

section .data

prompt1 db 0dh, 0ah, 0dh, 0ah, "Please input a signed base-10 integer: $"

prompt2 db 0dh, 0ah, "Your number in binary is: $"

prompt3 db 0dh, 0ah, "Pretty sure that wasn't a number. Please enter a number value. $"

prompt4 db 0dh, 0ah, "Your number in octal is: $"

section .text

START:

mov ah, 9 ;Display input prompt

mov dx, prompt1

int 21h

mov bx, 0 ;Get input

mov ah, 1

int 21h

DEC_IN:

cmp al, 0dh ;compare input to carriage return; check if user is finished

je DEC_OUT ;if yes, go display the prompt

cmp al, '0' ;compare to '0'

jg IS_DIGIT ;jump to IS_DIGIT to confirm that it is a number

jl NAN_ERROR ;if below 0, print error prompt and start over

IS_DIGIT:

cmp al, '9' ;confirms digit value

jl BIN_CONV ;if digit, convert to binary

jg NAN_ERROR ;if not, print 'not a number' error message

10. Write an assembly language program to multiply the two unsigned binary numbers.

MODEL SMALL

.STACK 100

.DATA ; Data Segment to initialize the variables

A DW 0FF87H ; First signed number A = (-79H) = FF87H (2'Compliment form)

B DW 0FF84H ; Second signed number B = (-7CH) = FF84H (2'Compliment form)

C DW ? ; Variable C to store result

.CODE

START:

MOV AX,@DATA

MOV DS,AX ; Initialize data segment

MOV SI,0000H ; Initialize SI to 0000H

MOV AX,A ;Take first number A in AX register

MOV CX,B ;Take second number B in CX register

MUL CX ; Performs unsigned Multiplication DX:AX = AX × CX

MOV C[SI],DX ; Store higher 16-bit result

MOV C[SI+2],AX ; Store lower 16-bit result

INT 03H

END START

Input:

FF87 × FF84 = FF0B 3A9C H

A = 0FF87 H (2'compliment of -79H)

B = 0FF84 H (2'compliment of -7CH)

Output:

C = FF0B 3A9C H