GOLD down the drain

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GOLD down the drain Uli Schäfer 1 What’s left after Heidelberg

description

GOLD down the drain. What’s left after Heidelberg. Strawman design HD-meeting. 14-slot ATCA crate with custom backplane Up to 3 instances of topological processor: 2 dual-quadrant boards 1 merger. Backplane traffic @ 640 Mb/s LVDS signalling Up to 600 lanes on a chip - PowerPoint PPT Presentation

Transcript of GOLD down the drain

Page 1: GOLD down the drain

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GOLD down the drain

Uli Schäfer

What’s left after Heidelberg

Page 2: GOLD down the drain

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Strawman design HD-meeting

• 14-slot ATCA crate with custom backplane

• Up to 3 instances of topological processor: • 2 dual-quadrant boards• 1 merger

Uli Schäfer

TP TCM

TP QM

TP QM

TP GM

TP ROD

TP QM

TP QM

TP GM

TP ROD

TP QM

TP QM

TP GM

TP ROD

TP ROD

TP QM

TP GM

TP QM

195 195

195

3 4 readout links

• Backplane traffic @ 640 Mb/s• LVDS signalling• Up to 600 lanes on a chip• Up to 200 lanes on standard

ATCA backplane double that at the expense of rear transition module non-ATCA

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Topo processor modules

Uli Schäfer

Z1

Z2

Z3

FPGA

O/E

O/E

O/E

O/E

O/E

O/E

O/E

Z1

Z2

Z3

FPGA

O/E

O/E

O/E

O/E

O/E

O/E

O/E

FPGA

TTCrx

CTL

Z1

Z2

Z3

FPGA

TTCrx

CTL

• Quadrant processor stage consisting of 2 FPGAs (??) Covering one quadrant each

• 7*12*6.4 Gb/s from cluster/jet/muon processors

• Would require 42 xGb links per processor (??)

• Merger stage is single FPGA

• Operating on 640Mb/s links

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Strawman design

How does it fit MZ processor design (GOLD) ? not at all

• Restricted choice of algorithms due to limited bandwidth from quadrant processors to merger

• Opto transceivers will have to go onto front panel, that’s a pain in the *** maintenance-wise

• Try and adopt the unavoidable

• Design for a sandwich of two feeder modules and one processor

• Avoid the most horrible• Do high speed links (6.4 and 10.4) Gb/s rather than 640

Mb/s to avoid bottlenecks• Keep space in zone 3 for opto links

• Adapt GOLD accordinglyUli Schäfer

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GOLD 2.0• ATCA form factor (8U x 280 mm)

• Standard Zone1 connectivity (2*-48V supply scheme)• Zone2 xGb/s inputs from adjacent feeder modules• Zone3 (RTMs) xGb/s optical links

• 4 processors XC6VLX240T/550T-FFG1759 : 24/36 * GTX link (6.5Gb/s)

• 4 processors XC6VHX380T/XC6VHX565T : 48*GTX, 24* GTH (10Gb/s) – available ~ Oct. ’10 (?) engineering samples

• Supply 2 processors with input data via backplane• Supply 6 processors from daughter module• Might have to mix standard SNAP12 (up to 6.4 Gb/s only?) and

Avago transceivers• Merger ???• Optical inputs from backplane via bare fibre ribbons• Electrical link fan-out (*2) with CML buffers (SY58011)• 1*SNAP12 out from control/merger FPGA or from processors ?• Everything else stays as planned• Build daughter module and backplane resident feeder module

Uli Schäfer

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Gold floor plan

Uli Schäfer

• ATCA

• daughter modulew. 4*FMC connector

• 8 processors

• SFP / SNAP12 out

• Merger / control ??

• SystemACE config

• Local routing

Z1

Z2

Z3

Opto

?

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Test daughter

Uli Schäfer

• Half size module

• 3* SNAP12 receive

• 36 * fanout (*2, CML)

• 2 FMC connectors

• 3 * SNAP12 transmit

• SNAP12 control CPLD


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