Goal of this lecture
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Transcript of Goal of this lecture
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© Digital Integrated Circuits2nd Devices
Goal of this lectureGoal of this lecture
Present understanding of device operation nMOS/pMOS as switches How to design complex gates using
nMOS/pMOS transistors
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What is a Transistor?What is a Transistor?
VGS VT
RonS D
A Switch!
|VGS|
An MOS Transistor
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The MOS TransistorThe MOS Transistor
Polysilicon Aluminum
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CMOS devicesCMOS devices
Drain
Gate
Source
p-substrate
p+ n+ n+
LW
Substratecontact
Drain Source
n-well
p+ n+
n-wellcontact
p+
GateAl SiO2
Polysilicon
NMOS PMOS
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The NMOSThe NMOS Substrate: lightly doped (p-) Source and drain: heavily doped (n+) Gate: polysilicon Thin oxide separates the gate and the “channel” Field oxide and field implant isolate the devices
Source
Gate
p-substrate
Polysilicon
n+n+
Drain
p+ field implant
Field oxide(SiO2)
NMOS Transistor
Gate oxide
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MOS Transistors -MOS Transistors -Types and SymbolsTypes and Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS withBulk Contact
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Threshold Voltage: ConceptThreshold Voltage: Concept
n+n+
p-substrate
DSG
B
VGS
+
-
Depletion
Region
n-channel
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Transistor in LinearTransistor in Linear
n+n+
p-substrate
D
SG
B
VGS
xL
V(x) +–
VDS
ID
MOS transistor and its bias conditions
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Transistor in SaturationTransistor in Saturation
n+n+
S
G
VGS
D
VDS > VGS - VT
VGS - VT+-
Pinch-off
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Summary of MOSFET Operating Summary of MOSFET Operating RegionsRegions
Strong Inversion VGS > VT
Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS VDSAT
Weak Inversion (Sub-Threshold) VGS VT
Exponential in VGS with linear VDS dependence
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MOSFET equationsMOSFET equations Cut-off region
Linear region
Saturation
Oxide capacitance/Gain Factor
Ids Vgs VT 0 0 for
Ids CoxW
LVgs VT Vds
Vds Vds Vds Vgs VT
2
21 0 for
IdsCox W
LVgs VT Vds Vds Vgs VT
2
21 for
Coxox
tox
F / m2 W/L
oxtox
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MobilityMobility
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IIDD versus V versus VGSGS
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VGS (V)
I D (
A)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VGS (V)
I D (
A)
quadratic
quadratic
linear
Long Channel Short Channel
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MOS output characteristicsMOS output characteristics
Linear region: Vds<Vgs-VT
Voltage controlled resistor
Saturation region: Vds>Vgs-VT
Voltage controlled current source
Curves deviate from the ideal current source behavior due to: Channel modulation
effects
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Static CMOS CircuitStatic CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
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Static Complementary CMOSStatic Complementary CMOSVDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks…
…
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NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X Y
A
B Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
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Threshold DropsThreshold DropsVDD
VDD 0PDN
0 VDD
CL
CL
PUN
VDD
0 VDD - VTn
CL
VDD
VDD
VDD |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
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Complementary CMOS Logic StyleComplementary CMOS Logic Style
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Example Gate: NANDExample Gate: NAND
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Example Gate: NORExample Gate: NOR
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© Digital Integrated Circuits2nd Devices
Complex CMOS GateComplex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
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© Digital Integrated Circuits2nd Devices
Constructing a Complex GateConstructing a Complex Gate
C
(a) pull-down network
SN1 SN4
SN2
SN3D
FF
A
DB
C
D
F
A
B
C
(b) Deriving the pull-up networkhierarchically by identifyingsub-nets
D
A
A
B
C
VDD VDD
B
(c) complete gate
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© Digital Integrated Circuits2nd Devices
Cell DesignCell Design
Standard Cells General purpose logic Can be synthesized Same height, varying width
Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width
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Standard CellsStandard Cells
Cell boundary
N Well
Cell height 12 metal tracksMetal track is approx. 3 + 3Pitch = repetitive distance between objects
Cell height is “12 pitch”
2
Rails ~10
InOut
VDD
GND
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© Digital Integrated Circuits2nd Devices
Standard CellsStandard Cells
InOut
VDD
GND
In Out
VDD
GND
With silicided diffusion
With minimaldiffusionrouting
OutIn
VDD
M2
M1
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Standard CellsStandard Cells
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A