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Transcript of Gnu Make
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GNU Make
1-Mar-12Enabling the ARM Learning in INDIA
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Most of the project requires the source code to bedistributed among many files. Modifications in anyone file necessitates compiling all the files. This willbe tedious and time consuming operation.
Objective
The make utility in Unix OS automates such tasks ofgenerating the object modules and the executables.The make compiles only those source codes that aremodified and links with other object modules.
This session gives an insight into make utility.Participants will look into the constituents of makefile.After this session, participants can automate theircompiling requirements using the make utility.
1-Mar-12Enabling the ARM Learning in INDIA
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GNU Make Course outline
writing make rules using macros/variables
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g /
taking advantage of implicit rules using shell inside make files dealing with sources spread across directories
Enabling the ARM Learning in INDIA
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A utility that determines dependencies in creation of targets
Builds files that are out of date
Not specific to any language
About make
Not specific to any language
Traditionally been used on UNIX platform
Various ports exist GNU - GNU make
Microsoft - nmake
1-Mar-12Enabling the ARM Learning in INDIA
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$ gcc -c foo1.c$ gcc -c foo2.c
Building an application manual way
foo
$ gcc -o foo foo1.ofoo2.o
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foo1.h foo2.hfoo1.c foo2.c
foo1.o foo2.o
Enabling the ARM Learning in INDIA
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$ cat makefile
f f 1 f 2
Simple make file
foo
foo: foo1.o foo2.ogcc -o foo foo1.o foo2.o
foo2.o: foo2.c foo2.h foo1.hgcc -c foo2.c
foo1.o: foo1.c foo1.hgcc -c foo1.c
foo1.h foo2.hfoo1.c foo2.c
foo1.o foo2.o
Enabling the ARM Learning in INDIA
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$ make
reads and processes makefile in the current
directory
How to run make
directory,
$ make [-f mymake] [target]
reads and processes mymake in the current
directory,
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Alternate WaysNormal compilation of asample application$ gcc -o sample sample.c
What if we had includedsample.h in sample.c ?
Revised makefile
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Doing it with make$ make
Contents of makefilesample : sample.c
gcc -o sample sample.c
Revised makefile
sample : sample.c sample.h
gcc -o sample sample.c
Is the following valid as well?
sample : sample.h sample.c
gcc -o sample sample.cEnabling the ARM Learning in INDIA
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Commentssample make to illustrate how to use comments
# rule to generate foo2.o object file
foo2.o : foo2.c foo2.h foo1.h
gcc -c foo2.c # compile-onlygcc c foo2.c # compile only
using # not as comment indicator
HASH = \#
BACKSLASH =\\
run:
echo HASH is $(HASH)echo BACKSLASH is $(BACKSLASH)
Enabling the ARM Learning in INDIA
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Rules Variables Directives
Constituents of a make file
Inclusion of another make Conditional directives
Comments Text that follows # symbol is treated as
comment To include # literally, prefix with \
1-Mar-12Enabling the ARM Learning in INDIA
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Syntax
target1 [target2] : [prerequisite1] [prerequisite2 ]command-1command-2
...
C t
Rules
Components
Targets
File names
Action names
Dependencies/ prerequisites
Commands
Compilation / linking
Any other command
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sample : sample.c
gcc -o sample sample.c
target
rule
dependency
command
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Explicit rule explicitly specify the prerequisites for a specific
Rules
target
Implicit rules Take advantage of the knowledge make has about
known patterns of files (e.g., .c, .cpp .o, .s )
Further classified into pattern rules & suffix rules
Enabling the ARM Learning in INDIA
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Two-phase processing Phase-1
Read include files, if any
Processing of make file
Read include files, if any
Expand variables and functions
Process conditional directives
Construct dependency graph
Phase-2 Determine which targets to be rebuild
Invoke necessary rules
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Immediate expansion Expansion that happens during the first phase
Deferredi h d h d i h fi h
Processing of make file
Expansion that does not happen during the first phase
targets : dependencies
actions (or commands)
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immediateimmediate
deferred
Enabling the ARM Learning in INDIA
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target1 :echo processing rule 1
t t2
Multiple rules in a make file
$ make target3
echo processing rule 3
processing rule 3target2 :echo processing rule 2
target3 :echo processing rule 3
processing rule 3
$ make target1 target3
echo processing rule 1
processing rule 1
echo processing rule 3
processing rule 3
Enabling the ARM Learning in INDIA
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Prefix Action
- ignore command errors,if any
Prefixes to commandsTARGET1 = $(SRC_DIR)
SRC_DIR = proj/src
TARGET4 := $(SRC_DIR)
show:if any
@ dont echo the commandto
standard output
+ execute the command even ifn option is selected
show:
+@echo this message is always
show
@echo TARGET1 is $(TARGET1)
-rm *.o
rm *.o
-rm *.o
Enabling the ARM Learning in INDIA
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Some commonly used variables predefined by GNU makeCC, FLAGS , CFLAGS, LDFLAGS
Predefined Variables
foo foo1 o foo2 o CC = gccfoo: foo1.o foo2.o
gcc -o $@ $^
foo2.o: foo2.c foo2.h foo1.h
gcc -c $