GLAST LAT Project 4.1.7

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GLAST Large Area Telescope:GLAST Large Area Telescope:

Electronics, Data Acquisition & Flight Software W.B.S 4.1.7

Monthly Status 11-02-04

Gunther Hallerhaller@slac.stanford.edu(650) 926-4257

Gamma-ray Large Gamma-ray Large Area Space Area Space TelescopeTelescope

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Test-Stand Summary Test-Stand Summary

• Finished TKR test-stands• ACD was already finished• Produced and shipped 3 more CAL FM TEM/TPS including conformal

coating/stacking• Tested 3 more TEM/TPS sets for CAL, in conformal coating, to be

shipped in about 2 weeks

Client Shipped Assemble/Test TotalCalorimeter (conformal) 11 3 TEM 14

Calorimeter 5 0 5Tracker (conformal) 2 0 2

Tracker 9 0 9ACD 4 0 4

I & T* (next slide) 5 0 5DAQ/FSW 12 0 12

Electronics Support 11 0 11Total 59 3 62

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Test-Stand Maintenance Test-Stand Maintenance

• TKR Returns– None

• ACD Returns– None

• CAL Returns– One TEM, FPGA failure during muon testing at NRL, replaced

FPGA

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ACD TeststandACD Teststand

• Last months issue: Issue with high-rate testing -> CPU crashes -> GASU needs to be power-cycled

• Mitigation provided last month:– DAQ/I&T sent ACD instruction on how to reset GASU after CPU

crash so that GASU does not need to be power-cycled. – ACD was to either

• Change code to process all events off-line (transmit from CPU to PC instead of process them in the CPU), or

• Change code to process only fraction of events real-time in CPU (prescaling)

– Testing could also continue by• First look at rate-counters to confirm that rates are not high• If rates are low, one can take data, if rates are high, there is a

problem anyways• Final Mitigation (DAQ/I&T team sent to GSFC today to install)

• 4 each LCB’s with updated FPGA code • New revision I&T release (back-ward compatible, transparent)

• This will fix crashes, but in order to do high rate processing, ACD code still needed to change code as described above (see ACD)

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ASICASIC

• All GTCC1, GCCC1 TEM ASIC’s screened– Qualification testing at GSFC is starting– SLAC personnel will help Thursday to get station up

running at GSFC• GLTC ASIC’s (for GASU)

– Thermal cycled GLTC’s– Screening hardware debugged, working– Test software in progress

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ACTELACTEL

• Returned all MEC fab-line FPGA’s to ACTEL with exception of already programmed (e.g. for qual, Twr A, Twr B)

• Scheduled to receive UMC fab-line ACTELs tomorrow at SLAC• 3 sets will be programmed at SLAC by ACTEL (will bring their

programming adapter)• Then 3 sets will go to lead-forming (1-2 weeks)• Decision was to be made: rework 3 assembled TEM’s or put

MEC’s on them, but see TEM production issues…

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TEM/TPS ProductionTEM/TPS Production

• Delays at General Dynamics (technical & priority)– Issue with Nusil under ASICs: ASIC lifted up in reflow oven, issue with air

pockets• Experiments did not succeed• SLAC analyzed temperature increase for flight by not applying Nusil

under ASIC– 3 degrees T difference– SLAC changed work-order to not apply Nusil under ASIC

– Issue with Nusil under ACTEL• Required for thermal reasons• Tests to solder with hot-air rework station failed, did not get to reflow

temp– After 10 days found out that station was defective

• Now fixed and works• Assembly in reflow oven was reported to work too since ACTELs are

bigger and heavier than ASICs (used samples of ACTELs)– Latest (yesterday): GT reports that pins on all ACTEL’s are bent and can’t

be used. ACTEL’s were received at GT 6 weeks ago. Being investigated how this can happen. ACTEL’s are being sent back to SLAC.

– Investigate whether pins can be straightened, or– Wait til UMC line is available (2 weeks)

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TEM/TPS Schedule Qual, TWR-A, TWR-BTEM/TPS Schedule Qual, TWR-A, TWR-B

• Near term schedule supplied by GT (BEFORE THEY TOLD US YESTERDAY THAT FPGA’s CAN’T BE USED!)– TPS complete with SMT (done) 11/1– TEM complete with SMT (done) 11/2– TPS QA (in progress) 11/2– TEM QA11/3– MECH ASSY TEM and TPS HEATSINK, ATTACH VR5 11/4– TEM and TPS QA 11/5– TEM and TPS thru hole 11/8– TEM and TPS QA 11/9– TEM and TPS SPEA 11/11– TEM and TPS install cable assys, aqueous clean 11/15– TEM and TPS staking 11/16– TEM and TPS QA 11/17– TEM AND TPS AVAILABLE FOR SLAC PERSONNEL 11/18

• TC/Temp test/review 12/13• Mating of TEM/TSP, test, vibration, TC, ship to SLAC 12/31• TVAC, EMI, deliver to I&T01/17

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TEM/TPSTEM/TPS

• Tasks left to be completed– Delivery/review of detailed vibration/TC procedure from GT– Travel of 3 engineers to GT (2 days before boards are

available for testing)– EMI SOW released, received quote for EMI testing at

vendor, is going out for RFP next week.• Schedule risk mitigation efforts in process

– Daily telecon with vendor

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GASU & GASU-PS & PDUGASU & GASU-PS & PDU• Internal harness for GASU, PDU, SIU

– SOW’s and Drawings released– Requisition written– Will go to purchasing for RFP cycle

• PDU– Enclosure contract awarded, 6 week delivery– Flight PCB’s in fabrication, due 11/10/04

• Will assembly one board in-house and test– SOW for flight assembly just released– Requisition being entered in system – Issue: OMNIREL linear-regulator. Recalled lot which was received by SLAC. (Tantalum

cap used has end-termination with pure Sn as opposed to Sn/Pb. Can’t use in space.) New delivery in Feb 05.

– Preliminary detailed schedule shows PDU QUAL&FLT delivered to SLAC 3/15 and delivery to I&T 3/30

• GASU– Enclosure contract awarded, 8 week delivery– Flight electrical package just signed off– PCB fab requisition created– Assembly drawings in sign-off cycle– SOW for assembly approved– Requisition for assembly awaits approval of drawings– Issue: might have to add LVDS driver on PCB -> see EEPROM slide– Same schedule as PDU

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SIU & LAT HarnessSIU & LAT Harness

• SIU– Enclosure fab awarded, 8 week delivery – LCB, CPS, Back-plane electrical in sign-off– Requisition for flight PCB fab await sign-off of drawings– SIB board layout was changed (power-on reset mod due to occasional

EEPROM addr 0 corruption. Was changed on EM’s, is working• Assume that 28 mil finished minimum hole size for PCI connector is

accepted (32 drill plated to 28 mil). Larger holes up to 32 mil are also ok.

– SIB electrical will be submitted for sign-off after above is final– Parts: PCI ERNI Connector not approved yet (need screening

specifications)– Crate assembly drawings in sign-off– SOW for board, crate assembly to be written

• Question of sending RAD750 board to board assembly vendor and testing of entire crate at vendor, versus having boards done individually at vendor and assembly and test in crate at SLAC

• LAT Harness– Connectors were ordered and have been received at SLAC– Drawings in sign-off– SOW in sign-off– Requisition awaits sign-off of above items

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RAD750 EEPROM/PROMRAD750 EEPROM/PROM

• Issue: possible risk of page fault in EEPROM (is it?, not clear)• Last week: Authorized BAE to order PROM assembly tool (2 week

delivery)• Options:

– Replace EEPROM with PROM– No change: keep one boot image in EEPROM– Keep EEPROM but minimize (~4 kBytes) critical single-copy code

and have two images of bulk of code (~60kbytes each)• Detect/control via checksum

– About 4 weeks code development & test– Potential problem with failures due to large number of repeated

reads of EEPROM (is it problem?, not clear)– But then also (smaller) problem in current boots since loop (wait)

run out of EEPROM• Use PID’s via SC discretes in SIU and (to be added) discrete

from GASU for EPU• Easier coding, would require board change of GASU and some

cable mod• Another telecon Friday to discuss

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Schedule/BudgetSchedule/Budget

• Total budget: $22,055• Work Scheduled up to date: $20,509• Work Performed: $18,121• Actuals: $19,832• Schedule Variance $-2,388k (-11.6%)

– Qual/Flight work should have been started, reflects current status

• Cost Variance: $-1,710k (-8.3%)• Mainly EGSE, GASU, PDU are over budget