GigE Project

8/12/2019 GigE Project

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Project

A] Sobel Filter implementation in the FPGA Zynq.

1. Approach to design a sobel filter in fpga block with read/write operations from the DDR memory. [

2. Writing/Reading the captured data from camera to the DDR memory. [PS side on Linux

B] Sending data to Odroid Board


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Zynq PS and PL Some Brief detaiProcessor System

applicatio

I/O periph

multiplexe(Emio)

memory i

PS interco

Dma

timers

general in

on-chip m

debug con

The PS can Mast

- Using the G

PL Devices can ac

- Through the

1. GP_slave_A

2. HP_slave_AMemory map

The cortex-A9 processor uses 32-bit addressing

All the PS and PL peripherals are memory mappe


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A] 1. Hardware Design part (Hardware Driver part)

What is already done:

Xilinx provide AXI VDMA for video read/write

capabilities from AXI4 memory mappeddomain to AXI4stream

AXI_INTERCONNECT_GP0_MASTER

Using this The Cortex-A9

processor writes and reads

all AXI4-Lite slave registers in

the design for control and status

information.

AXI4-Lite

AXI4-Lite


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Sobel filter part

Zynq PS-PL

A. 1.


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Virtual memory

A. 2.


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Steps followed for building fpga (PL) side of p Open PlanAhead Software -> EDK Design

A.


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Hardware Design

Add Sobel filter Go to

http://www.wiki.xilinx.com/Zynq+Base+TRD+14.2Downloa

Zynq Bas

Go to

Hardware

In the Pc

Sobel filt

Folder in

Then it ca

EDK desig


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ADD Extra design drivers (Sobel filtand VDMA)


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Close the EDK Design tool and Expthe Hardware design to SDK


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Make a New Application Project: FSProject in SDK


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Now Steps to generate the DeviceTthe new Hardware design using SD

First The Device Tree Generator Git repository needs to be cfrom the Xilinx. Using the following command on linux.

Now the cloned BSP repository should be added to SDK.

SDK Menu: Xilinx Tools > Repositories > New... () > OK

git clone git://github.com/Xilinx/device-tree.git bsp/device-tree_v0_00_x


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In the Local Repositories, New->Add the BSrepository ->OK


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Create a Device Tree Board SupporPackage (BSP):SDK Menu: File > New > Board Support Package > Board Support Package OS: device-tree > Fini

A BSP tti i d ill


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A BSP settings window will appear.

Fill in the values as appropriate: The 'bootargs' parameter specifies the arguments passed to the kernel at boot time (kernel comma

The 'console device' parameter specifies which serial output device will be used. Select a value from

Generally Default options are preferred and works in most c

Click Ok -> This will create a devicetree (.dts format) at the location : ///libsrc/device-tree_v0_00_x/xilinx.dts.

N G t d D i t i i dt f


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Now Generated Devicetree is in .dts forIn order to be used it needs to be conveto .dtb format The Device Tree Compiler (DTC)is the toolchain for building device tre

files (*.dts) into the binary format (*.dtb).

The source code of the DTC should be cloned from a git repository ongit.kernel.org. This can be done using following command.

git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git


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Now the Device Tree compiler shouinstalled

sudo apt-get install device-tree-complier (Command to ins


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Now the dts file can be converted to the

Command: dtc -I dts -O dtb -o devicetree.dtb Xilinx.dts

It will generate a dtb formate devicetree.

er genera ng e ev ce ree


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er genera ng e ev ce ree. ,We need to make the BOOT.bin file SDK. Go to Xilinx tools -> Creat Zynq Boot Image

Select the location of output folder and create image This will create u-boot.bin, remane it as BOOT.bin


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The SD card Boot partition files

zImage (Kernel Image is downloaded from the Xilinx

site)

BOOT.bin and devicetree.dtb are made.

These three files should be put in the boot partitionof sd card.

After powering up Linux will automatically getsbooted on the zynq device.


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HDMI test run on hardware design


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After Linux installationA. 2.

GigE Project

Documents

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