Gheorghe M. Ştefan - 2014 -

25
Gheorghe M. Ştefan http://arh.pub.ro/gstefan/ - 2014 -

Transcript of Gheorghe M. Ştefan - 2014 -

Page 1: Gheorghe M. Ştefan  - 2014 -

Gheorghe M. Ştefan http://arh.pub.ro/gstefan/

- 2014 -

Page 2: Gheorghe M. Ştefan  - 2014 -

Tristate buffers enable = 0, out = hi-z

enable = 1, out = in’

Interconnecting two systems:

en1=1, en2=0 : System 1 sends, System 2 receives

en1=0, en2=1 : System 2 sends, System 1 receives

en1=0, en2=0 : System 1 receives, System 2 receives

en1=1, en2=1 : forbidden

2014 Digital Integrated Circuits - week three 2

Page 3: Gheorghe M. Ştefan  - 2014 -

Inverting & non-inverting tristate buffer

2014 Digital Integrated Circuits - week three 3

Page 4: Gheorghe M. Ştefan  - 2014 -

Transmission gate

en = 1 => out = in

en = 0 => out = hi-z

Main limitation: RON is serially connected to CL

Main advantage: no connection to VDD and ground

2014 Digital Integrated Circuits - week three 4

Page 5: Gheorghe M. Ştefan  - 2014 -

Elementary inverting multiplexor

Low power, small area, but low speed

2014 Digital Integrated Circuits - week three 5

Page 6: Gheorghe M. Ştefan  - 2014 -

Memory circuits

Data latches revisited

Delay flip-flop (DF-F)

Reset-able DF-F

2014 Digital Integrated Circuits - week three 6

Page 7: Gheorghe M. Ştefan  - 2014 -

Data latches

0 : active level of CK 1 : active level of CK

CK = 1 : loop closed CK = 1 : transparent CK = 0 : transparent CK = 0 : loop closed

2014 Digital Integrated Circuits - week three 7

Page 8: Gheorghe M. Ştefan  - 2014 -

The master-slave structure of DF-F

What is the active edge of clock?How can the active edge be changed?

2014 Digital Integrated Circuits - week three 8

Page 9: Gheorghe M. Ştefan  - 2014 -

master-latch is transparent, slave-latch latches

master-latch latches, slave-latch is transparent

the overall structure is anytime non-transparent

2014 Digital Integrated Circuits - week three 9

Page 10: Gheorghe M. Ştefan  - 2014 -

Reset-able DF-F

The free inverter is substituted by an appropriate gate

Both, master-latch and slave–latch must be “forced” asynchronously

2014 Digital Integrated Circuits - week three 10

Page 11: Gheorghe M. Ştefan  - 2014 -

Growing – Speeding - Featuring

Size vs. Complexity Time restrictions in digital systems

Growing the size by composition Speeding by pipelining Featuring by closing new loops The taxonomy of digital systems

2014 Digital Integrated Circuits - week four 11

Page 12: Gheorghe M. Ştefan  - 2014 -

Size vs. ComplexitySize: the dimension of physical resources –

Sdigital_system

Gate size: the number of CMOS pairsArea size: silicon areaDepth: number of logic levels

Complexity (algorithmic complexity): ~ the dimension of the shortest description Cdigital_system

Simple circuit: Csimple_system << Ssimple_system

Complex circuit: Ccomplex_system ~ Scomplex_system

2014 Digital Integrated Circuits - week four 12

Page 13: Gheorghe M. Ştefan  - 2014 -

Size vs. Complexity (examples)

2014 Digital Integrated Circuits - week four 13

Complex circuit:

Simple circuit:

Page 14: Gheorghe M. Ştefan  - 2014 -

Time restrictions in digital systems

2014 Digital Integrated Circuits - week four 14

tin_reg : minimum input arrival time before clocktreg_reg : minimum period of clock = Tclock_min = 1/fclock_max

tin_out : maximum combinational delay pathtreg_out : maximum required time after clock

Page 15: Gheorghe M. Ştefan  - 2014 -

Example

2014 Digital Integrated Circuits - week four 15

tin_reg = tp(adder) + tp (selector) + tsu(register) = (550+85+35)ps

treg_reg = Tclock_min = 1/fmax= tp(register) + tp(adder) + tp(selector) + tsu(register) = (150+550+85+35)ps fmax= 1.21 GHz

tin_out = tp(comparator) = 300ps

treg_out = tp(register) + tp(comparator) = (150+300)ps

Page 16: Gheorghe M. Ştefan  - 2014 -

Pipelined connections

2014 Digital Integrated Circuits - week four 16

Page 17: Gheorghe M. Ştefan  - 2014 -

Blocking – Non-Blocking assignment

2014 Digital Integrated Circuits - week four 17

Blocking assignment: “=“ for combinational circuitsNon-blocking assignment: “<=“ for edge triggered transitions

Page 18: Gheorghe M. Ştefan  - 2014 -

Fully buffered connection

2014 Digital Integrated Circuits - week four 18

tin_reg = tsu(regsiter)

treg_reg = tp(regsiter) + tp(comb) + tsu(regsiter) = 1/fclock_max

tin_out : not defined

treg_out = tp(regsiter)

Page 19: Gheorghe M. Ştefan  - 2014 -

Growing by composing

2014 Digital Integrated Circuits - week four 19

f(x) = g(h1(x), h2(x), … hm(x) )

Page 20: Gheorghe M. Ştefan  - 2014 -

Serial & Parallel Composition

2014 Digital Integrated Circuits - week four 20

Page 21: Gheorghe M. Ştefan  - 2014 -

Example: inner product

2014 Digital Integrated Circuits - week four 21

Page 22: Gheorghe M. Ştefan  - 2014 -

Example: inner product (cont.)

2014 Digital Integrated Circuits - week four 22

Page 23: Gheorghe M. Ştefan  - 2014 -

Speeding by pipeliningWith no pipeline:fclock = 1/(treg+tf+tsu) =

1/(treg+th_1+tg+tsu)

Latency: λ = 2

With pipeline:fclock =

1/(treg+ max(th_1+tg)+tsu)

Latency: λ = 3

2014 Digital Integrated Circuits - week four 23

Page 24: Gheorghe M. Ştefan  - 2014 -

Example: pipelined inner product

2014 Digital Integrated Circuits - week four 24

tp(mult) = 2 nstp(add) = 1nstsu(reg) = 20pstp(reg) = 50ps

No pipeline:fck = 0.325 GHz

With pipeline:fck = 0.483 GHz

Page 25: Gheorghe M. Ştefan  - 2014 -

Home work 3 Problem 1: design at the gate level an asynchronously reset-

able (RST) and preset-able (SET) DF-F.

Problem 2: design a synchronously reset-able DF-F.

Problem 3: design the test module for the pipelined version of the inner product circuit represented in Figure 3.6 and described in Example 3.7. Use it to simulate the inner product circuit.

2014 Digital Integrated Circuits - week three 25