GGT-Electronics System design

GGT-Electronics System design

Alexander Kluge Alexander Kluge CERN-PH/EDCERN-PH/ED

April 3 , 2006

April 3, 2006 A. Kluge

General: Chip SpecificationsChip Parameter

Specification

Preliminary Design parameter

Time resolution

160/200 ps 160/200 ps (bin size?)

Beam size(a x b)

48 x 36 mm2 48 x 36 mm2

Pixel size(a x b)

300 x 300 µm2

300 x 300 µm2

Matrix size(a x b)

32 x ?

Active area/per chip(a x b)

9.6 x ? mm2

# chip/module(a x b)

5 x 2 / 5 x 3 / 4 x 3

Calculation,simulationWorking parameters


General: Chip Specifications

Chip Parameter

First ideas Specification Preliminary Design parameter

Avg Rate: avg/max

60/173 MHz/cm2 Depends on TDC, segmentation

Efficiency 99%98% for center??

Number of pixels/segment

1 (analog TDC)7-20 (digital TDC)

Dead time of segment

100 ns for 1 TDC/pixel

7 -10 ns for shared TDC

Buffer size per segment

Readout speed/Trans-mission speed

Needs to operate in vacuum

Yes/no ??


inputs output

I/O block diagram of chip


I/O of chip• Which connections to on-detector electronics?

– 2 Power supplies per chip: • Core supply; analog and digital (1.5V / 1.3A / 2W)• I/O supply (≤ 2.5V / ~0.1A)• Several wire pads (~30) but all to few conductors outside

– Outputs (5 Gbits/s)• Data: ≥ 2 high speed serial outputs (differential 3 Gbit/s)

• Status: 1 low speed serial output pair• (6 pads)

– Inputs• Clock input: 1 differential pair• Configuration & control: 1 low speed serial output pair• 2 single ended control • 8 config • (6 + 8 pads)


clk 2

2control

data0 2

2data1

status 2

10testconfig8

control2

5VddCoreAna

5GndCoreAna 5 GndIO

5VddCoreDig5VddIO

5GndCoreDig

2

2

2

1 1 1

1

2

2

2

I/O block diagram of chip


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Configuration


Chip size

Readout and supply

21 mm18 mm

3 mm• Readout needs possibly more space ->not leaving 18mm active area

• Supply from one side has strong power drop

• Thinning of long narrow chips more difficult

Readout and supply


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Configuration

• Highest rate


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Configuration

Max rate on one chip, but chip smaller


Configuration: study starting point


Components in beam of 48 x 36 mm

Si; 48 x 12 mm2; 200 µm

Si; 9.6 x (12+6) mm2; 100 µm

Carbon; 48 x 36 mm2; 100 µm

48 x 9 mm2;Al; 50 µmKapton; 50 µm + 12 µmAl; 10 µm * 50%Al bonds; 2mm; 25 µmSMD comp 0402 (glued or wire bonded); 1 x 0,5 x 0.5 mm3


9 mm

Low mass cable


Configuration

• Center: 0.45% X0

• Off Center1: 0.55% X0

• Off Center2: 0.65% X0

• Border: 0.65% X0

• Sensor&bonds: 0.24% X0

• RO chip: 0.11% X0

• Low mass cable: 0.10% X0

• Structure: 0.10% X0

6 mm: 0.48%3 mm: 0.58%3 mm: 0.69%

3 mm: 0.58%3 mm: 0.69%9 mm: 0.69%

9 mm: 0.69%


Configuration: study starting point


• Signal lines 100µm width200µm pitch + separation =>~ 0.7 mm per signal line

• Vdd lines 1mm & separation =>~1.2 mm

• Per chip and side:3 Vdd + 3 signal =>5.7 mm

9 mm


Configuration• Sensor&bonds: 0.24% X0

• RO chip: 0.11% X0

• Low mass cable: 0.10% X0

• Structure: 0.10% X0


Conclusion: configuration• What is the required material budget?

• Is the starting point configuration acceptable and if not what are the reasons?– Use reasons to adapt other parameters accordingly - geometric efficiency (areas of complete inefficiency),electronics efficiency, beam geometry


Number of components needed

• 3 stations each consisting of:• 1 module & mechanics & cooling• 1 modules consists of:• 3 assemblies

9 assemblies needed for GGT

• 100 days of operation:– Life time of assembly : 14 to 28 days =>

• 4 to 7 exchange cycles• 36 to 63 assemblies needed

– in this scheme 4 low mass cables are needed for 1 module => in total 48 to 84 low mass cables needed


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Configuration 3 x 5• Assume matrix of 40 rows x 32 columns:

– 12 mm x 9.6 mm = 115.2 mm2

• Chip size– (12 + (2 x 3mm)) x 9.6 mm = 18 x 9.6 mm

• Pixel size 300 um x 300 um – => 40 x 32 pixels = 1280 pixels

• Max. Avg Rate of column in center chip: ~150 MHz/cm2

(for beam with max. 173 MHZ/cm2)– => 135 kHz/pixel– => 173 MHz/chip– => 173 MHz/chip * ~32 bit = 5.5 Gbit/s


Configuration 3 x 4• Assume matrix of 40 rows x 40 columns:

– 12 mm x 12 mm = 144 mm2

• Chip size– (12 + (2 x 3mm)) x 12 mm = 18 x 12 mm

• Pixel size 300 um x 300 um – => 40 x 40 pixels = 1600 pixels

• Max. Avg Rate of center chip: ~150 MHz/cm2

(for beam with max. 173 MHZ/cm2)– => 135 kHz/pixel– => 216 MHz/chip– => 216 MHz/chip * ~32 bit = 6.9 Gbit/s


Rate and super pixels• Super pixel structure for rate maximum in center

Column of 40 pixels

• 12 mm column centered on beam~150 MHz/cm2 => 135 kHz/pixel => 99%,

• Td = 10ns, N=7, Nseg = 183;• Td = 6 ns, N= 12, Nseg = 107;• Td = 7.4 ns, N= 10, Nseg = 128;

Readout and supply

Readout and supply


Rate and super pixels• Super pixel structure for rate maximum in center

Column of 40 pixels

• 12 mm column centered on beam~150 MHz/cm2 => 135 kHz/pixel => 98%,

• Td = 10ns, N=14, Nseg = 91;• Td = 6 ns, N= 24, Nseg = 53;• Td = 7.4 ns, N= 20, Nseg = 64;

Readout and supply

Readout and supply


Read out

• 3 planes x 3 x 5 chips x (2 high speed + 2 low speed + 1 clock) optical links = 90 high speed links +90 low speed links+ 45 clock links


ALICE pixel trigger processor

BRAINHS0

HS1

HS11

HS108

HS109

HS119

12 x 800 MHzJTAG

parallel bus

DDLEthernet

Multi Gigabitserial link

DAQ data linkcontrol &

datato computer(control room)

CTP

clkSPD RO

TTC

Multi Gigabit serial link

JTAGparallel bus

OPTIN9

FPGA config

Multi Gigabit serial link

JTAG

Control serial link

parallel bus

OPTIN0

FPGA config

Control serial link

Parallel data bus

Parallel data bus TTC


Conclusion• Configuration specification have influence on chip and system design

• Full information and choice of options only during design of full chip

GGT-Electronics System design

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