GET – Front End · GET – Front End:AsAd Technical Specification Reference: - User Requirements...

GET – Front End: AsAd Technical Specification

User Requirements Document Issue: 1 Revision: 0

Reference: - Created: October 2009 Last modified: -

Prepared By: Jérôme PIBERNAT in collaboration with: Jean-Louis Pedroza Abdelkader Rebii Patrick Hellmuth Arnaud Tizon Cedric Huss

GET – Front End:AsAd Technical Specification Reference: - User Requirements Document Revision: 0 Issue: 1 Last modified: -

This document has been prepared using the CERN PSS-05 Templates. The CERN PSS-05 Templates have been prepared by the Information and Programming Technology Group, ECP Division, CERN (The European Laboratory for Particle Physics) and conform to the PSS-05 Software Engineering Standards (ISBN 0-13-106568-8) defined by ESA (European Space Agency) BSSC (Board for Software Standardization and Control).

page ii


Abstract

This document describes a first level of specification for AsAd (ASIC-ADC board) which constitutes the GET-system front-end. The document is divided into three parts, the first part describes each AsAd functional blocks, the second part describes the AsAd interfaces, the third part relates to AsAd in its physical context. The purpose of the document is to provide the most complete, accurate, and up-to-date list of specifications for the system being designed.

Document Status Sheet

Table 1 Document Status Sheet

1. Document Title: AsAd technical specification - System and User Requirements Document

2. Document Reference Number: -

3. Issue 4. Revision 5. Date 6. Reason for change

1 0 October 2009 Creation

page iii


Document Change Record

Table 2 Document Change Record

Document Change Record DCR No.

Date

Originator

Approved By

1. Document Title

2. Document Reference Number [Document Reference Number]

3. Document Issue / Revision Number [Document Issue]/[Document Revision Number]

4. Page 5. Paragraph 6. Reason for Change

page iv


Table of Contents

Abstract............................................................................................................... iii Document Status Sheet ..................................................................................... iii Document Change Record ................................................................................ iv

Table of Contents ................................................................................................v

List of Figures....................................................................................................vii List of Tables ...................................................................................................... ix

1 Introduction .................................................................................................1 1.1 Purpose of the document ..............................................................................................1 1.2 Scope of the system......................................................................................................1 1.3 Acronyms and abbreviations ........................................................................................3 1.4 References ....................................................................................................................3

2 PART ONE: AsAd Functional Blocks ........................................................4 2.1 ASIC for GET...............................................................................................................4 2.2 Switched Capacitors Array Management for AGET....................................................5

2.2.1 Cycle Controller ...............................................................................................5 2.2.2 Local Clocks Manager .....................................................................................6

2.3 Serial Control for AGET ..............................................................................................8 2.4 Test & Calibration for AGET.....................................................................................10 2.5 Analogue to Digital Conversion.................................................................................12 2.6 Power Supply .............................................................................................................14 2.7 Monitoring..................................................................................................................15 2.8 Slow Control...............................................................................................................17

2.8.1 AsAd Slow Control Manager data-flow handling overview..........................17 2.8.2 General description of the data flow ..............................................................18

2.9 Inputs Management ....................................................................................................20 2.10 Inspections Management ...........................................................................................21 2.11 Identification .............................................................................................................22

3 PART TWO: AsAd Interfaces ...................................................................23 3.1 AsAd-CoBo Interface.................................................................................................23 3.2 AsAd-GET Power Unit Interface ...............................................................................25 3.3 AsAd-External Instruments Interface .........................................................................25

page v


3.4 AsAd-ZAP Interface...................................................................................................26 3.5 AsAd-JTAG Interface.................................................................................................26

4 PART THREE: AsAd in its physical context ...........................................27 4.1 AsAd board size .........................................................................................................27 4.2 AsAd Module (EMC and cooling aspects).................................................................29

Appendix A: AsAd functional diagram ............................................................32

page vi


List of Figures

Figure 1: GET Synoptic ......................................................................................................1

Figure 2: AsAd highest level functional diagram ................................................................2

Figure 3: AGET into AsAd context .....................................................................................4

Figure 4: Cycle Controller architecture...............................................................................6

Figure 5: Local Clocks Manager architecture and interconnections ..................................7

Figure 6: Serial Controller architecture and interconnections ............................................9

Figure 7: AGET Test & Calibration block architecture and interconnections ...................11

Figure 8: Analogue to Digital Conversion outputs format (ADS6422 datasheet extraction)12

Figure 9: AD conversion architecture and interconnections.............................................13

Figure 10: Power Supply architecture and interconnections............................................14

Figure 11: Monitoring architecture and interconnections .................................................16

Figure 12: Inputs Manager architecture and interconnections .........................................21

Figure 13: Inspection Manager architecture and interconnections ..................................22

Figure 14: AsAd-CoBo interconnection............................................................................23

Figure 15: AsAd connection side .....................................................................................23

Figure 16: AsAd-CoBo buffering scheme.........................................................................24

Figure 17: AsAd presence from a CoBo point of view......................................................24

Figure 18: AsAd-GET Power Supply Unit Interconnection...............................................25

Figure 19: AsAd-External Instruments Interface ..............................................................26

Figure 20: AGET/AsAd-ZAP Interface relative placement ...............................................27

Figure 21: AsAd minimal edge length ..............................................................................27

Figure 22: AsAd size and component locations ...............................................................28

Figure 23: Shielding shape ..............................................................................................30

page vii


Figure 24: AsAd module cooling profile ...........................................................................30

page viii


List of Tables

Table 1 Document Status Sheet ....................................................................................... iii

Table 2 Document Change Record................................................................................... iv

Table 3: AGET working cycles ...........................................................................................5

Table 4: Cycle Controller I/O names, standards and directions.........................................5

Table 5: Local Clocks Manager I/O names, standards and directions...............................7

Table 6: Serial Controller I/O names, standards and directions.........................................9

Table 7: Calibration ranges available...............................................................................10

Table 8: AGET Test & Calibration block I/O names and properties .................................11

Table 9: AD conversion I/O names and properties ..........................................................13

Table 10: Power Supply I/O names and properties..........................................................15

Table 11: Monitoring I/O names and properties...............................................................17

Table 12: Core device (ADT7519) I/O names and properties ..........................................17

Table 13: Slow Control preamble content ........................................................................19

Table 14: Body content format by writing a data into an ADC register.............................19

Table 15: Body content format by reading or writing into a DAC register ........................19

Table 16: Body content format by writing into an AMD register .......................................19

Table 17: Body content format by reading from an AMD register ....................................20

Table 18: Body content format by reading or writing into the LC1 or LC2 registers.........20

Table 19: Inputs Manager output names, standards and direction ..................................20

Table 20: Inspection Manager I/O names, standards and direction.................................22

Table 21: Identification format..........................................................................................22

Table 22: AsAd-CoBo interconnection details..................................................................23

Table 23: AsAd components sizes and maximal dissipated power .................................29

page ix


1 Introduction

1.1 Purpose of the document

The purpose of this document is to define the most complete and accurate set of constraints and requirements to drive the design of AsAd starting from a functional point of view to reach a structural approach of this GET subsystem.

1.2 Scope of the system

AsAd (Asic-Adc) is the part of GET (General Electronics for TPCs) that processes the analogue TPC's outgoing signals in order to make their informative contents digitally processable by the others GET subsystems represented on figure 1.

MUTANT

TPC AsAd

BEM

CoBo

PC

Disk

InBoZAP

MUTANTMUTANT

TPCTPC AsAd

BEMBEM

CoBoCoBo

PC

Disk

InBo

PCPC

DiskDisk

InBoInBoZAP

Figure 1: GET Synoptic

The system being discussed in this document is presented as a functional diagram in the figure 2. It consists of:

• Eleven functional blocks o Two main blocks:

An ASIC for GET block (blue) ( TPC's analogue signals processing) An Analog to Digital Conversion block (indigo)

( Digital conversion of the analogue processing result)

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o Three AGET-dedicated secondary blocks: A Switched Capacitors Array Management block (light green)

( Real time signal processing management) A Serial Control block (green)

( Delayed time signal processing control) A Test and Calibration Management block (cyan)

( Analogue processing result and digital conversion checks) o Six AsAd-dedicated secondary blocks:

A Power Supply block (brown) ( AsAd's local power sources and sources management) A Monitoring block (red)

( AsAd's operating environment check) A Slow Control Management block (orange)

( AsAd's own resources control) An Input Management block (purple)

( AsAd's inputs configuration) An Inspection Management block (grey)

( AsAd's operations check) An Identification block (black)

( AsAd's location in the whole GET system)

• Five interfaces

o Four user interfaces: The AsAd-CoBo Interface The AsAd-Power Supply Unit Interface The AsAd-External Instruments Interface The AsAd-ZAP Interface

o One expert interface: The AsAd-JTAG Interface

AsAd functional diagram (highest level)

POWER SUPPLY

MONITORING

SLOW CONTROL MAN.

SCA MAN.

SERIAL CONTROL

TEST & CAL MAN.

AGET

ADC

INPUT MAN.

INSPECTION MAN.

IDENTIFICATION

CoBo Interface(user)

External Instruments Interface(user)

ZAP Interface(user)

Power Supply Unit Interface(user)

JTAG Interface(expert)

Arrows indicate related blocks

AsAd functional diagram (highest level)

POWER SUPPLY

MONITORING

SLOW CONTROL MAN.

SCA MAN.

SERIAL CONTROL

TEST & CAL MAN.

AGET

ADC

INPUT MAN.

INSPECTION MAN.

IDENTIFICATION

CoBo Interface(user)

External Instruments Interface(user)

ZAP Interface(user)

Power Supply Unit Interface(user)

JTAG Interface(expert)

Arrows indicate related blocks

Figure 2: AsAd highest level functional diagram

page 2


All functional blocks are described in the first part of the document whereas the second part concerns the interfaces details. The third part gives an overview of AsAd as a physical GET module located into its operating context.

1.3 Acronyms and abbreviations

CENBG Centre d'Etudes Nucléaires de Bordeaux-Gradignan

GET General Electronics for TPC's

TPC Time Projection Chamber

AsAd ASIC-ADC board or module (the system introduced in this document)

ASIC Application Specific Integrated Circuit

AGET ASIC for GET

SCA Switched Capacitors Array (an AGET subsystem)

ADC Analog to Digital Conversion or Converter

I/O Inputs/Outputs

CoBo Concentration Board

1.4 References

External documents referenced in this document can directly be accessed by following the hypertext link inserted into the text

page 3


2 PART ONE: AsAd Functional Blocks

2.1 ASIC for GET

AGET is basically a configurable Application Specific Integrated Circuit able to process simultaneously 64 random analogue signals by amplifying, filtering and sampling them, as well as discriminating them by comparing their magnitude to a user-defined threshold level. The analogue samples are stored into a Switched Capacitor Array (SCA) and the number of coincident discriminated input signals has to be concurrently monitored in order to trigger the sampling process stop (Multiplicity detection). Once this process interrupted, the stored samples have to be sequentially extracted from the SCA in order to convert their analogue values into digital data. Further details on AGET features and processes can be found here AsAd is able to host up to four AGETs and to provide them with: - their required power supply and bias voltages (c.f. Power Supply section) - their required means to be tested and calibrated (c.f. Test & Calibration Management) AsAd receives from CoBo the parameters allowing AGET operations under any circumstance and is responsible to allocate them correctly. (c.f. Switch Capacitors Array management and Serial Control sections) AsAd implements devices allowing the digital conversion of the multiplicity and the analogue samples stored into the SCA. It is also able to transfer the converted data to CoBo (c.f. Analogue to Digital Conversion section). Figure 3 shows AGET as the AsAd main block with its interconnections to the others AsAd blocks.

VO -

AGET

InCalInTst

VO+

WCK+WCK -RCK+RCK -Read

Write

SC_DoutSC_CkSC_En

SC_SDin

64 inputs

Analog to Digital ConversionTest & Cal Management

Serial Control

SCA Management

Power SupplyVdd & Biases

AsAd-ZAP Interface

AGET block into AsAd context

AGET

VO -

InCalInTst

VO+


Write

SC_DoutSC_CkSC_En

SC_SDin

64 inputs

Analog to Digital ConversionTest & Cal Management

Serial Control

SCA Management

Power SupplyVdd & Biases

AsAd-ZAP Interface

AGET block into AsAd context

Figure 3: AGET into AsAd context

page 4

http://groups.nscl.msu.edu/tpc/wiki/doku.php?id=electronics


2.2 Switched Capacitors Array Management for AGET

This block is divided into two sub-blocks: - The Cycle Controller which is basically responsible to transmit the sampling and readout commands

coming from CoBo to AGET. - The Local Clocks Manager which is in charge of spreading towards AGET the clocks required to make it

work properly under any circumstances.

2.2.1 Cycle Controller

This FPGA-implemented controller receives through the AsAd-CoBo Interface the SCW and SCR signals which respectively represent the sampling and the readout command. From these signals, the cycle controller is able to:

• generate the "write" and "read" commands sent to AGET • define an AGET working state

The cycles are defined as follows:

• A high to low transition on SCR when SCW is low defines the general AGET configuration cycle, which stops on a SCW low to high transition.

• A low to high transition on SCW when SCR is low defines the AGET sampling cycle, which stops on a SCW high to low transition.

• A high to low transition on SCW when SCR is low defines the specific AGET "channel-addresses" configuration cycle, which stops on a SCR low to high transition.

• A low to high transition on SCR when SCW is low defines an AGET readout cycle, which stops on a SCR high to low transition.

Mode<0-1> gives the AGET working state in each cycle (table 3)

Cycle SCR SCW Mode <1> Mode <0> General config. 0 0 0 Sampling 0 0 1 Channel-addresses config. 0 1 0 Readout 0 1 1

Table 3: AGET working cycles

Figure 4 shows the Cycle Controller foreseen architecture, its I/O names and standards are summarized in table 4

Name Standard voltages Direction SCW LVTTL/LVCMOS 3.3V (17mA input) CoBo Cycle Ctrl SCR LVTTL/LVCMOS 3.3V (17mA input) CoBo Cycle Ctrl write LVTTL/LVCMOS 3.3V Cycle Ctrl AGET read LVTTL/LVCMOS 3.3V Cycle Ctrl AGET Mode<0-1> FPGA standard logic Cycle Ctrl logic blocks

Table 4: Cycle Controller I/O names, standards and directions

page 5


State Machine

SCR

SCW

Mode<0>

Mode<1>

AGET 2

ReadWrite

AGET 3

ReadWrite

AGET 1

ReadWrite

AGET 0

ReadWrite AsAd-CoBo Interface

50Ω

50Ω

100

100

vdd1

vdd1

100

100

To other logic blocks

INSP. MAN.

Cycle Controller block

ReadWrite

State Machine

SCR

SCW

Mode<0>

Mode<1>

AGET 2

ReadWrite

AGET 3

ReadWrite

AGET 1

ReadWrite

AGET 0

ReadWrite AsAd-CoBo Interface

50Ω

50Ω

vdd1

100

100

vdd1

100

100

vdd1

100

100

To other logic blocks

INSP. MAN.

Cycle Controller block

ReadWrite

Figure 4: Cycle Controller architecture

2.2.2 Local Clocks Manager

This FPGA-implemented manager receives through the AsAd-CoBo Interface the CKW, CKR and CKP signals which respectively represent the sampling process clock, the readout process clock and the AGET serial transfer process clock. CKW is a frequency adjustable clock (4MHz to 100MHz) which is continuously sent by CoBo. CKR is a 25MHz frequency clock which is continuously sent by CoBo. CKP is only active for data transferring through AGET serial port. Depending on AGET working cycle its frequency is 25MHz (for AGET general configuration mode) or 50MHz (for the specific AGET "channel-addresses" configuration mode) In order to align the sampling clocks phases between several AsAd, the Local Clocks Manager passes CKW through a PLL and allows delaying it by slow control over a 6ns range by step of 200 ps. The resulting signal WCK is applied to AGET during a sampling cycle (Mode = 01) The Local Clocks Manager passes CKR through a PLL and generates two signals: - RCK which is the 25MHz clock used to extract from AGET the multiplicity (Mode = 01) or to extract the analogue samples from the SCA (Mode = 11) - ACK which is the free running clock used in the analogue to digital conversion. ACK is a 180° phase-shifted image of RCK that can be delayed by slow control over a 6ns range by step of 200ps. The inspection manager can be provided with WCK, RCK, ACK images at its inputs.

page 6


The Local Clocks Manager receives CKP when a serial transfer is initiated by CoBo (Mode = x0) it makes a level conversion on it and applies the converted signal SC_Ck, to the Serial Control block (see Serial Control section) Figure 5 shows the Local Clocks Manager foreseen architecture, its I/O names and standards are summarized in table 5

Name Standard voltages Direction CKW LVDS CoBo Local Clocks Manager CKR LVDS CoBo Local Clocks Manager CKP LVDS CoBo Local Clocks Manager Mode<0-1> FPGA standard logic Cycle Ctrl Local Clocks Manager WCK LVDS Local Clocks Manager AGET RCK LVDS Local Clocks Manager AGET ACK LVDS Local Clocks Manager ADC SC_Ck FPGA standard logic Local Clocks Manager Serial Controller

Table 5: Local Clocks Manager I/O names, standards and directions

Cycle Controller

CKW-

CKW+

AsAd

-CoB

oIn

terfa

ce

50Ω

50Ω100Ω

CKR-

CKR+

100Ω

CKP-

CKP+

100Ω

50Ω

50Ω

50Ω

50Ω

AG

ET 0 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

τ1

AG

ET 1 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

AG

ET 2 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

AG

ET3 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

τ2

AD

C

WCK-WCK+

100Ω

Ser.

Ctr

l

SC_Ck-

Slow

. Ctr

l. M

an.

PLL core 1, τ1 setting regSPI_Ck-

SPI_MOSI

SPI_MISO

SPI_CS5

En

InOut

LOCAL CLOCKS MANAGER

Mod

e<0>

Mod

e<1>

PLL core 1

PLL core 2

Out

En

In

PLL core 2, τ2 setting reg

SPI_CS6

Inspection Manager

WC

K

RC

K

AC

K

Cycle Controller

CKW-

CKW+

AsAd

-CoB

oIn

terfa

ce

50Ω

50Ω100Ω

CKR-

CKR+

100Ω

CKR-

CKR+

100Ω

CKP-

CKP+

100Ω

CKP-

CKP+

100Ω

50Ω

50Ω

50Ω

50Ω

AG

ET 0 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

AG

ET 0 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

τ1

AG

ET 1 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

AG

ET 1 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

AG

ET 2 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

AG

ET 2 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

AG

ET3 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

AG

ET3 WCK-

WCK+

100Ω

100Ω

RCK-RCK+

τ2

AD

C

WCK-WCK+

100Ω

AD

C

WCK-WCK+

100Ω

Ser.

Ctr

l

SC_Ck-

Slow

. Ctr

l. M

an.

PLL core 1, τ1 setting regSPI_Ck-

SPI_MOSI

SPI_MISO

SPI_CS5

En

InOut

LOCAL CLOCKS MANAGER

Mod

e<0>

Mod

e<1>

PLL core 1

PLL core 2

Out

En

In

PLL core 2, τ2 setting reg

SPI_CS6

Inspection Manager

WC

K

RC

K

AC

K

Figure 5: Local Clocks Manager architecture and interconnections

page 7


2.3 Serial Control for AGET

This FPGA-implemented controller block receives through the AsAd-CoBo Interface the CAx signals, and drives the AxC signals which represent in any AGET configuration mode, the data flow AGETx /CoBo (As there is 4 AGET per AsAd this block is replicated 4 times, and then x value can be 0, 1, 2 or 3). From an AsAd-CoBo point of view, this transfer is synchronous with CKP (c. f. Local Clocks Manager section), it is then defined as a 3-wire, full-duplex serial transfer. Depending on the AGET working mode the transfer sequences are defined as follows:

• When AGET is operated in general configuration mode (Mode = 00, c.f. Cycle Controller section):

A 16-bit preamble is sent from CoBo to AsAd through the CAx link, synchronously with the CKP signal (data present on the CKP rising edge to be latched on the CKP falling edge). This preamble is stored into one Serial Controller register. Its Most Significant Byte defines the size in bit of the body message that will follow. Its Least Significant Byte is used by the serial controller to:

o Activate the SC_Enx signal which must be applied to AGETx during the body-message transfer.

o Enable or inhibit SC_Ck (the CKP image coming from the Local Clocks Manager) during the body transfer. When enabled SC_Ck becomes SC_Ckx which is applied to AGETx

The 16-bit preamble is followed by a variable-sized body message which is formatted as expected to access any AGET configuration register:

o The first byte sent though CAx link is composed of one bit to set a read or write operation, followed by seven bits which define the address of the targeted AGETx register. The serial controller transfers this byte to AGETx through SC_Dinx.

o The following bits represent the register data. In case of a write operation, the serial controller receives the data from CoBo

through the CAx link and drives it to AGETx through SC_Dinx. In case of a read operation, the serial controller receives the data from AGETx

through the SC_Doutx link and drives it to CoBo through the AxC link. The body message is followed by an 8-bit postamble which represents the 2's complement of the sum of "ones" transferred between AsAd and CoBo in any direction.

• When AGET is operated in the specific "address configuration" mode (Mode = 10, c.f. Cycle Controller section) :

The same 16-bit preamble previously defined is sent from CoBo to AsAd to be equally processed by the serial controller The 16-bit preamble is followed by a variable-sized body message (most often 69-bit) which is formatted as expected to access the specific AGET "address configuration" register:

o the first bit sent though CAx set a read or write operation of the "address configuration" register. The serial controller transfers this bit to AGETx through the SC_Dinx link.

o the following bits represent the register data (addresses configuration) In case of a write operation, the serial controller receives the data from CoBo

through the CAx link and drives it to AGETx through the SC_Dinx link. In case of a read operation, the serial controller receives the data from AGETx

through the SC_Doutx link and drives it to CoBo through the AxC link. No postamble is used in this mode.

page 8


Figure 6 shows the Serial Controller foreseen architecture, its I/O names and standards are summarized in table 6 Name Standard voltages Direction CAx LVDS CoBo Serial Controller AxC LVDS Serial Controller CoBo SC_Ck FPGA standard logic Local Clocks Manager Serial Controller Mode<0-1> FPGA standard logic Cycle Controller Serial Controller SC_Dinx LVTTL/LVCMOS 3.3V Serial Controller AGETx SC_Doutx LVTTL/LVCMOS 3.3V AGETx Serial Controller SC_Enx LVTTL/LVCMOS 3.3V Serial Controller AGETx SC_Ckx LVTTL/LVCMOS 3.3V Serial Controller AGETx

Table 6: Serial Controller I/O names, standards and directions

R7

8-bit Shift Reg

RST D7

CAx+

Mux

0

R0

16-bit Shift Reg

RST D0

R0<7-0>R0<15-8>

Mux

1

R8

8-bit Shift Reg

RST Q8

R8<7-0>A0

8-bit adder

En

(1) dec. SC_Ck

Mux

0M

ux1

AxC+

C0

8-bit Counterin

C0*<7-0>

C1

8-bit Counter

C2

8-bit Comparator

A2

8-bit adder

En

(24) dec

(24)dec

(17)dec

(16)dec

C1<7-0>

D2 1

C3

8-bit Comparator

C4

8-bit Comparator

C5

8-bit Comparator

C6

8-bit Comparator

R2

1-bit Reg

R3

1-bit Reg1D3

Q2

Q3

R1

1-bit RegQ1

D1 SC_DinMode<0>Mode<1>

R4

1-bit Reg

1

D4Q4

Mux0R0<7-0>

Dem

0D

em1

Dem0

Read

Mux0R5

1-bit RegQ5 D5

1

SC_Ckx

SC_Enx

SC_Doutx

SC_Dinx

En

Mux1R6

1-bit RegQ6 1

RST

Dem1

Mux1

RST

Mux1

Mux1

RST

RST

RST

RST

RST

RST

50Ω

50Ω100Ω

50Ω

50Ω

AsAd

-CoB

oIn

terfa

ce

CAx-

AxC-

AG

ETxSC_Doutx

SC_Dinx

SC_EnxSC_Ckx

Cyc

le C

ontr

olle

r

Loca

l Clo

cks

Man

ager

SERIAL CONTROLLER

A1

8-bit adder(16) dec

R0<15-8>

Dem0

R7

8-bit Shift Reg

RST D7

CAx+

Mux

0

R0

16-bit Shift Reg

RST D0

R0<7-0>R0<15-8>

Mux

1

R8

8-bit Shift Reg

RST Q8

R8<7-0>A0

8-bit adder

En

(1) dec. SC_Ck

Mux

0M

ux1

AxC+

C0

8-bit Counterin

C0*<7-0>

C1

8-bit Counter

C2

8-bit Comparator

A2

8-bit adder

En

(24) dec

(24)dec

(17)dec

(16)dec

C1<7-0>

D2 1

C3

8-bit Comparator

C4

8-bit Comparator

C5

8-bit Comparator

C6

8-bit Comparator

R2

1-bit Reg

R3

1-bit Reg1D3

Q2

Q3

R1

1-bit RegQ1

D1 SC_DinMode<0>Mode<1>

R4

1-bit Reg

1

D4Q4

Mux0R0<7-0>

Dem

0D

em1

Dem0

Read

Mux0R5

1-bit RegQ5 D5

1

SC_Ckx

SC_Enx

SC_Doutx

SC_Dinx

En

Mux1R6

1-bit RegQ6 1

RST

Dem1

Mux1

RST

Mux1

Mux1

RST

RST

RST

RST

RST

RST

50Ω

50Ω100Ω

50Ω

50Ω

AsAd

-CoB

oIn

terfa

ce

CAx-

AxC-

AG

ETxSC_Doutx

SC_Dinx

SC_EnxSC_Ckx

Cyc

le C

ontr

olle

r

Loca

l Clo

cks

Man

ager

SERIAL CONTROLLER

A1

8-bit adder(16) dec

R0<15-8>

Dem0

Figure 6: Serial Controller architecture and interconnections

page 9


2.4 Test & Calibration for AGET

AGET is able to perform: • A functional test of each of its channels by means of a channel-dedicated internal capacitor • A global test of its channels by means of channels-group-dedicated internal capacitors • A calibration of its channels by means of channels-group-dedicated external capacitors

For each of these three operating modes, AsAd provides a pulse generator which output voltage swing generates across the selected capacitors, the charge injected at the channels inputs. This generator is made of a 14-bit current-mode DAC (AD9707) followed by a transimpedance amplifier. The procedure used in each mode is fully set by slow control (c.f. slow control management section). Assuming the DAC settings have already been made by slow control, a 24-bit word has to be sent to the FPGA test & calibration manager (c.f. figure 4-1) The 24-bit word is formatted as follows:

• If high, the most significant bit indicates a calibration procedure. If low, a test mode procedure or a functional mode procedure is selected. In any case, the most significant bit value must be chosen according to the AGET settings previously defined.

• The following bit value defines the charge range in which the calibration will be made, when a calibration procedure has been selected. A high value corresponds to the highest charge ranges achievable, whereas a low value corresponds to lower ranges.

• The 14 following bits values define the pulse generator output voltage magnitude • The further bit value indicates the way of triggering the pulse generator. A high value corresponds to

an external triggering mode (c.f. Inspection Manager section) whereas a low value indicates an internal triggering mode, which is defined by the 6 least significant bit values.

• For internal triggering mode, the 6 least significant bits correspond to the delay introduced between the instant of the 24-bit word reception and the instant of the DAC triggering by the CKO signal. The minimal delay must not be lower than 40ns. Assuming this minimal delay equal to 40ns, the six bits enable to delay the DAC trigger output from 40ns to (40+6x) ns by step of x ns.

From a hardware point of view, the two most significant bits enable to select the position of the analogue switches (TS3A44159) involved in the generator output voltage handling. If a calibration procedure has been chosen, up to four charge ranges can be used by first selecting a 1pF±1% or a 10pF±1% external capacitor and then by limiting the pulse generator output voltage swing. Table 7 defines the four calibration ranges available.

Charge range Voltage eq. range DAC current eq. range

qmax (pC) Vmax (mV) Imax (µA) ±0.12 ±120 ±60 1pF ±0.24 ±240 ±120

±1 ±100 ±50 10pF ±10 ±1000 ±500

Table 7: Calibration ranges available

The 1mA full scale output current DAC is defined by a 1.225V ±0.1% external voltage source reference (AD1580) ; as stated in figure 7, the output current DAC is voltage converted by a transimpedance amplifier made of an AD8062. Table 8 summarizes the Test & Calibration block I/O names and properties. AsAd Name Properties Interconnections

SPI_CK LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Test & Cal SPI_MOSI LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Test & Cal SPI_MISO LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Test & Cal SPI_CS1* LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Test & Cal SPI_CS2 LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Test & Cal

page 10

http://www.analog.com/static/imported-files/data_sheets/AD9704_9705_9706_9707.pdf

http://focus.ti.com/lit/ds/symlink/ts3a44159.pdf

http://www.avx.com/docs/catalogs/uq.pdf

http://www.analog.com/static/imported-files/data_sheets/AD1580.pdf

http://www.analog.com/static/imported-files/data_sheets/AD8061_8062_8063.pdf


CKO LVTTL/LVCMOS 3.3V (active on a low to high transition)

Inspection Man. Test & Cal Test & Cal Inspection Man.

Vdd 3.3V DC (Block Supply) Slow Ctrl. Man. Test & Cal InTest0 Analogue voltage (±1V dynamics) Test & Cal AGET0 InCal0 Analogue current Test & Cal AGET0 InTest1 Analogue voltage (±1V dynamics) Test & Cal AGET1 InCal1 Analogue current Test & Cal AGET1 InTest2 Analogue voltage (±1V dynamics) Test & Cal AGET2 InCal2 Analogue current Test & Cal AGET2 InTest3 Analogue voltage (±1V dynamics) Test & Cal AGET3 InCal3 Analogue current Test & Cal AGET3

Table 8: AGET Test & Calibration block I/O names and properties

10pF1pF 10pF1pF10pF1pF 10pF1pF

TS3A

4415

9

In_C

al

In_T

est

AGET0

TS3A

4415

9

In_C

al

In_T

est

AGET1

TS3A

4415

9

In_C

al

In_T

est

AGET2

TS3A

4415

9

In_C

al

In_T

est

AGET3

2kΩ

2kΩ

-+

+ -AD

8062

AD

8062

1.1kΩ

127Ω

AD

1580

1kΩ

Vdd

1.1V

1.225V

±0.1%

±15ppm/°

0Ω0Ω

AD9707

(DAC)

IAIBOTC

M

REF

IO

FSADJ

34.8

kΩCSB*

SPI

SCLKSDIO

DB

00D

B01

DB0

2D

B03

DB

04D

B05

DB0

6D

B07

DB

08D

B09

DB1

0D

B11

DB

12D

B13

CLK+CLK-

DCOMACOM

CLKCOM

AVDDDVDDCLKVDD

1.1V

2.1V

0.1V

delay24-bit

Din DoutEn

FPGA Test & Calibration Manager

AGET Test & Calibration Management

Insp.Man.

Pwr SupplyVdd

CAL

RANGECKO

CKO

3ns

Slw. Ctrl.Man.

SPI_CS1*SPI_CK

SPI_CS2SPI_MISOSPI_MOSI

10pF1pF 10pF1pF10pF1pF 10pF1pF

TS3A

4415

9

In_C

al

In_T

est

AGET0

TS3A

4415

9

In_C

al

In_T

est

AGET1

TS3A

4415

9

In_C

al

In_T

est

AGET2

TS3A

4415

9

In_C

al

In_T

est

AGET3

2kΩ

2kΩ

-+

+ -AD

8062

AD

8062

1.1kΩ

127Ω

AD

1580

1kΩ

Vdd

1.1V

1.225V

±0.1%

±15ppm/°

0Ω0Ω

AD9707

(DAC)

IAIBOTC

M

REF

IO

FSADJ

34.8

kΩCSB*

SPI

SCLKSDIO

DB

00D

B01

DB0

2D

B03

DB

04D

B05

DB0

6D

B07

DB

08D

B09

DB1

0D

B11

DB

12D

B13

CLK+CLK-

DCOMACOM

CLKCOM

AVDDDVDDCLKVDD

1.1V

2.1V

0.1V

delay24-bit

Din DoutEn

FPGA Test & Calibration Manager

AGET Test & Calibration Management

Insp.Man.

Pwr SupplyVdd

CAL

RANGECKO

CKO

Slw. Ctrl.Man.

SPI_CS1*SPI_CK

SPI_CS2SPI_MISOSPI_MOSI

3ns

Figure 7: AGET Test & Calibration block architecture and interconnections

page 11


2.5 Analogue to Digital Conversion

This block receives from AGET output, either a signal representing the channels triggered sum during the sampling process (Mode = 01), either the analogue samples stored into the SCA during the readout process (Mode = 11). These analogue signals are converted into digital values at the 25MHz frequency given by ACK (c.f. Local Clocks Manager section). The block architecture consists of four 12-bit analogue to digital converters (each one relates to one AGET), one voltage reference and a PLL, all embedded into the chip ADS6422. The ADS6422 power supply inputs are all connected to the AsAd main Vdd (c.f. power supply section), the device settings can be adjusted by slow control (c.f. slow control management section) once grounded its parallel input (PDN, CFG<4-1>). The main default settings are: - All conversion channels enabled - Use of the internal voltage reference (1,5V input common mode voltage has to be then equal to AGET output common mode voltage) - 1V peak to peak input full scale range - Conversion processes initiated for all channels on ACK rising edges - LVDS output signals driven through 100Ω differential impedances - 2-wire, 1x frame clock, 12x serialisation with SDR bit clock, byte wise MSB-first mode outputs format (c.f. figure 8)

Figure 8: Analogue to Digital Conversion outputs format (ADS6422 datasheet extraction)

For each ADC, the 12-bit digital output data is transferred to CoBo in serial mode through two wires. Each wire enables to transfer a 6-bit data which can be unserializided into CoBo by using the ADC bit-clock (CKB) and the ADC frame clock (CKF) which is aligned with the 12-bit word boundary. These clocks signals are generated from ACK by the PLL embedded into the conversion device.

page 12

http://focus.ti.com/lit/ds/symlink/ads6422.pdf


Figure 9 shows the AD conversion block architecture; its I/O names and properties are summarized in table 9

AsAd Name ADS6422 IO Name Properties Direction Vdd AVDD, LVDD 3.3V supply voltage Power Man. ADC ACK+, ACK- CLKP, CLKM LVDS Loc. Clocks. Man. ADC VO0+, VO0- INA_P, INA_M Analogue differential AGET0 ADC VO1+, VO1- INB_P, INB_M Analogue differential AGET1 ADC VO2+, VO2- INC_P, INC_M Analogue differential AGET2 ADC VO3+, VO3- IND_P,IND_M Analogue differential AGET3 ADC

CAP 2nF to Ground SPI_CK* SCLK LVTTL/LVCMOS 3.3V Slow Ctrl. Man. ADC SPI_MOSI SDATA LVTTL/LVCMOS 3.3V Slow Ctrl. Man. ADC SPI_CS0* SEN* LVTTL/LVCMOS 3.3V Slow Ctrl. Man. ADC GND PDN 0V GND CFG<4-1> 0V VOCM VCM 1.5V (DC level) ADC all AGET (option) OA0+, OA0- DA0_P, DA0_M LVDS ADC CoBo Interface OA1+, OA1- DA1_P, DA1_M LVDS ADC CoBo Interface OB0+, OB0- DB0_P, DB0_M LVDS ADC CoBo Interface OB1+, OB1- DB1_P, DB1_M LVDS ADC CoBo Interface OC0+, OC0- DC0_P, DC0_M LVDS ADC CoBo Interface OC1+, OC1- DC1_P, DC1_M LVDS ADC CoBo Interface OD0+, OD0- DD0_P, DD0_M LVDS ADC CoBo Interface OD1+, OD1- DD1_P, DD1_M LVDS ADC CoBo Interface CKB+, CKB- DCLKP, DCLKM LVDS ADC CoBo Interface CKF+, CKF- FCLKP, FCLKM LVDS ADC CoBo Interface

Table 9: AD conversion I/O names and properties

LOC. CK. MAN

OA0-OA0+OA1-OA1+OB0-OB0+OB1-OB1+

CKB-CKB+CKF-CKF+

OC0-OC0+OC1-OC1+OD0-OD0+OD1-OD1+

IND_M

ADC A

ADC C

ADC D

ADS6422CLKM

CLKP

SE

N*

SLC

KS

CLK

IND_P

ADC B

INC_M

INC_P

INB_M

INB_P

INA_M

INA_P

ACK-ACK+

SLW. CTRL. MAN.

SPI_CK*SPI_MOSISPI_CS0*

150MHz

25MHz

AGET 0 VO0-VO0+

AGET 1 VO1-VO1+

AGET 2 VO2-VO2+

AGET 3 VO3-VO3+

AsA

d/C

oBo

Inte

rfac

e

PLL

PD

NC

FG<4

-1>

AV

DD

LVD

D

Power Supply

VDD GND

VCM

100nF

100nF

LOC. CK. MAN


CKB-CKB+CKF-CKF+


IND_M

ADC A

ADC C

ADC D

ADS6422CLKM

CLKP

SE

N*

SLC

KS

CLK

IND_P

ADC B

INC_M

INC_P

INB_M

INB_P

INA_M

INA_P

ACK-ACK+

SLW. CTRL. MAN.


150MHz

25MHz

AGET 0 VO0-VO0+

AGET 1 VO1-VO1+

AGET 2 VO2-VO2+

AGET 3 VO3-VO3+

AsA

d/C

oBo

Inte

rfac

e

PLL

PD

NC

FG<4

-1>

AV

DD

LVD

D

Power Supply

VDD GND

LOC. CK. MAN


CKB-CKB+CKF-CKF+


IND_M

ADC A

ADC C

ADC D

ADS6422CLKM

CLKP

SE

N*

SLC

KS

CLK

IND_P

ADC B

INC_M

INC_P

INB_M

INB_P

INA_M

INA_P

ACK-ACK+

SLW. CTRL. MAN.


150MHz

25MHz

AGET 0 VO0-VO0+

AGET 1 VO1-VO1+

AGET 2 VO2-VO2+

AGET 3 VO3-VO3+

AsA

d/C

oBo

Inte

rfac

e

PLL

PD

NC

FG<4

-1>

AV

DD

LVD

D

Power Supply

VDD GND

VCM

100nF

100nF

Figure 9: AD conversion architecture and interconnections

page 13


2.6 Power Supply

ASAD board uses the GET power supply unit to make its own power supply sources. Four voltage sources are available into AsAd: AsAd main voltage source, Vdd = 3.3V, which is used to supply all active devices excepting those involved in the monitoring process. AsAd secondary voltage source, Vdd1 = 3.3V, which is especially dedicated to supply the monitoring active devices. AsAd LVDS voltage source, Vdd2 = 2.5V, which is dedicated to supply all the LVDS buffers. AsAd FPGA voltage source, Vdd3=1.5V, which is dedicated to supply the AsAd FPGA core as well as the PLL cores. Each voltage source is obtained from an ultra low dropout (ULDO) voltage regulator in order to minimize the dissipated power. The TPS74401 ULDO is chosen not only because of its low dropout feature for high current supplies, but also because of its ability to be easily controlled (Enable input and Power Good output flag). As this regulator requires a 5V reference voltage, a LTC1516 DC/DC converter which is not sensitive to the AsAd magnetic field environment has been chosen to generate the reference. The AsAd Power Supply block also uses a Power Manager embedded into the AsAd FPGA that is able to deal with the regulators Enable and Power Good signals as well as the Alert signal coming from the monitoring core device (c.f. Monitoring section) Figure 10 shows the AsAd Power Supply architecture; its I/O names and properties are summarized in table 10

Monitoring

AL

TPS74401

(ULDO)

Vin

Vbias

En

Vout

Vpg

FB3.57

k1.

15k

10k

Vdd1=3.3V

TPS74401

(ULDO)

Vin

Vbias

En

Vout

Vpg

FB3.57

k1.

69k

10k

Vdd2=2.5V

TPS74401

(ULDO)

Vin

Vbias

En

Vout

Vpg

FB4.12

k4.

75k

10k

Vdd3=1.5V

0.8V dropout

1V dropout

LTC1516

(DC/DC conv)5V ref

Vdd1

TPS74401

(ULDO)

Vin

Vbias

En

Vout

Vpg

FB3.57

k1.

15k

10k

Vdd=3.3V

VoutVin

Shdn

0.2V dropout

≈ 0.4V dropout

PWD

V+

FPGA Power Manager

V+Vin

AsAd Power Supply

AL

PG1PG2PG3PDN

PWG

AC11245

Vin

GET

Pow

er S

uppl

yU

nit

Inte

rface

CoB

oIn

terfa

ce

50Ω

Vin

100

100

Vdd_En

Monitoring

AL

TPS74401

(ULDO)

Vin

Vbias

En

Vout

Vpg

FB3.57

k1.

15k

10k

Vdd1=3.3V

TPS74401

(ULDO)

Vin

Vbias

En

Vout

Vpg

FB3.57

k1.

69k

10k

Vdd2=2.5V

TPS74401

(ULDO)

Vin

Vbias

En

Vout

Vpg

FB4.12

k4.

75k

10k

Vdd3=1.5V

0.8V dropout

1V dropout

LTC1516

(DC/DC conv)5V ref

Vdd1

TPS74401

(ULDO)

Vin

Vbias

En

Vout

Vpg

FB3.57

k1.

15k

10k

Vdd=3.3V

VoutVin

Shdn

0.2V dropout

≈ 0.4V dropout

PWD

V+

FPGA Power Manager

V+Vin

GET

Pow

er S

uppl

yU

nit

Inte

rface

AL

PG1PG2PG3PDN

PWG

AsAd Power Supply

AC11245

Vin

CoB

oIn

terfa

ce

50Ω

Vin

100

100

Vin

100

100

Vdd_En

Figure 10: Power Supply architecture and interconnections

page 14

http://focus.ti.com/lit/ds/symlink/tps74401.pdf

http://cds.linear.com/docs/Datasheet/1516f.pdf


Name Standard voltages Direction V+ Global power supply voltage GET Pwr Unit AsAd Pwr Supply Vin 3.5V DC (main power supply input) Monitoring AsAd Pwr Supply PWD LVTTL/LVCMOS 3.3V (17mA input) CoBo AsAd Pwr Supply AL LVTTL/LVCMOS 3.3V Monitoring AsAd Pwr Supply PWG LVTTL/LVCMOS 3.3V AsAd Pwr Supply Insp. Man. Vdd 3.3V DC (main pwr. supply output) AsAd Pwr Supply AGET

AsAd Pwr Supply ADC AsAd Pwr Supply Test & Cal

Vdd1 3.3V DC (second. Pwr. supply output) AsAd Pwr Supply FPGA LVCMOS IO AsAd Pwr Supply Monitoring

Vdd2 2.5V DC (LVDS power supply) AsAd Pwr Supply LVDS buffers Vdd3 1.5V DC (core FPGA power supply) AsAd Pwr Supply FPGA core

Table 10: Power Supply I/O names and properties

Operation: Even when AsAd is connected to the GET power supply unit, AsAd devices are not supplied until PWD goes high (CoBo controls AsAd power up). If PWD is high, then Vdd1, Vdd2 and Vdd3 are enabled (FPGA IO and core as well as AsAd Monitoring are supplied). When each of all these voltage sources have reached 90% of their nominal value the PWG signal goes high (This signal level can be checked, c.f. Inspection Manager section) When PWG is high, AsAd main power source is enabled. The main power supply voltage and current are checked by the monitoring. If any limit stored into the Monitoring core device is exceeded, the alert signal (AL) goes high and the AsAd main power source is switched off. The failure can be found by reading the Monitoring status registers (Slow Control operation)

2.7 Monitoring

ASAD board is able to monitor the temperature at which it is operated, its main power supply voltage and current levels (Vdd, Idd). These measurements are obtained from sensors connected to one monitoring core device, the ADT7519. The settings of this device are adjusted by slow control (c.f. slow control management section). Once the ADT7519 has been supplied by the AsAd secondary power source Vdd1 (c.f. power supply section), it makes an auto-calibration during 5ms. It is then able to scan and convert into digital data, sequentially:

• its own power supply voltage (AsAd secondary power source voltage Vdd1) • its own operating temperature (Tint) • the temperature measured at AsAd hottest point (Text) • AsAd main power source current (Idd) • AsAd main power source voltage (Vdd)

For each item 16 measurements are made and their mean values are stored into 8-bit registers (in 2's complement format for the temperature measurement, in natural binary for all others measurements). The 1.4 kHz conversion frequency is supplied by internal means into the ADT7519. The register contents can be accessed at any time by slow control. The slow control enables as well to store into the ADT7519 the top and bottom limits not to exceed for each item. If any limit is exceeded the ADT7519 gives an alert signal which is used to:

• inform CoBo that a failure occurred • switch off AsAd main power source

page 15


The secondary power source, which is only used to supply the ADT7519 and the slow control manager, is still switched on allowing thus CoBo to find the point of failure. Figure 11 shows the monitoring block architecture.

T sense

2N3906

I sense

INA 122

111

mΩ

(PV

S1 se

rie)

V sense

2kΩ

1.3kΩ

AIN4

AIN3

AIN2

AIN1

ADT7519

INT INT AL

FPGA Al. Man.

Slw

. Ctr

l. M

an.

AsAd

Monitoring

AsA

d/C

oBo

Inte

rfac

e

SPI_MOSI

SPI_MISO

SPI_CK

SPI_CS3*CS*

SCLK

DIN

DOUT

PWR

UN

IT

Inte

rfac

e

Pow

erSu

pply

Vdd 1

Vdd 1

Vdd

V+

AL

AL

24mA buffer

Vin

820Ω

820Ω

820Ω

T sense

2N3906

I sense

INA 122

111

mΩ

(PV

S1 se

rie)

V sense

2kΩ

1.3kΩ

AIN4

AIN3

AIN2

AIN1

ADT7519

INT INT AL

FPGA Al. Man.

Slw

. Ctr

l. M

an.

AsAd

Monitoring

AsA

d/C

oBo

Inte

rfac

e

SPI_MOSI

SPI_MISO

SPI_CK

SPI_CS3*CS*

SCLK

DIN

DOUT

PWR

UN

IT

Inte

rfac

e

Pow

erSu

pply

AL

Vdd 1

Vdd

V+

Vdd 1

24mA buffer

VinAL

820Ω

820Ω

820Ω

Figure 11: Monitoring architecture and interconnections

This architecture is composed of : • One temperature sensor (Text measurement) made of a semi-conductor junction (2N3906 transistor) • One current sensor (Idd measurement) made of a PVS1 resistor and an INA122 differential amplifier • One voltage sensor (Vdd measurement) made of a voltage divider. • One core device, the ADT7519. • One Alert Manager FPGA block made of inverters-buffers. The aim of the alert manager is to disable

all the FPGA IO except those concerning the slow control transfers when an alert has been sent by the monitoring core device.

The monitoring I/O names and properties are summarized in table 11. The ADT7519 (monitoring core) connections are summarized in table 12. AsAd Name Block IO Name Properties Direction V+ I sense input GET power unit voltage Power Interface Monitoring Vin I sense output 3.5V DC voltage Monitoring Power Supply Vdd V sense input 3.3V DC voltage Power Supply Monitoring Vdd1 VDD 3.3V DC block supply Power Supply Monitoring AL AL LVTTL/LVCMOS 3.3V Monitoring CoBo Interface

Monitoring Power Supply

page 16

http://www.fairchildsemi.com/ds/2N%2F2N3906.pdf

http://www.precisionresistor.com/pvs1-1w-wire-wound-current-sensing-shunts-2-tab-surface-mounted-pr-50.html

http://focus.ti.com/lit/ds/symlink/ina122.pdf

http://www.analog.com/static/imported-files/data_sheets/ADT7516_7517_7519.pdf


SPI_CK SCLK LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Monitoring SPI_MOSI DIN LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Monitoring SPI_MISO DOUT LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Monitoring SPI_CS3* CS* LVTTL/LVCMOS 3.3V Slow Ctrl. Man. Monitoring

Table 11: Monitoring I/O names and properties

ADT7519 IO Name Properties Direction VDD 3.3V supply voltage Power Man. Vdd1 ADT7519 Vref-IN 3.3V voltage Power Man. Vdd1 ADT7519 AIN1, AIN2 Analogue inputs Tsense ADT7519 AIN3 Analogue input Isense ADT7519 AIN4 Analogue input Vsense ADT7519 INT LVTTL/LVCMOS 3.3V ADT7519 FPGA Alert Man SCLK LVTTL/LVCMOS 3.3V Slow Ctrl. Man. ADT7519 DIN LVTTL/LVCMOS 3.3V Slow Ctrl. Man. ADT7519 DOUT LVTTL/LVCMOS 3.3V Slow Ctrl. Man. ADT7519 CS LVTTL/LVCMOS 3.3V Slow Ctrl. Man. ADT7519

Table 12: Core device (ADT7519) I/O names and properties

2.8 Slow Control

The slow control is an AsAd-CoBo data transfer which enables CoBo to: • define the behaviour of all AsAd configurable devices (excepting AGET) by writing instructions into

their configuration registers • check the working state of these devices by reading into their status registers

The data transfer is defined as a full duplex synchronous serial transfer since: • the transfer from CoBo to AsAd is made by one link (CAS) • the transfer from AsAd to CoBo is made by one link (ACS) • CoBo always masters the 10MHz CKS clock that is only active during the data transfer process.

The data transfer protocol consists of one preamble followed by a body message, itself followed by a postamble.

2.8.1 AsAd Slow Control Manager data-flow handling overview

The AsAd slow control manager is an FPGA implemented device which is able to handle the data-flow between CoBo and any AsAd devices excepting AGET. From an AsAd/CoBo point of view, the slow control manager acts as follows:

• When CoBo wants to write a data into an AsAd register, it sends through CAS the data flow containing the preamble, the body message and the postamble. This data flow is received by the Slow Control Manager and is sent back to CoBo through ACS with an updated postamble (the postamble format will be described hereafter).

• When CoBo wants to read into an AsAd register, it sends through CAS the data flow containing the preamble, the body message and the postamble. This data flow is sent back to CoBo by the Slow Control Manager which updates first the body message by inserting the data extracted from the AsAd register and updates then the postamble.

From an AsAd Slow Control Manager/AsAd device point of view, the slow control manager acts as follows:

page 17


• It stores the preamble sent by CoBo and generates from it the signal enabling the device serial port (Chip Select)

• It transfers then to the device the body message received from CoBo through its MOSI output (Master Out Slave In) and, in case of a read operation, receives from the device an extracted data through its MISO input (Master In Slave Out).

The Slow Control Manager is basically in charge to switch from CoBo to one AsAd device or to switch from an AsAd device to CoBo, the correct data flow. To complete all these operation any bit that has to be stored into a register must be present at a CKS rising edge to be latched on the following falling edge, any bit that have to be extracted from a register is present on a CKS falling edge and can be processed on the following CKS leading edge

2.8.2 General description of the data flow

The 8-bit preamble four Most Significant Bits define an AsAd device address which is used by the Slow Control Manager to generate the signal enabling the device serial port. The four Least Significant Bits define the size in byte of the body message that follows. These bits are used by the Slow Control Manager to check the data transfer frame length. The 8-bit preamble is followed by a variable-sized body message which is formatted as expected to access any device register. The body message is itself followed by an 8-bit postamble which represents the 2's complement of the sum of "ones" transferred between AsAd and CoBo in any direction Preamble content Nine devices can be accessed by slow control:

• The ADS6422 (ADC) which converts the AGET analogue data • The AD9707 (DAC) which generates the AGET test or calibration pulses • The FPGA implemented test & calibration manager (TCM) which controls the AGET test mode

procedures • The ADT7519 (AMD) which is the AsAd monitoring core device • The FPGA implemented identification memory (AIM) • The FPGA implemented local clocks manager first device (LC1) which controls the AGET sampling

clock • The FPGA implemented local clocks manager second device (LC2) which controls the AGET readout

clock and the AD conversion clock • The FPGA implemented AsAd input manager (INP) • The FPGA implemented AsAd inspection manager (ISP)

Table 13 shows the preamble format linked to each accessed device within read or write mode.

page 18


Device Reference

Decimal Address

Binary Address (Preamble MSB)

Access Body size in bytes Binary Body Size in bytes (Preamble LSB)

ADC 1 0000 write 2 0001 write 2 0001 DAC 2 0001 read 2 0001 write 3 0010 TCM 3 0010 read 3 0010 write 3 0010 AMD 4 0011 read 4 0011

AIM 5 0100 read 4 0011 write 10 1001 LC1 6 0101 read 10 1001 write 10 1001 LC2 7 0110 read 10 1001 write 1 0000 INP 8 0111 read 1 0000 write 1 0000 ISP 9 1000 read 1 0000

Table 13: Slow Control preamble content

Body content As the body content varies depending on each accessed device within read or write mode, the format is given for each combination:

• The ADC is an eight write-only 11-bit registers device requiring a body message that specify a register address (5 most significant bits) followed by a 11bit data (table 14). The ADC registers map will be given into a complementary document.

(MSB) Address Data (LSB) A4 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 14: Body content format by writing a data into an ADC register

• The DAC is an eight 8-bit registers device accessible within read or write mode that requires a body message which specifies a R/W operation (most significant bit) followed by a 00 format code and 5 address bits. This first byte is followed by a data byte (table 15). The DAC registers map will be given into a complementary document.

(MSB) Instruction Address Data (LSB) R/W 0 0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Table 15: Body content format by reading or writing into a DAC register

• The TMC is a 24-bit register device accessible within read or write mode. In any mode, the body message is a 24 bit data (MSB first).

• The AMD is a twenty seven read or write 8-bit registers device. By writing into any of its 17 R/W

registers the body message is formatted as follows in table 16.

(MSB) Instruction byte Address byte 1 0 0 1 0 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0

Data byte (LSB) D7 D6 D5 D4 D3 D2 D1 D0

Table 16: Body content format by writing into an AMD register

page 19


By reading from any of its 10 read only registers or 17 R/W registers the body message is formatted as follows in table 17.

(MSB) Instruction byte Address byte 1 0 0 1 0 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0

Instruction byte Data byte (LSB)

1 0 0 1 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0

Table 17: Body content format by reading from an AMD register

The Monitoring core registers map will be given into a complementary document.

• The AIM is a 32-bit read only register device which is defined in the identification section. When it receives a read instruction the body message transferred is a 32-bit data (MSB first).

• The LC1 and LC2 each represent an 80-bit register accessible within read or write mode. In any mode the body message transferred is an 80-bit data (LSB first as stated in table 18)

(LSB) (MSB)

D0 D79

Table 18: Body content format by reading or writing into the LC1 or LC2 registers

• The INP is an 8-bit register accessible within read or write mode. In any mode the body message transferred is an 8-bit data (MSB first).

• The ISP is an 8-bit register accessible within read or write mode. In any mode the body message

transferred is an 8-bit data (MSB first).

2.9 Inputs Management

This FPGA implemented manager which is accessible by slow control, enables to bias or not the anti-sparkling protection circuits which are implemented into ZAP, as well as connect or disconnect 64 AGET inputs from 64 detector outputs. Figure 12 shows the Input Manager foreseen architecture, its output names and standards are summarized in table 19 By default AGET inputs are disconnect from the detector outputs by setting low the SWZ<3-0> levels and the anti-sparkling protection are biased by setting low the DBi<3-0>. These voltages are applied to the TS3A5018 analogue switches control inputs. Name Standard voltages Direction DBi<3-0> LVTTL/LVCMOS 3.3V Input Manager ZAP Interface SWZ<3-0> LVTTL/LVCMOS 3.3V Input Manager ZAP Interface

Table 19: Inputs Manager output names, standards and direction

page 20

http://focus.ti.com/lit/ds/symlink/ts3a5018.pdf


SPI_MISOSPI_CS7SPI_CKSPI_MOSI

INPUTS MANAGER

Slw

Ctrl

Man

8-bi

t Shi

ft R

egE

n

8-bi

t Reg

DBi1

DBi0

ZAP

Inte

rface

SWZ0

TS3A5018

Vdd

VddVdd

Vdd

Vdd

VddVdd

Vdd

TS3A5018

SWZ1

SWZ2

DBi2

SWZ3

DBi3


INPUTS MANAGER

Slw

Ctrl

Man

8-bi

t Shi

ft R

egE

n

8-bi

t Reg

DBi1

DBi0

ZAP

Inte

rface

SWZ0

TS3A5018

Vdd

VddVdd

Vdd

Vdd

VddVdd

Vdd

TS3A5018

SWZ1

SWZ2

DBi2

SWZ3

DBi3


INPUTS MANAGER

Slw

Ctrl

Man

8-bi

t Shi

ft R

egE

n

8-bi

t Reg

DBi1

DBi0

ZAP

Inte

rface

SWZ0

TS3A5018

Vdd

VddVdd

Vdd

Vdd

VddVdd

Vdd

TS3A5018

SWZ1

SWZ2

DBi2

SWZ3

ZAP

Inte

rface

SWZ0

TS3A5018

Vdd

Vdd

Vdd

VddVdd

Vdd

Vdd

Vdd

Vdd

VddVdd

Vdd

TS3A5018

SWZ1

SWZ2

DBi2

SWZ3

DBi3

Figure 12: Inputs Manager architecture and interconnections

2.10 Inspections Management

This FPGA implemented manager receives or drives some AsAd "critical" signals by the External Instruments Interface. The signals to be received or to be driven are chosen by slow control. The Inspection Manager can drive to the interface:

• The signals Write (SCA write command) coming from the Cycle Controller and WCK (sampling clock) coming from the Local Clocks Manager

• Or the signals Read (SCA read command) coming from the cycle controller and RCK (readout clock) coming from the Local Clocks Manager

• Or the signals RCK and ACK (readout clock and AD conversion clock) coming from the Local Clocks Manager

• Or the signal PWG (Power supply good) coming from the Power Manager • Or the signal CKO (Calibration pulse trigger sent by slow control) coming from the test and

calibration manager The Inspection Manager can receive from the interface:

• The signal CKO (Calibration pulse trigger sent by an external generator) Figure 13 shows the Inspection Manager foreseen architecture, its I/O names and standards are summarized in table 20

page 21


Name Standard voltages Direction CKO LVTTL/LVCMOS 3.3V Test & Cal. Man. Inspection Manager PWG LVTTL/LVCMOS 3.3V Power Manager Inspection Manager WCK LVTTL/LVCMOS 3.3V Local Clocks Manager Inspection Manager RCK LVTTL/LVCMOS 3.3V Local Clocks Manager Inspection Manager ACK LVTTL/LVCMOS 3.3V Local Clocks Manager Inspection Manager Write LVTTL/LVCMOS 3.3V Cycle Controller Inspection Manager Read LVTTL/LVCMOS 3.3V Cycle Controller Inspection Manager DIR LVTTL/LVCMOS 3.3V Inspection Manager Ext. Inst. Interface ISP1 LVTTL/LVCMOS 3.3V Inspection Manager Ext. Inst. Interface ISP2 LVTTL/LVCMOS 3.3V Inspection Manager Ext. Inst. Interface

Table 20: Inspection Manager I/O names, standards and direction

ISP 1

ISP2

EnA1A0

A1A0

WCKRCKACK


INSPECTION MANAGER BLOCK

Slw

Ctrl

Man

DIR

8-bi

t Shi

ft R

eg

8-bi

t Reg

En

Ext

erna

lIns

trum

ents

Inte

rface

Loc.

lClk

Man

Cyc

le C

trl

writeread

CKO

PWG

Pw

rMan

Tst&

C

al

Man

ISP 1

ISP2

EnA1A0

A1A0

WCKRCKACK


INSPECTION MANAGER BLOCK

Slw

Ctrl

Man

DIR

8-bi

t Shi

ft R

eg

8-bi

t Reg

En

Ext

erna

lIns

trum

ents

Inte

rface

Loc.

lClk

Man

Cyc

le C

trl

writeread

CKO

PWG

Pw

rMan

Tst&

C

al

Man

Figure 13: Inspection Manager architecture and interconnections

2.11 Identification

The block in use to identify AsAd is implemented into its FPGA on-chip user non volatile memory (Actel A3PE1500). It consists of a 32-bit register which content is written by the FPGA JTAG interface.

The register content is readable by slow control. Its format is the same defined for all GET hardware sub-systems and is given in table 21.

I<31-28> I<27-24> I<23-20> I<19-16> I<15-12> I<11-0> User defined Slot Number TPC reference Hard release Board Type Serial number

Table 21: Identification format

page 22


3 PART TWO: AsAd Interfaces

3.1 AsAd-CoBo Interface

The AsAd -CoBo interconnection is completed by a 3 meters length cable which consists of double-shielding (foil and braid) enclosing 34 twisted pairs connected to VHDCI connectors (68-contacts). This cable supports SCSI transfers up to 320Mbps (it is then well suited for high transfer rates through 50Ω differential pairs). The connexion diagram for this cable used as the AsAd-CoBo interconnection is given in figure 14. Table 22 gives for each signal name, its position, its standard and direction, as well as its general description.

GNDOD1+OD0+OC1+OC0+GNDCKF+CKB+GNDOB1+OB0+OA1+OA0+GNDCKP+GNDCKR+

GNDOD1-OD0-OC1-OC0-GNDCKF-CKB-GNDOB1-OB0-OA1-OA0-GNDCKP-GNDCKR-

GNDOD1+OD0+OC1+OC0+GNDCKF+CKB+GNDOB1+OB0+OA1+OA0+GNDCKP+GNDCKR+

GNDOD1-OD0-OC1-OC0-GNDCKF-CKB-GNDOB1-OB0-OA1-OA0-GNDCKP-GNDCKR-

2

1

34

33

A0C-CA0-A1C-CA1-A2C-CA2-A3C-CA3-GNDPLGALGNDACSGNDSCWGNDCKW-

A0C+CA0+A1C+CA1+A2C+CA2+A3C+-CA3+GNDPWDNCCKSCASGNDSCRGNDCKW+

A0C-CA0-A1C-CA1-A2C-CA2-A3C-CA3-GNDPLGALGNDACSGNDSCWGNDCKW-

A0C+CA0+A1C+CA1+A2C+CA2+A3C+-CA3+GNDPWDNCCKSCASGNDSCRGNDCKW+

36

35

68

67

38

37

40

39

42

41

44

43

46

45

48

47

50

49

52

51

54

53

56

55

58

57

60

59

62

61

64

63

66

65

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

VHDCI 68 cable reference (twisted pairs)

Figure 14: AsAd-CoBo interconnection

ASAD COBOLVCMOS 3.3VSCA readSCR39

ASAD COBOLVCMOS 3.3VSCA writeSCW40

ASAD COBOLVDSSCA Write ClockCKW35,36

ASAD COBOLVDSADC D output MSBOD131,32

ASAD COBOLVDSADC D output LSBOD029,30

ASAD COBOLVDSADC C output MSBOC127,28

ASAD COBOLVDSADC C output LSBOC025,26

ASAD COBOLVDSADC’s Frame ClockCKF21,22

ASAD COBOLVDSADC’s Bit ClockCKB19,20

ASAD COBOLVDSADC B output MSBOB115,16

ASAD COBOLVDSADC B output LSBOB013,14

ASAD COBOLVDSADC A output MSBOA111,12

ASAD COBOLVDSADC A output LSBOA09,10

ASAD COBOLVDSAGET Serial Control ClockCKP5,6

ASAD COBOLVDSSCA Read ClockCKR1,2

DirectionStandardDescriptionNamePosition

ASAD COBOLVCMOS 3.3VSCA readSCR39

ASAD COBOLVCMOS 3.3VSCA writeSCW40

ASAD COBOLVDSSCA Write ClockCKW35,36

ASAD COBOLVDSADC D output MSBOD131,32

ASAD COBOLVDSADC D output LSBOD029,30

ASAD COBOLVDSADC C output MSBOC127,28

ASAD COBOLVDSADC C output LSBOC025,26

ASAD COBOLVDSADC’s Frame ClockCKF21,22

ASAD COBOLVDSADC’s Bit ClockCKB19,20

ASAD COBOLVDSADC B output MSBOB115,16

ASAD COBOLVDSADC B output LSBOB013,14

ASAD COBOLVDSADC A output MSBOA111,12

ASAD COBOLVDSADC A output LSBOA09,10

ASAD COBOLVDSAGET Serial Control ClockCKP5,6

ASAD COBOLVDSSCA Read ClockCKR1,2


ASAD COBOLVDSAGET0 Serial Control Data inCA065,66

ASAD COBOLVDSAGET0 Serial Control Data outA0C67,68







ASAD COBOLVCMOS 3.3VASAD presencePLG50

ASAD COBOLVCMOS 3.3VASAD switch on/offPWD49

ASAD COBOLVCMOS 3.3VAlarm FlagAL48

Not ConnectedNC47

ASAD COBOLVCMOS 3.3VSlow Control ClockCKS45

ASAD COBOLVCMOS 3.3VSlow Control Data outACS44

ASAD COBOLVCMOS 3.3VSlow Control Data inCAS43










ASAD COBOLVCMOS 3.3VASAD presencePLG50

ASAD COBOLVCMOS 3.3VASAD switch on/offPWD49

ASAD COBOLVCMOS 3.3VAlarm FlagAL48

Not ConnectedNC47

ASAD COBOLVCMOS 3.3VSlow Control ClockCKS45

ASAD COBOLVCMOS 3.3VSlow Control Data outACS44

ASAD COBOLVCMOS 3.3VSlow Control Data inCAS43


Positions 3, 4, 7, 8, 17,18, 23, 24, 33, 34, 37, 38, 41, 42, 46, 51 52 are grounded (GND =OV)

Table 22: AsAd-CoBo interconnection details

The AsAd connector that matches with the previously described cable, as well as its pinout, are represented on figure 15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

67 6865 6663 6461 6259 6057 5855 5653 5451 5249 504846 4744 454341 424038 393735 36

353637383940

OA0

-G

ND

GN

D

OA0

+O

A1-

OA1

+O

B0-

OB

0+O

B1-

OB

1+G

ND

GN

DC

KB

-C

KB

+C

KF-

CK

F+G

ND

GN

DO

C0-

OC

0+O

C1-

OC

1+O

D0-

OD

0+O

D1-

OD

1+

GN

DG

ND

CK

P+C

KP-

GN

DG

ND

CK

W+

CK

W-

GN

DG

ND

68 6741424344454648495051 66 65 64 63 62 61 60 59 58 57 56 55 54 5352

CA

3+C

A3-

A3C

+A

3C-

CA

2+C

A2-

A2C

+A

2C-

CA

1+C

A1-

A1C

+A

1C-

CA

0+C

A0-

A0C

+A

0C-

CK

R+

CK

R-

GN

DG

ND

SCR

SCW

GN

D

CAS

AC

S

GN

D

CK

S

VHDCI 68 PCB Connector ref.

ASAD Pinout

ALPWD

PLG

GN

D

Figure 15: AsAd connection side

page 23

http://www.tripplite.com/en/products/model.cfm?txtModelID=2782


Buffering strategy: All signals that have to be transferred through the AsAd-CoBo Interface are LVDS or LVTTL/LVCMOS 3.3V compatible (excepting PLG which will be described here-after). The global buffering scheme used for each of these standards is given in figure 16. To save room-space first, and to have enhanced performances on the AsAd side, it is foreseen to include into the AsAd FPGA all the LVDS buffers (jitter + skew < 20ps rms). The LVTLL/LVCMOS 3.3V receivers must be outside the FPGA (The maximal voltage admissible for a FPGA buffer input in a low state is 0.4V, versus 0.9V for a 74AC11245 as an example device).

AsAd

-CoB

oIn

terfa

ce

100Ω

LVDS-

LVDS +

100Ω

50Ω

50Ω

50Ω

-

+10

0Ω

Vdd=3.3V

LVCMOS 3.3V

74AC11245

Receiver side Driver side

LVDS Buffering in accordance with Fairchild AN5017 LVCMOS 3.3V buffering in accordance with ICS « High Speed CMOS Driver Termination Design Guide »

LVCMOS 3.3V details:Two 100Ω resistors are used to terminate the transmission line in order to match the cable impedance.When the driver output buffer is low (0V) the voltage V at the receiver input is given by:

Which leads to V=0.825 V and thus to an output current for the driver buffer equal to -16.5mAWhen the driver output buffer is high (3.3V) the voltage V at the receiver input is given by:

Which leads to V=2.475 V and thus to an output current for the driver buffer equal to +16.5mA

50V

100V

100V3.3

+=−

100V

50V3.3

100V3.3

=−

+−

AsAd

-CoB

oIn

terfa

ce

100Ω

LVDS-

LVDS +

100Ω

LVDS-

LVDS +

100Ω

50Ω

50Ω

50Ω

-

+10

0Ω

Vdd=3.3V

LVCMOS 3.3V

74AC11245

Receiver side Driver side

LVDS Buffering in accordance with Fairchild AN5017 LVCMOS 3.3V buffering in accordance with ICS « High Speed CMOS Driver Termination Design Guide »

LVCMOS 3.3V details:Two 100Ω resistors are used to terminate the transmission line in order to match the cable impedance.When the driver output buffer is low (0V) the voltage V at the receiver input is given by:

Which leads to V=0.825 V and thus to an output current for the driver buffer equal to -16.5mAWhen the driver output buffer is high (3.3V) the voltage V at the receiver input is given by:

Which leads to V=2.475 V and thus to an output current for the driver buffer equal to +16.5mA

50V

100V

100V3.3

+=−

100V

50V3.3

100V3.3

=−

+−

Figure 16: AsAd-CoBo buffering scheme

The PLG connection enables CoBo to detect AsAd presence. Following the previous scheme, this connection is made as represented in figure 17.

AsA

d-C

oBo

Inte

rface

100Ω

50Ω 100Ω

Vdd=3.3V

PLG

74AC11245

AsAd side CoBo side

When AsAd is disconnected, the CoBo input buffer voltage is 3.3VWhen AsAd is connected, the CoBo input buffer voltage is 0.825V

AsA

d-C

oBo

Inte

rface

100Ω

50Ω 100Ω

Vdd=3.3V

PLG

74AC11245

AsAd side CoBo side

When AsAd is disconnected, the CoBo input buffer voltage is 3.3VWhen AsAd is connected, the CoBo input buffer voltage is 0.825V

Figure 17: AsAd presence from a CoBo point of view

page 24

http://focus.ti.com/lit/ds/symlink/74ac11245.pdf


page 25

3.2 AsAd-GET Power Unit Interface

The AsAd connector that allows linking the GET power supply unit is one of the M250 series ATI connectors (There is no M250 description available on the internet but this series are vey similar with the M220) This connector is a 2 gold plated contacts (15A/ctc) male connector with latches that exhibits a 6 mΩ resistive contact. Its metallic body enables to meet the EMC requirements by using an interconnection cable which shielding is ground-connected on both sides of the cable. Figure 18 is a diagram showing how to connect to the GET Power Supply Unit using the ATI M250 series connector: AsAd is linked to a power dispatching module by a 30cm length shielded cable. Each dispatcher enables to feed four AsAd board and is itself linked by a M250 4-contacts connector to a 200W power supply module. The M250 4-contacts connector allows a load regulation of the supply voltage (V+ - V-) applied at each dispatcher input.

M250

V-

V+

Sense-

Sense+

M250M250M250M250

M250

GN

D

Power Dispatching(12A max)

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250

GN

D


V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250

M250

GN

D


V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250

M250

GN

D


V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

1024 Channels

30cm max

Power Supply Unit Module

(4096 channels; ≈200W)

M250

250cm

(total length =300cm)

V1- V2- -

S3-

V4-

S4-

V1+ = V2+ = V3+ = V4+ = 4V±10%

V1- = V2- = V3- = V4- = 0V

S1-V1+

S1+ S2+

V2+ S2-

S3+

V3+

V3 S4+

V4+

M250

V-

Sense-

V+

Sense+

M250M250M250M250

M250

GN

D


V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250

GN

D


V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250

M250

GN

D


V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250

M250

GN

D


V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

GN

D

V+

AsAd

M250(3A m

ax)

1024 Channels

30cm max



M250

250cm


V1- V2- -

S3-

V4-

S4-

V1+ = V2+ = V3+ = V4+ = 4V±10%

V1- = V2- = V3- = V4- = 0V

S1-V1+

S1+ S2+

V2+ S2-

S3+

V3+

V3 S4+

V4+

M250

V-

Sense-

V+

Sense+

M250M250M250M250M250M250M250M250

M250

GN

D

V+

GN

D


V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250M250M250M250M250

GN

D

V+

GN

D


V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250M250M250M250M250

M250

GN

D

V+

GN

D


V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

1024 Channels

M250

V-

Sense-

V+

Sense+

M250M250M250M250M250M250M250M250

M250

GN

D

V+

GN

D


V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

GN

D

V+

GN

D

V+

AsAd

M250(3A m

ax)

AsAd

M250M250(3A m

ax)

1024 Channels

30cm max



M250

250cm


V1- V2- -

S3-

V4-

S4-

V1+ = V2+ = V3+ = V4+ = 4V±10%

V1- = V2- = V3- = V4- = 0V

S1-V1+

S1+ S2+

V2+ S2-

S3+

V3+

V3 S4+

V4+

Figure 18: AsAd-GET Power Supply Unit Interconnection

Behind the power connector, AsAd uses a fuse able to protect the AsAd Power Supply block if an overload occurs.

3.3 AsAd-External Instruments Interface

The AsAd External Instruments Interface is directly linked to the Inspection Manager inputs/outputs (described in the first part of this document). This interface is composed of a 74AC11245 chip connected to two LEMO elbow sockets for printed circuit (EPL.00.250.NTN) as shown in figure 19.

http://www.ati-electronique.fr/connec2.htm

http://www.vishay.com/docs/28747/28747.pdf

http://focus.ti.com/lit/ds/symlink/74ac11245.pdf

http://intra.lemo.ch/WD140AWP/WD140Awp.exe/CTX_5876-122-JNMXSZeUPq/SinglePartDisplay/SYNC_-423072562


AsAd External Instruments Interface

74AC11245

DIR

OE*

A1

A2

B2

B1LEMO

LEMO

Insp

ectio

nM

anag

erISP1

ISP2

DIR

AsAd External Instruments Interface

74AC11245

DIR

OE*

A1

A2

B2

B1LEMO

LEMO

Insp

ectio

nM

anag

erISP1

ISP2

DIR

Figure 19: AsAd-External Instruments Interface

3.4 AsAd-ZAP Interface

For the AsAd-ZAP Interface a 68 contacts connector is at least required (64 contacts to connect the AGET inputs + 1 contact for the protection diode biasing + 1 contact to control the 64 AGET inputs from the detector outputs + 2 GND). Additional pins may be required depending on the amount of current needed to bias the ZAP protection diodes, and depending on the way of shielding ZAP. To minimize the crosstalk on ZAP, the connector pitch should not be less than 1.27 mm. A 2 rows connector would have in this case a minimal length of 43.18mm (68 contacts x 1mm pitch / 2 rows). 4 connectors of this type required for AsAd lead to an AsAd edge length that cannot be lower than 172.2mm (≈ 20cm). Taken into account the ASIC size (based on the AFTER packaging) and the bus size to route its 64 inputs, the AsAd length can't anyway be lower than 20 cm (c. f. this document part 3 AsAd board dimensions section). Under these conditions an ERNI connector (ref 114805) can be used as the AsAd-ZAP interface. Nevertheless, others solutions are still studied as more than 68 contacts can be required at the AsAd-ZAP interface and as the ASIC packaging could change in a future version. Four rows connectors are particularly under the scope to achieve the AsAd-ZAP interface.

3.5 AsAd-JTAG Interface

This expert interface enables to upgrade AsAd firmware and to define an ID tag for it (c.f. Identification section in the first part of the document). This interface description is given into an ACTEL application note.

page 26

http://www.erni.com/smc.htd?gID=4654590

http://www.embedtools.com/pro_kaifa/SOPC_%20EDA/ProASIC3/PA3_E_UJTAG_AN.pdf


4 PART THREE: AsAd in its physical context

4.1 AsAd board size

One of the major constraints for AsAd is to host four AGET and provide them with signals having the best immunity against noise, parasites and crosstalk. Under these conditions the best relative placement between AGET and the AsAd-ZAP interface connector is presented in figure 20.

32- inputs

64-i

nput

s fro

mZA

P

32- inputs

AGET controls

Bias AGET

32- inputs

64-i

nput

s fro

mZA

P

32- inputs

AGET controls

Bias AGET

Figure 20: AGET/AsAd-ZAP Interface relative placement

In this placement configuration, there are indeed no clocks signals crossing the input signals at any level (from a board layer point of view) and the room-space taken by the biasing components do not increase AsAd edge length. Assuming a class 5 routing for AsAd (conductors minimal width and isolation between conductors both equal to150µm) the 64 inputs bus width is approximately equal to 19.2mm (64x2x150µm). AGET itself represents a 30.2 x 30.2 mm² area, which leads to define one dimension for the physical block shown in figure 20 equal to 49.4mm (30.2mm+19.2mm). Assuming this basic pattern replicated for times, AsAd edge length cannot be lower than 197.6mm (figure 21)

30.2 mm

30.2 mm

30.2 mm

30.2 mm

9.6 mm

9.6 mm9.6 mm

9.6 mm9.6 mm

9.6 mm9.6 mm

9.6 mm

30.2 mm

30.2 mm

30.2 mm

30.2 mm

9.6 mm

9.6 mm9.6 mm

9.6 mm9.6 mm

9.6 mm9.6 mm

9.6 mm

Figure 21: AsAd minimal edge length

page 27


AsAd foreseen length is thus 20 cm. Its width is deduced from the FPGA and ADC placements on the symmetry axis of the pattern shown in figure 21. The figure 22 represents a foreseen view of the AsAd dimensions regarding to its components locations.

10,8

19,2

19,2

19,2

19,2

10,8

4

4

4

4

12

6

5

5

6 66 15

35

20

70,8 6 3

10

44

20

2

1002

2

135

200

AsAd components locations

10,8

19,2

19,2

19,2

19,2

10,8

4

4

4

4

12

6

5

5

6 66 15

35

20

70,8 6 3

10

44

20

2

1002

2

135

200

10,8

19,2

19,2

19,2

19,2

10,8

4

4

4

4

12

6

5

5

6 66 15

35

20

70,8 6 3

10

44

20

2

1002

2

135

200

AsAd components locations

Figure 22: AsAd size and component locations

page 28


The yellow area represents AsAd size, the grey areas represent AsAd main connectors, and the green areas represent the AsAd components. Each component is referenced by a number (black background for the components dissipating power, transparent background for the others), a description for each one is given in table 23. Dimensions may vary with the availability of the components in the chosen packages, that’s the reason why some dimensions are drawn in red. AsAd width should anyway be 135mm ±10%.

0,071,6 ±0,1557DC/DC converter

4,29,748,2Connector

614,6542,7Connector

4,66,916,1Connector

7717,7Connector

1652,6 ±0,11116Buffers

11 ±0,1533VRef for DAC

0,260,9 ±0,13,653,65Switches

0,281,6 ±0,1557Transimpedance Ampli.

101,6 ±0,1557Monitoring core

7503,9 ±0,230,630,6FPGA

4501 ±0,15,55,5Regulator

4001,6 ±0,1557Transimpedance Ampli.

601 ±0,15,55,5DAC

1,5 ±0,1

3,3 ±0,1

0,9 ±0,1

Heigth (mm)

72030,230,2ASIC

9003,29,1Rsense

12501010ADC

Power max (mW)Width (mm)Length (mm)FunctionRef.

Table 23: AsAd components sizes and maximal dissipated power

4.2 AsAd Module (EMC and cooling aspects)

AsAd board must be enclosed into a Faraday cage to prevent it from troubleshooting caused by electromagnetic fields. The board and its shielding constitute the AsAd module. The manufacturing of the shielding mechanics is done by machining in the mass. Therefore, connection of 0 V to the chassis should not generate disrupting currents flows in the sensitive areas. The electrical continuity with the removable top of the module is provided by metallic screws (additional conductive seals may also be used). The AsAd modules must be connected to the mechanical ground with a load impedance as low as possible. Figure 23 shows an artistic view of the shielding module shape.

page 29


ZAP input

CoBo I/O SupplyInspection

ZAP input

CoBo I/O SupplyInspection

Figure 23: Shielding shape

Because of the AsAd electromagnetic environment, as well as the AsAd reduced mounting space, the use of a liquid cooling solution to dissipate the power consumed is required (An installation of liquid cooling comprises additional equipment: a pump, a flow controller, a storage tank and finally a heat exchanger). The estimated maximal power dissipated by AsAd is deduced from table 23, it is approximately equal to 9W. The cooling system is integrated in the top of the board housing. A thermal conductivity between AsAd components and the top of the module is provided by graphite films (figure 24). Assuming an operating temperature equal to 20° with a margin of ±4°C the liquid input/output system can be connected to 4 AsAd modules. The total height of the housing with cooling will be approximately 12 mm. Sealing is ensured by friction-stir of the metal constituting the top.

Liqu

idin

put

Liqu

id o

utpu

t

Top

Graphite PCB Integrated circuit

Liqu

idin

put

Liqu

id o

utpu

t

Top

Graphite PCB Integrated circuit

Figure 24: AsAd module cooling profile

page 30


page 31

GET – Front End:AsAd Technical SpecificationUser Requirements Document Issue:

page 32

Reference: - Revision: 0

1 Last modified: -

Appendix A: AsAd functional diagram


page 1

Serial Control

ALERT MAN.

LOC. CK. MAN

CYCLE CTRL

12345678910111213141516171819202122232425262728293031323334

353637383940

OA0-GNDGND

OA0+OA1-OA1+OB0-OB0+OB1-OB1+GNDGNDCKB-CKB+CKF-CKF+GNDGNDOC0-OC0+OC1-OC1+OD0-OD0+OD1-OD1+

GNDGND

CKP+CKP-GNDGND

CKW+CKW-

GNDGND

6867

414243444546

48495051

6665646362616059585756555453

52

CA3+CA3-A3C+A3C-CA2+CA2-A2C+A2C-CA1+CA1-A1C+A1C-CA0+CA0-A0C+A0C-

CKR+CKR-

GNDGNDSCRSCW

GND

CASACS

GND

CKS

ALPWDPLG

GND

VO3-

ADC A

ADC C

ADC D

ADS6422

ACK-ACK+

SP

I_C

S0*

SP

I_C

K*

SP

I_M

OS

I

VO3+

ADC B

VO2-

VO2+

VO1-

VO1+

VO0-

VO0+

TEST & CALIBRATION MANAGER.

SP

I_CK

SP

I_CS

2

SP

I_MIS

OS

PI_M

OS

I

AD9707 (DAC)D

00D

01D

02D

03D

04D

05D

06D

07D

08D

09D

10D

11D

12D

13

SDIOSCLKCLK+

SP

I_CS

1*

Transimpedance

Amplifier (AD8062)

IAIB

VG

Rng

CalCKO

Mode<0>

writeread SCR

SCW

CKRCKW

SPI_CS5

SPI_MOSISPI_CK

SPI_MISORCK-RCK+WCK-WCK+

ACK-ACK+SC_Ck CKP

Mode<1>

Mode<1>Mode<0>

SPI_CS6

Serial Control

Serial Control

Serial Control

A0CCA0

A1CCA1

A2CCA2

A3CCA3

SC

_Ck

Mode1

Mode0

SC

_Ck

Mode1

Mode0

SC

_Ck

Mode1

Mode0

SC

_Ck

Mode1

Mode0

SC_Dout0SC_CkSC_En0SC_Din0SC_Dout1SC_CkSC_En1SC_Din1SC_Dout2SC_CkSC_En2SC_Din2SC_Dout3SC_CkSC_En3SC_Din3

VO1 -


Write

SC_Dout1SC_Ck1SC_En1

SC_SDin1

AGET 1

InCal1InTst1

VO1+

IQ

AL

VO2 -

AGET 2

InCal2InTst2

VO2+


Write


SC_SDin2

VO3 -

AGET 3

InCal3InTst3

VO3+


Write


SC_SDin3

VO0 -

AGET 0

InCal0InTst0

VO0+


Write


SC_SDin0

ADT7519

(Monitoring)

IQ

SP

I_CS

3*S

PI_C

K

SP

I_MIS

OS

PI_M

OS

I

Vdd1

T°sense

Ain1

Ain2

Ain3

Ain4

SLO

W C

TRL

MA

NA

GER

ACSCAS

CKS

SPI_CKSPI_MOSI

SPI_CS0*SPI_CS1*SPI_CS2SPI_CS3*SPI_CS4SPI_CS5

SPI_MISO

SPI_CS6SPI_CS7

IDEN

TIFI

ERS

PI_

CK

SP

I_M

ISO

SP

I_C

S4

FPGA Pr IC3Eo AS

JTAG

25/50MHz

25MHz

1→100MHz

10MHz

150MHz

25MHz

Analog MUXs

& capacitorsCalRng

VG

DBi3SWZ3

ZAP 64 inputs

AsAd Architecture

DBi0SWZ0

ZAP 64 inputs

Vdd

DBi1SWZ1

ZAP 64 inputs

DBi2SWZ2

ZAP 64 inputs

PWR MAN. ALPWD

TPS

7440

1

(ULD

O)

Vdd

En

Bia

s

Vou

t

I sen

se

TPS

7440

1

(ULD

O)

En

Bia

sV

inV

out TP

S74

401

(ULD

O)

En

Bia

sV

in

TPS

7440

1

(ULD

O)

En

Bia

sV

in

Vou

t

Vdd

3

Vdd

2

Vdd

1

INA122

VddE

n

LTC1516

(Charge pump reg)5V

INSP. MAN.

SPI_CS8

SPI_CKSPI_MOSISPI_MISO

SPI_CS8

CKO

Bi-Dir. BuffersISP1

ISP2

Dir.

ISP1ISP2

DIR

WCKRCK

ACKreadwrite

CKOPWG

PWG

1PW

G2

PWG

3

INPUTS MAN.

SP

I_CK

SP

I_CS

7S

PI_M

OS

IS

PI_M

ISO

SW

Z0

SW

Z1

SW

Z2

SW

Z3

DB

i0

DB

i1

DB

i2

DB

i3

PWG

1

PWG

2

PWG

3

V se

nse

Vin

Vou

t

fuse

LEM

OV

HD

CI

68AT

I M

250

GND

VddGND

VddGND

VddGND

V+

Vin

CSB*

SP

I_CK

CKO

Serial Control

ALERT MAN.

LOC. CK. MAN

CYCLE CTRL

12345678910111213141516171819202122232425262728293031323334

353637383940

OA0-GNDGND

OA0+OA1-OA1+OB0-OB0+OB1-OB1+GNDGNDCKB-CKB+CKF-CKF+GNDGNDOC0-OC0+OC1-OC1+OD0-OD0+OD1-OD1+

GNDGND

CKP+CKP-GNDGND

CKW+CKW-

GNDGND

6867

414243444546

48495051

6665646362616059585756555453

52

CA3+CA3-A3C+A3C-CA2+CA2-A2C+A2C-CA1+CA1-A1C+A1C-CA0+CA0-A0C+A0C-

CKR+CKR-

GNDGNDSCRSCW

GND

CASACS

GND

CKS

GND

VO3-

ALPWDPLG

ADC A

ADC C

ADC D

ADS6422

ACK-ACK+

SP

I_C

S0*

SP

I_C

K*

SP

I_M

OS

I

VO3+

ADC B

VO2-

VO2+

VO1-

VO1+

VO0-

VO0+

TEST & CALIBRATION MANAGER.

SP

I_CK

SP

I_CS

2

SP

I_MIS

OS

PI_M

OS

I

AD9707 (DAC)D

00D

01D

02D

03D

04D

05D

06D

07D

08D

09D

10D

11D

12D

13

SDIOSCLKCLK+

SP

I_CS

1*

Transimpedance

Amplifier (AD8062)

IAIB

VG

Rng

CalCKO

Mode<0>

writeread SCR

SCW

CKRCKW

SPI_CS5

SPI_MOSISPI_CK

SPI_MISORCK-RCK+WCK-WCK+

ACK-ACK+SC_Ck CKP

Mode<1>

Mode<1>Mode<0>

SPI_CS6

Serial Control

Serial Control

Serial Control

A0CCA0

A1CCA1

A2CCA2

A3CCA3

SC

_Ck

Mode1

Mode0

SC

_Ck

Mode1

Mode0

SC

_Ck

Mode1

Mode0

SC

_Ck

Mode1

Mode0

SC_Dout0SC_CkSC_En0SC_Din0SC_Dout1SC_CkSC_En1SC_Din1SC_Dout2SC_CkSC_En2SC_Din2SC_Dout3SC_CkSC_En3SC_Din3

VO1 -


Write


SC_SDin1

AGET 1

InCal1InTst1

VO1+

IQ

AL

VO2 -

AGET 2

InCal2InTst2

VO2+


Write


SC_SDin2

VO2 -

AGET 2

InCal2InTst2

VO2+


Write


SC_SDin2


Write


SC_SDin2

VO3 -

AGET 3

InCal3InTst3

VO3+


Write


SC_SDin3

VO3 -

AGET 3

InCal3InTst3

VO3+


Write


SC_SDin3


Write


SC_SDin3

VO0 -

AGET 0

InCal0InTst0

VO0+


Write


SC_SDin0


Write


SC_SDin0

ADT7519

(Monitoring)

IQ

SP

I_CS

3*S

PI_C

K

SP

I_MIS

OS

PI_M

OS

I

Vdd1

T°sense

Ain1

Ain2

Ain3

Ain4

SLO

W C

TRL

MA

NA

GER

ACSCAS

CKS

SPI_CKSPI_MOSI

SPI_CS0*SPI_CS1*SPI_CS2SPI_CS3*SPI_CS4SPI_CS5

SPI_MISO

SPI_CS6SPI_CS7

IDEN

TIFI

ERS

PI_

CK

SP

I_M

ISO

SP

I_C

S4

FPGA Pr IC3Eo AS

JTAG

25/50MHz

25MHz

1→100MHz

10MHz

150MHz

25MHz

Analog MUXs

& capacitorsCalRng

VG

DBi3SWZ3

ZAP 64 inputs

AsAd Architecture

DBi0SWZ0

ZAP 64 inputs

Vdd

DBi1SWZ1

ZAP 64 inputs

DBi2SWZ2

ZAP 64 inputs

PWR MAN. ALPWD

TPS

7440

1

(ULD

O)

Vdd

En

Bia

s

Vou

t

I sen

se

TPS

7440

1

(ULD

O)

En

Bia

sV

inV

out TP

S74

401

(ULD

O)

En

Bia

sV

in

TPS

7440

1

(ULD

O)

En

Bia

sV

in

Vou

t

Vdd

3

Vdd

2

Vdd

1

INA122

VddE

n

LTC1516

(Charge pump reg)5V

INSP. MAN.

SPI_CS8

SPI_CKSPI_MOSISPI_MISO

SPI_CS8

CKO

Bi-Dir. BuffersISP1

ISP2

Dir.

ISP1ISP2

DIR

WCKRCK

ACKreadwrite

CKOPWG

PWG

1PW

G2

PWG

3

INPUTS MAN.

SP

I_CK

SP

I_CS

7S

PI_M

OS

IS

PI_M

ISO

SW

Z0

SW

Z1

SW

Z2

SW

Z3

DB

i0

DB

i1

DB

i2

DB

i3

PWG

1

PWG

2

PWG

3

V se

nse

Vin

Vou

t

fuse

LEM

OV

HD

CI

68AT

I M

250

GND

VddGND

VddGND

VddGND

V+

Vin

CSB*

SP

I_CK

CKO

GET – Front End · GET – Front End:AsAd Technical Specification Reference: - User Requirements...

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Transcript of GET – Front End · GET – Front End:AsAd Technical Specification Reference: - User Requirements...