Georgia Tech Digital Back-endµHRG interface

Curtis MayberrySchool of Electrical and Computer Engineering

Georgia Institute of Technology

January 13th, 2014

Contact: Curtisma@gatech.edu www.ece.gatech.edu/research/integrated-mems/

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Topics• System Design• Digital Processing• ADC • DAC • Power Supply• AFE Interface• Feed Through Cancellation Tuning• Review Measures

Topics

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System Overview• Analog Front End (Red Board)

– Device Pad– Pickoff Channels (Node and Antinode)– Forcer Channels (node and Antinode)– Feed-through Cancellation (x4)– Quadrature Amplifiers (50v)

• Digital Back End (GT BE)– 24 bit ADC (8 Channels) and LPF ADC Drivers– 16 bit DAC (8 Channels) and Reconstruction LPF– Feed Through Cancellation Tuning Digital Potentiometers

• Digital Signal Processor (TI Tiva C Launchpad)– 80 MHz MCU Development Board

System Design

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System Diagram

System Design

Microcontroller: TI Tiva C Series• 80 MHz 32bit MCU (internal PLL to adjust)• 4xSPI Serial communication• Single Precision Floating point• 128 kB Flash• Up to 43 GPIOs• Tiva C Launchpad

– Microcontroller Part Number: TM4C123GH6PMI

– On-board ICDI • USB programmer and debugger

– 40 Pin Header to connect to back-end– On-board RGB LED and 2 Switches– USB Powered

Digital Processing

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Alternative Signal Processor: FPGA• Spartan 6 XC6SLX9 FPGA• 84 digital IO pins• 8 analog inputs• 8 general purpose LEDs• 1 reset button• 1 LED to show when the FPGA is correctly

configured • On board voltage regulation that can

handle 4.8V - 12V• A microcontroller (ATmega16U4) used for

configuring the FPGA, USB communications, and reading the analog pins

• On board flash memory to store the FPGA configuration file

Digital Processing

• Board designed to mate on top of Tiva C series Launchpad

• Uses female 0.1” Low profile Headers by Samtec to mate with the Launchpad

• Can use ribbon cable and header strip to reposition Launchpad

Connection: Launchpad

Interface

Connection: Launchpad Ports

Pin Connection Port Con Pin Connection Port Con Pin Connection Port Con3.3V - - J1.01 TEST0 ~LDAC_FORCER GPIO P PE1 J3.07GND GND - J2.01 TEST1 ~LDAC_QUAD GPIO P PE2 J3.085.0V - - J3.01 CLKDIV GPIO PE5 PE5 J1.06 ~CLR GPIO P PE3 J3.09GND GND - J3.02 ~SYNC GPIO PE0 PE0 J2.03

CLK M1PWM5 PF1 J3.10 SCLK SPI0_CLK PA2 J2.10MODE0 GPIO PA6 PA6 1.09 SDIN SPI0_MOSI PA5 J1.08

RESET - - J2.05 MODE1 GPIO PA7 PA7 1.10 SDO SPI0_MISO PA4 J2.08Red LED R2 PF1 - FORMAT0 GPIO PC4 PC4 J4.04 ~SYNC SPI0_FS_CS PA3 J2.09Blue LED R11 PF2 J4.01 FORMAT1 GPIO PC5 PC5 J4.05Green LED R12 PF3 J4.02 FORMAT2 GPIO PC6 PC6 J4.06USR_SW1 R13 PF4 J4.10

SCLK SPI2_CLK PB4 J1.07

DOUT1 SPI2_MISO PB6 J2.07DOUT2 GPIO PB0 PB0 J1.03DOUT3 GPIO PB1 PB1 J1.04DOUT4 GPIO PB2 PB2 J2.02

PB6-PD0 PB6 J2.07 DOUT5 GPIO PB3 PB3 J4.03 SCLK SPI1_CLK PD0 J3.03PB6-PD0 PD0 J3.03 DOUT6 GPIO PB7 PB7 J2.06 DIN SPI1_MOSI PD3 J3.06PB7-PD1 PB7 J2.06 DOUT7 GPIO PD6 PD6 J4.08 ~CS (U9) DPOT1_CS PD1 J3.04PB7-PD1 PD1 J3.04 DOUT8 GPIO PD7 PD7 J4.09 ~CS (U14) DPOT2_CS PD2 J3.05

R10 (0Ω )

ADC DAC

R9 (0Ω )

Need to Remove

GPIO PE4 PE4 J1.05

Launch Pad

SERIAL

DPOT

USR_SW2/WAKE (R1)

~DRDY/ FSYNC

SPI2_FS_CS PB5 J1.02

SERIAL

GPIO PF0 PF0 J2.04

Tiva C Launchpad Pinout

SERIAL

Interface

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Launchpad Interface Pinout

Interface

ADC: High Resolution• TI ADS1278• 24 bit, up to 111 dB SNR (52kSPS)• 8 Channel, simultaneous sample• Up to 144 kSPS (w/ 106 SNR)• SPI or Frame-Sync Serial Interface• No registers: all settings set by pins

(GPIO)• Power Supplies

– Analog VDD: 5v– Digital Core: 1.8v– IO VDD: 3.3v

• Initialization– Settings set digitally by GPIOs– Jumpers: Clock input selection

and power down selection

ADC

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ADC Sampling Frequency and Resolution• Is a 144 kSPS sampling frequency fast

enough?

• Over-sampling Rate– High-resolution mode: 128– All other modes: 64– 39 dB or 45 dB (HR) of image

Rejectioin

• Is 24-bits of resolution good enough?

– More than high enough resolution

ADC

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ADC Schematic: Main

Common Mode Buffer

Fully Differential ADC Drivers (4ch) Single Ended

ADC Drivers (4ch)

Clock Input Selection Jumper

ADC Shutdown Jumpers

ADC

Fully Differential ADC Driver• OPA1632• Fully differential Audio Op-amp• sets common mode for ADC input• LOW NOISE: 1.3nV/√Hz• Gain Bandwidth: 180MHz• Jumper Option: ground Vin- for

single-ended to differential conversion

• ADC input channels 1-4– Ch.1: Node Pickoff– Ch. 2: Antinode Pickoff– Ch. 3: Ain 3– Ch.4: RTD

• Supply: ±8v• Symmetric and Balanced Layout

ADC

Schematic

Layout

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AC Simulation ResultsAC Response @ fmax = 10 kHzGain = 1 (-6 dB for each differential output)Phase = -3.76o

Corner Frequency: 195.96 kHzGain Peaking: 1.07 dB

ADC

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Transient Simulation Results

Input

Outputs

ADC

ADC Common Mode Voltage Buffer• Buffers 2.5v Common

Mode Voltage from ADC

• Op-amp– OPA350– Low Noise:

5nV/√Hz– Unity-gain stable– Single Supply: 5v

ADC

Schematic

Layout

Voltage Reference• ADR4525• 2.5v• Output Noise (0.1Hz to 10 Hz):

<1μVpp• Initial Output Voltage Error:

0.02%• Input Voltage Range: 3v-15v

– (Running off of regulated 5v Rail)

• Output current:±10mA• TCVOUT: 2ppm/oc• Solder Heat Shift: ±0.02%• Long Term Drift:

25ppm/1000hrs @60oc

ADC

Reference Schematic

Reference Layout

Trace to ADCLength: 17.08 mmWidth: 0.35/0.254mm

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ADC Layout

ADS1278 ADC

Fully Differential ADC Drivers (4ch)

Single-Ended ADC Drivers

Channels 5-8

CH1 Fully Diff

ADC Driver

CH2 Fully Diff

ADC Driver CH3

Fully DiffADC

Driver CH4

Fully DiffADC Driver

Channel Shutdown Jumpers

CLK Selection Jumper

ADC

DAC: High Resolution• ADI AD5754• 16-bit• 4 Channel• Serial clock: up to 30 MHz• Programmable Bipolar/unipolar output

– +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V ( only 5v, ±5 V w/ Vs= ±8 V)

• INL error: ±16 LSB maximum, • DNL error: ±1 LSB maximum• Integrated output and reference buffers

DAC

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DAC Reconstruction Filter

• 2nd Order Sallen-Key Filter: Fc = 15kHz• 1st Order RC: Fc = 15.915 kHz• Amplitude and Phase:• 10kHz: -92o• 160kHz: -258o• Op-amp Selection

• OPA 4140:• 4 channels/package• Noise: 5.1 nV/Hz• Input Bias Current: 0.5pA• Id: 2.0 mA• Vdd max: ± 18 V• SOIC-14

DAC

21DAC Reconstruction Filter: AC Simulation Results

DAC

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DAC Resolution, sampling rate, and DR • Resolution

– 16-bit– 153 μV

• Sampling Rate– Max serial clock frequency = 30 MHz– 24 bit word– Max Sampling Rate ≈ 30MHz/(30cycles/sample) = 1 MSPS

• DR (due to quantization) = (6.02dB/bit)*16bits = 96 dB• Alias Rejection: 61.2 dB (assuming 150 kSPS)

DAC

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DAC Main Schematic

DAC: AD5754 Daisychained

Reconstruction Filters

Output Format Jumper

Quadrature Grounding Options

DAC

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DAC Layout

DAC: AD5754 Daisychained

Reconstruction Filters

Output Format Jumper

Quadrature Grounding Options

DAC

Connection: External and AFE (“Red” Daughterboard) Interface

• SMA connectors for power and data connections• Only 7 connectors total (3 SMA Supplies + 4 USB)

Interface

26Digital Potentiometers: Feed-through Cancellation Tuning

• Digital Potentiometers used to control feedthrough cancellation gains

• 4 channels total • 10kΩ maximum resistance per

channel• Parallel and series resistors allow

adjustment of resistance• Interface: 1 SPI channel, 2 CS• Screw terminals to connect to AFE

Feed Through Cancellation Tuning

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Power Supplies: 1.8v, 3.3v, and 5v• Regulated 1.8v, 3.3v, and 5v supplies• TPS767D318

– Dual Supply: 3.3v and 1.8v LDO– Output Current: 1.0A per regulator– 2% Tolerance – Power –on reset

• unused – maybe I should add this to the reset sources?

– Need 3.3v for digital logic– Need 1.8v for ADC core

• TPS78650– 5.0v LDO– 2% Tolerance – Vin: up to 10v (8v used)

Power Supply

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Layout and Schematic Checks• Schematic

– ERC: Electrical Rules Check: No Major Problems

• Layout– DRC: Design Rules Check No Errors– LVS: Layout vs. Schematic: No

differences

Review

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DFM Review

Review

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Complete Main Schematic

Review

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3D Visualization

Top

Bottom

Missing 3D Models: 90 degree SMA Connectors, jumper headersReview