Gaps and Technical Limitations for Future Packaging ...
Transcript of Gaps and Technical Limitations for Future Packaging ...
Substrate & Package Technology workshop April 22-23, 2014
Gaps and Technical Limitations for
Future Packaging Requirements
Presented by: Dr. W. R. Bottoms
Format for INEMI TWG Chapters
Substrate & Package Technology workshop April 22-23, 2014
The Most Important Part of our Work
Accurately predict Gaps and Showstoppers over a 10 year horizon Recommendation of alternative strategies that
may close these identified Gaps and resolve the difficult challenges before they become showstoppers These tasks are more challenging today than
ever before due to demands for revolutionary new Packaging Solutions
Substrate & Package Technology workshop April 22-23, 2014
Forces Driving this Packaging Revolution
The impending end of Moore’s Law Scaling Dominance of smart phones and tablets in
electronics markets The emergence of the Internet of Things Movement of data, logic and applications to
the Cloud
Each of these factors present new gaps and showstoppers for Packaging Technology
The end of Moore’s Law is coming and Packaging is the only near term solution to
Maintain the pace of Progress
More than Moore is Enabled by Packaging
Interacting with people and environment Non-digital content System-in-Package (SiP)
Beyond CMOS
Information Processing Digital content System-on-Chip (SOC)
Biochips Fluidics
Sensors Actuators
HV Power
Analog RF Photonics
More than Moore : Functional Diversification
65 nm
45 nm
32 nm
22 nm
16 nm
Λ . .
10 nm
Mor
e M
oore
: Sc
alin
g
Baseline CMOS: CPU, Memory, Logic
Substrate & Package Technology workshop April 22-23, 2014
The Technology Drivers are Changing
We are still digesting the change from fixed electronics to mobile devices driving the industry and forcing innovation in:
Rf Components Low power processors Power management ICs
The smart phone and tablets added: Increased processing power and data bandwidth Incorporation of MEMS and a growing number of
sensors
Substrate & Package Technology workshop April 22-23, 2014
Emerging Technology Drivers
There are 2 market driven trends that will force more fundamental change on the industry as they move into position as the technology Drivers.
Rise of the Internet of Things Data, logic and applications moving to the Cloud
Over the next 20 years almost everything will change including the global network architecture and all the components incorporated in it or attached to it.
IoT With Trillions of Sensors
The projected growth is likely to be driven by applications yet to be imagined: Medical Industrial Agricultural ????
Substrate & Package Technology workshop April 22-23, 2014
IP Data Traffic Drives Network Requirements We have seen explosive data traffic growth as both mobile device bandwidth requirement and the number of connected devices expanded rapidly.
Global IP traffic will pass 1.4 Zettabytes (1021) by 2017 Wireless traffic will surpass wired traffic by 2016 Smart phones will grow >80% CAGR The number of mobile-connected devices will exceed the
number of people on earth by the end of this year The Yottabyte era is rapidly approaching
Cisco’s view of near term mobile communications
Substrate & Package Technology workshop April 22-23, 2014
The Driving Forces are Changing
Driver Mainframe computers
Fixed personal computer Mobile Consumer Internet of Things
and the Cloud
Key success Parameters
1. Performance 2. Cost
1. Cost 2. Performance
1. Cost 2. Power 3. Performance 4. Size
1. Cost 2. Power 3. Latency 4. Bandwidth
density 5. Size
Time
Wired Wireless
This requires change in packaging
Substrate & Package Technology workshop April 22-23, 2014
Requirements To Support This View Of The Future
High bandwidth density Low latency Expanded data processing Expanded data storage
All this is needed at no increase in total cost and total Network power. Power and cost/function need >104 improvement over the next 20 years.
Substrate & Package Technology workshop April 22-23, 2014
Major Gaps and Showstoppers
Power requirements (Particularly package related) Thermal management for high thermal density Cost (lowest system cost may not be lowest package cost) Heterogeneous integration (Both device &material) Physical density of Bandwidth Latency
There are many details associated with each of these issues and solutions will require new materials, new package architectures and new packaging processes.
Reducing power requirements and ensuring reliability and power integrity at
the point of use are major Gaps and potential showstoppers for packaging.
What are the potential solutions?
Substrate & Package Technology workshop April 22-23, 2014
Potential Power Solutions Distribute power to the PCB/package at 200V and use it in
integrated circuits at low Drop operating voltage as low as possible (dynamically) Drop operating frequency (dynamically) Move photonics as close to the transistors as possible Increase conductivity with new materials Move components as close together as possible (use the
3rd dimension) Decouple inductance with local high k dielectrics Use ULK k dielectrics for isolation Turn off power not needed for short times (sub-microsecond?)
Substrate & Package Technology workshop April 22-23, 2014
How Can We Reduce Power? Continue Moore’s Law Scaling Reduce leakage currents
– Transistors are less than 10% of IC power today and going down
Reduce on-chip Interconnect power by: – Improved conductor conductivity – Decrease capacitance
Reduce interconnect length Reduce operating frequency Reduce operating voltage
– Voltage regulator per core Reduce high speed electrical signal length
– Move photons closer to the transistors
(new transistor designs)
(new material) (new material) (3D integration) (increased parallelism) (increased parallelism)
(On-package photonics)
Moore’s Law Scaling Is Nearing Its End The advantages of scaling still increase density but cost
and performance no longer Scale with Moore’s Law This vector cannot address the future challenges, Packaging is the
only near term solution
Source: IMEC
Substrate & Package Technology workshop April 22-23, 2014
Speed And Power Advantages Of 3D
3D interconnect decreases path lengths. – For “n” TSV stacked layers, this may reduce global
interconnect path lengths by square root of “n” – Reduction in interconnect length
• Faster circuit speed • Reduced power consumption
– Standby power reduced by 75% compared to PoP and MCP packages
– Smaller physical size – Eventually, lower cost
We have not yet come down the learning curve
Substrate & Package Technology workshop April 22-23, 2014
Qi Wang, Cadence technical marketing group director
“In the last 10 to 20 years, there has been a lot of effort devoted to performance, but we have left a lot of margin on the power side. Why do we keep Vdd at 1 volt? There’s no point. You can drop Vdd to 0.3 or 0.4. People need a safer way to do circuit design.”
Decrease The Operating Voltage
This decreases power requirement but increases need for low cost high k dielectrics
for 3D-TSV stacking
Thermal management is critical due to higher circuit density and lower
operating temperature requirement.
What are the potential solutions?
Substrate & Package Technology workshop April 22-23, 2014
Thermal Management Challenges Finding solutions is not going to be easy
High thermal dissipation density Hot spots Differential thermal expansion Heterogeneous integration
– Both circuit type and material The result is thermal limitations for:
– Bandwidth – Power density – Cost – Reliability
Substrate & Package Technology workshop April 22-23, 2014
Potential Thermal Management Solutions
Don’t make heat in the first place Improved thermal conductivity through new
materials Incorporation of microfluidics, heat pipes Segregation of high temperature components
Microfluidic Cooling Is One Solution
T. Brunschwiler et al., 3D-IC 2009 (IBM)
It works but It is likely to remain too expensive for most applications
Substrate & Package Technology workshop April 22-23, 2014
NanoTubes Have Been Limited By Poor Connection to the Package
Intel and Berkeley developed a technique to adher carbon nanotubes to metal Results are impressive:
– Six-fold increase in heat flow from the metal to nanotubes. – Technique can be integrated into production
Package Cost has not scaled with device cost and now poses
a significant Gap that will become a showstopper with
out major innovation
Substrate & Package Technology workshop April 22-23, 2014
Increase parallelism in package manufacturing
Panel Processing FO-WLP WLP
ParallelismWiring Density2
Substrate & Package Technology workshop April 22-23, 2014
Reduce Processing Steps
Remove package underfill New materials and lower processing
temperature to reduce stress – Reduce CTE differential
Lower modulus materials with improved fracture toughness Improved interfacial adhesion Reduce stress concentration by design
Alchimer metal
Ziptronix DIB
Cu nano-solder
Ultra-conducting CU
Simulation
New ULK dielectrics
Substrate & Package Technology workshop April 22-23, 2014
Specific Gaps for Consideration by the Breakout Groups
Component substrates with improved thermal and electrical conductivity, greater wiring density and incorporation of photonic signals Conductors with higher thermal and electrical
conductivity and lower CTE Low power, high density O to E conversion on
package through sub-wavelength confinement of photon energy Cost reduction in assembly and packaging
Substrate & Package Technology workshop April 22-23, 2014
A Potential Solution: 2.5D Photonic Co-integrated SiP
Silicon Substrate with TSV interconnects and Si Waveguides Photonic engine CMOS logic
Memory controller DRAM DRAM DRAM
DRAM
Power Controller Memory controller
DRAM Flash memory
DRAM
Flash memory Flash memory Flash memory
Photonic/electronic Circuit Board
Electronics, Photonics and Plasmonics on an
SOI Substrate
Multiple voltage regulators to match power delivery to
each component to the work in process
TSV memory stack, direct bonding
interconnect, serdes in controller
PCB with electronic and photonic signals
with embedded components
Large on-package memory cache with serdes in controller
Substrate & Package Technology workshop April 22-23, 2014
Thank You for Your Attention