Galileo Revision 1.11 System Controller for RC4640, RM523X,Galileo GT–64115 System Controller for...

GalileoGT–64115

System Controller for RC4640, RM523X, and VR4300 CPUs

DatasheetRevision 1.11APR 04, 2000

FEATURES

Please contact Galileo Technology for possibleupdates before finalizing a design.

• Integrated PCI system controller for high-performance cost sensitive embedded applications.

• Support the following 32-bit bus CPUs:- IDT RC4640 and RC4650 (in 32-bit mode).- QED RM523X.- NEC/Toshiba VR4300.

• Up to 75MHz CPU bus frequency.

• 3.3V CPU bus interface.

• 64-byte CPU write posting buffer.- 32-bit wide, 16 levels deep.

• CPU address remapping to resources.

• Accepts CPU writes with zero wait-states.

• SDRAM controller:- 3.3V (5V tolerant).- 512MB address space.- Supports 2-way & 4-way SDRAM bank

interleaving.- 256KB-128MB device depth.- Supports 16/64/128-Mbit SDRAM.- 1- 4 banks supported.- 32-bit data width.- Parity support.- Zero wait state interleaved burst accesses at

75MHz.

• Supports VESA Unified Memory Architecture (VUMA) standard.- Allows for external masters access to SDRAM

directly.

• Device controller: - 3.3V (5V tolerant).- 5 chip selects.- Programmable timing for each chip select.- Supports several types of standard

memories (ROM/Flash/SRAM) and I/O.- Up to 160MB address space.- Optional external wait state support.- 8-,16-, and 32-bit width device (and boot)

support.- Support for boot ROMs.- Parity support.

• Four channel DMA controller:- Chaining via link lists of records.- Byte address boundary for source and

destination.- Moves data between PCI, DRAM and devices.- Two 32-byte internal FIFOs allowing two

transfers to take place concurrently.- Alignment of source and destination addresses.- Optional external termination of DMA transfer on

each channel.- Descriptor ownership transfer to CPU.- Fly-By support between DRAM and devices.- Override capability of source, destination, and

record address mapping.

• One 32-bit wide timer/counter.

• Three 24-bit wide timer/counters.

www.galileoT.com [email protected]

GT–64115 System Controller for RC4640, RM523X, and VR4300 CPUs

• 32-bit high-performance PCI 2.1 compliant interface:- 96 bytes of posted write and read prefetch

buffers.- 32-bit PCI master and target operations.- PCI bus speed of up to 66MHz with no wait

states.- Universal PCI buffers.- Operates either synchronous or asynchronous

to CPU clock.- Burst transfers used for efficient data movement.- Doorbell interrupts provided between CPU and

PCI.- Supports flexible byte swapping through PCI

interface.- Synchronization barrier support for PCI side.- PCI address remapping to resources.

• Host to PCI bridge:- Translates CPU cycles into PCI I/O or Memory

cycles.- Generates PCI Configuration, Interrupt

Acknowledge, and Special cycles on PCI bus.

• PCI to Main Memory bridge:- Supports fast back-to-back transactions.- Supports memory and I/O transactions to

internal configuration registers.- Supports locked operations.- Expansion ROM support.

• PCI Power Management compliant.

• PCI Hot-Plug and Compact PCI Hot-Swap capable compliant.- All inputs are 5V tolerant.

• Internal PLL.

• Advanced 0.35 micron process.

Part Number: GT–64115Publication Revision: 1.11

©Galileo Technology, Inc.

No part of this datasheet may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose without the express written permission of Galileo Technology, Inc.

Galileo Technology, Inc. retains the right to make changes to these specifications at any time, without notice.

Galileo Technology, Inc. makes no warranty of any kind, expressed or implied, with regard to this material, including, but not limited to, the implied warranties of merchant-ability or fitness for any particular purpose. Galileo Technology, Inc. further does not war-rant the accuracy or completeness of the information, text, graphics, or other items contained within these materials. Galileo Technology, Inc. makes no commitment to update nor to keep current the information contained in this document.

Galileo Technology, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in Galileo Technology, Inc. products. No other circuit patent licenses are implied.

Galileo Technology, Inc. products are not designed for use in life support equipment or applications in which if the product failed it would cause a life threatening situation. Do not use Galileo Technology, Inc. products in these types of equipment or applications.

Contact your local sales office to obtain the latest specifications before finalizing your product.

Galileo Technology, Inc. 142 Charcot AvenueSan Jose, California 95131Phone: 1 408 367-1400Fax: 1 (408) 367-1401E-mail: [email protected]

Other brands and names are the property of their respective owners.

GT-6411532-bit/75MHz SysADCPU

32-bit/66MHz PCI Bus

Network Other. . .SCSI

32-bit Address/Data Bus

Address/Control Flash I/O. . .SDRAM

2 Revision 1.11


TABLE OF CONTENTS

1. Overview ..................................................................................................................... 111.1 CPU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.2 SDRAM and Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.3 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.4 DMA Engines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.5 Multi-Purpose Pins (MPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2. Pin Information........................................................................................................... 152.1 Pin Assignment Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2 RC4640/RM523X to VR4300 Pins Multiplex Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3. Address Space Decoding.......................................................................................... 243.1 Two Stage Decoding Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.2 PCI Decoding Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.3 Disabling Address Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.4 DMA Unit Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.5 Address Space Decoding Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.6 Default Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.7 CPU PCI Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.8 CPU Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.9 PCI Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.10 DMA PCI Override. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4. CPU Interface.............................................................................................................. 384.1 CPU Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.2 SysAD and SysCmd Buses (9-bit SysCmd Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.3 VR4300 Bus Mode Support (5-bit SysCmd Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.4 Operation of WrRdy* and the Internal Write Posting Queues . . . . . . . . . . . . . . . . . . . . . 464.5 MIPS Write Modes and Write Patterns Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.6 CPU Interface Endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.7 Burst Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.8 CPU Interface Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5. Memory Controller ..................................................................................................... 485.1 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485.2 Connecting the Address Bus to SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545.3 64/128 Mbit SDRAM Connection to Memory Bus Using x4 Devices. . . . . . . . . . . . . . . . 555.4 Programmable SDRAM Bank Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565.5 SDRAM Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575.6 SDRAM Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605.7 Unified Memory Architecture (UMA) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605.8 Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645.9 Programming MPP Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705.10 Memory Controller Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Revision 1.11 3


TABLE OF CONTENTS (Continued)

6. PCI Bus ....................................................................................................................... 726.1 PCI Master Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726.2 PCI Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756.3 PCI Synchronization Barriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806.4 Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806.5 PCI Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816.6 Target Configuration and Plug and Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826.7 Retry Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856.8 PCI Parity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856.9 PCI Bus/Device Bus/CPU Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.10 Universal PCI VRef Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.11 Hot-plug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.12 PCI Power Management Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.13 PCI Interface Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7. DMA Controllers......................................................................................................... 897.1 DMA Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897.2 DMA Channel Control Register (0x840 - 0x84c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907.3 Restarting a Disabled Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957.4 Reprogramming an Active Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967.5 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967.6 Current Descriptor Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967.7 Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967.8 Initiating a DMA from a Timer/Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017.9 DMA Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8. Timer/Counters......................................................................................................... 103

9. Interrupt Controller .................................................................................................. 104

10. Reset Configuration................................................................................................. 105

11. Connecting the Memory Controller to SDRAM and Devices................................ 10711.1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10711.2 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

12. Big and Little Endian ............................................................................................... 11012.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11012.2 Configuring a System for Big and Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

13. Using the GT–64115 Without the CPU Interface.................................................... 112

14. Using the GT–64115 without PCI Interface ............................................................ 113

15. Test Mode ................................................................................................................. 114

16. PLL Application Notes............................................................................................. 11516.1 PLL Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11516.2 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4 Revision 1.11


TABLE OF CONTENTS (Continued)

17. System Configurations............................................................................................ 11617.1 Basic System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11617.2 High Performance System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

18. Register Tables ........................................................................................................ 11818.1 Access to On-Chip PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . 11818.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11818.3 CPU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12418.4 CPU Address Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12418.5 SDRAM and Device Address Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12918.6 SDRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13318.7 SDRAM Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13418.8 Device Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13618.9 MPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13718.10 DMA Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13818.11 DMA Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14118.12 DMA Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14518.13 Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14518.14 PCI Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14818.15 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15518.16 PCI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

19. Pinout Table, 208 pin PQFP ................................................................................... 170

20. DC Characteristics ................................................................................................... 17320.1 DC Electrical Characteristics Over Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . 17420.2 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

21. AC Timing ................................................................................................................. 17721.1 TClk/PClk Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17821.2 Additional Delay Due to Capactive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

22. Packaging ................................................................................................................. 183

23. GT–64115 Part Numbering ...................................................................................... 18523.1 Standard Part Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18523.2 Valid Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

24. Revision History....................................................................................................... 186

Revision 1.11 5


LIST OF TABLES

1. Overview ..................................................................................................................... 11Table 1: DMA Source and Destinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 2: MPP Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2. Pin Information........................................................................................................... 15Table 3: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 4: Pins Used for VR4300 CPU Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3. Address Space Decoding.......................................................................................... 24Table 5: CPU and Device Decoder Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 6: PCI Base Address Register and Device Decoder Mappings. . . . . . . . . . . . . . 26Table 7: CPU and Device Decoder Default Address Mapping . . . . . . . . . . . . . . . . . . . 31Table 8: PCI Function 0 and Device Decoder Default Address Mapping . . . . . . . . . . . 32Table 9: PCI Function 1 (Byte Order Swap) and Device Decoder Default Address

Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Table 10: PCI Address Remapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4. CPU Interface.............................................................................................................. 38Table 11: CPU Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 12: SysCmd Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 13: Address Phase SysCmd [8:0] Encodings (driven by CPU) . . . . . . . . . . . . . . . 39Table 14: Data Identifier SysCmd[8:0] Encodings (driven by GT–64115). . . . . . . . . . . . 40Table 15: CPU Data Identifier SysCmd[8:0] Encodings (driven by CPU). . . . . . . . . . . . 40Table 16: SysCmd Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 17: Address Phase SysCmd[4:0] Encodings (driven by CPU) . . . . . . . . . . . . . . . 44Table 18: Data Identifier SysCmd[4:0] Encodings (driven by GT–64115). . . . . . . . . . . . 45Table 19: CPU Data Identifier SysCmd[4:0] Encodings (driven by CPU. . . . . . . . . . . . . 46

5. Memory Controller ..................................................................................................... 48Table 20: CPU/PCI Address Decoding for 16 Mbit SDRAM . . . . . . . . . . . . . . . . . . . . . . 53Table 21: CPU/PCI Address Decoding for 64/128 Mbit SDRAM. . . . . . . . . . . . . . . . . . . 53Table 22: Supported SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Table 23: CPU SDRAM Performance on Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 24: PCI Read Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 25: GT-64115 Sync Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Table 26: SDRAM Performance Summary PCI Read Accesses. . . . . . . . . . . . . . . . . . . 59Table 27: MPP[3:0] Pin Select Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6. PCI Bus ....................................................................................................................... 72Table 28: DevNum to IdSel Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Table 29: PCI Registers Loaded at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6 Revision 1.11


LIST OF TABLES (Continued)

7. DMA Controllers......................................................................................................... 89Table 30: Location of Source Address, SLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 31: Location of Destination Address, DLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 32: Location of Record Address, RLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 33: Design Information Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Table 34: Source and Destination Data Transfer Examples. . . . . . . . . . . . . . . . . . . . . . 98Table 35: DMA Control Register Bits for Fly-By Indications . . . . . . . . . . . . . . . . . . . . . 100

10. Reset Configuration................................................................................................. 105Table 36: Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11. Connecting the Memory Controller to SDRAM and Devices ............................... 107Table 37: 32-bit SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Table 38: 32-bit Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Table 39: 16-bit Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Table 40: 8-bit Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

12. Big and Little Endian ............................................................................................... 110Table 41: Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Table 42: Bit 12 of the CPU Interface Configuration Register Settings . . . . . . . . . . . . 110Table 43: Bit 12 of the CPU Interface Configuration Register Settings . . . . . . . . . . . . 111Table 44: Configuring for Big and Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

13. Using the GT–64115 Without the CPU Interface ................................................... 112Table 45: CPU-less Pin Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

14. Using the GT–64115 without PCI Interface ............................................................ 113Table 46: PCI-less Pin Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

15. Test Mode ................................................................................................................. 114Table 47: Test Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

18. Register Tables ........................................................................................................ 118Table 48: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

NOTE: The Register Map table specifies the location for each register table.

19. Pinout Table, 208 pin PQFP ................................................................................... 170Table 175: Pinout Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

20. DC Characteristics ................................................................................................... 173Table 176: DC Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173Table 177: DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 173Table 178: PIN Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173Table 179: DC Electrical Characteristics Over Operating Range . . . . . . . . . . . . . . . . . . 174Table 180: 208 PQFP Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

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LIST OF TABLES (Continued)

21. AC Timing ................................................................................................................. 177Table 181: AC Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Table 182: TClk/PClk Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179Table 183: Btyp Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

22. Packaging ................................................................................................................. 183Table 184: 208 PQFP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

24. Revision History....................................................................................................... 186Table 185: Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

8 Revision 1.11


LIST OF FIGURES

2. Pin Information........................................................................................................... 15Figure 1: Pin Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3. Address Space Decoding.......................................................................................... 24Figure 2: Two Stage Address Decoding- Conceptual View . . . . . . . . . . . . . . . . . . . . . 24

Figure 3: CPU-Side Resource Group Decode Function and Example . . . . . . . . . . . . . 27

Figure 4: Device Sub-Decode Function and Example . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 5: Bank Size Register Function Example (16Mbyte Decode) . . . . . . . . . . . . . . 29

Figure 6: CPU Address Remapping to Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4. CPU Interface.............................................................................................................. 38Figure 7: Single Word Read Through CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 8: Four Word Burst Read Through CPU Interface. . . . . . . . . . . . . . . . . . . . . . . 42

Figure 9: CPU Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 10: GT–64115 to VR4300 Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5. Memory Controller ..................................................................................................... 48Figure 11: Memory Controller Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 12: Non-Staggered Refresh Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 13: Staggered Refresh Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 14: Read Modify Write Transaction by the SDRAM Controller . . . . . . . . . . . . . . 51

Figure 15: 64/128 Mbit SDRAM Connection to Memory Bus Using x4 Devices. . . . . . . 55

Figure 16: VUMA Device and GT–64115 sharing SDRAM . . . . . . . . . . . . . . . . . . . . . . 61

Figure 17: Handing the Bus Over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 18: MREQ* Requests from the VUMA Device. . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 19: Waveform Showing Device Read Parameters . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 20: Waveform Showing Device Write Parameters. . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 21: Ready* Extending AccToFirst on Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 22: Ready* Extending AccToNext on Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 23: Extending WrActive Parameter on Write Cycle . . . . . . . . . . . . . . . . . . . . . . . 69

6. PCI Bus ....................................................................................................................... 72Figure 24: PCI Master FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 25: PCI Target Interface “Ping-Pong” FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 26: PCI Target Interface FIFOs Operational Example. . . . . . . . . . . . . . . . . . . . . 78

Figure 27: PCI Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 28: Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7. DMA Controllers......................................................................................................... 89Figure 29: Chained Mode DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Revision 1.11 9


LIST OF FIGURES (Continued)

16. PLL Application Notes............................................................................................. 115Figure 30: PLL Circuit for the GT–64115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

17. System Configurations............................................................................................ 116Figure 31: Basic System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 32: High Performance System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

21. AC Timing ................................................................................................................. 177Figure 33: TClk = PClk Skew Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

22. Packaging ................................................................................................................. 183Figure 34: 208 Lead PQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

23. GT–64115 Part Numbering ...................................................................................... 185Figure 35: Sample Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

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1. OVERVIEWThe GT–64115 provides a single-chip solution for designers building systems around 32-bit bus/64-bit internal MIPS CPUs. The GT–64115 architecture supports several system implementations for different applications and cost/performance points.

The GT–64115 has a three bus architecture:

• A 32-bit interface to the CPU bus.

• A 32-bit interface to the memory and device subsystem.

• A 32-bit PCI interface.

The three buses are de-coupled from each other in most accesses, enabling concurrent operation of the CPU bus, PCI devices, and access to memory. For example, the CPU bus can write to the on-chip write buffer, a DMA agent can move data from SDRAM to its own buffers, and a PCI device can write into an on-chip FIFO, simulta-neously.

1.1 CPU Bus Interface

The GT–64115 SysAD bus allows the CPU to access the PCI and memory/device buses. The SysAD bus proto-col supports byte, sub-word or 32-bit word operations with burst lengths up to eight words. With a maximum fre-quency of 75MHz, the CPU can transfer in excess of 254 Mbytes/sec.

The GT–64115 can automatically determine if the attached MIPS processor is using the 9-bit SysCmd protocol (RC4640, RM523X) or the 5-bit SysCmd protocol (VR4300).

GT–64115 supports CPU address remapping to resources. It can also be configured to operate in the little or big endian mode.

1.2 SDRAM and Device Interface

The GT–64115 SDRAM controller supports a 32-bit wide SDRAM data bus.

The SDRAM controller:

• Supports 16-, 64- and 128MBit SDRAMs.

• Tolerates 3.3V and 5V.

• Works at frequencies up to 75MHz.

• Address up to 512MBytes.

• Allows up to four banks of SDRAM to be connected.

The controller supports two bank interleaving for 16Mbit SDRAMs and two or four bank interleaving for 64 and 128Mbit SDRAMs.

The GT–64115 device controller supports different types of memory and I/O devices. It has the control signals and the timing programmability to support devices such as Flash, EPROMs, FIFOs, and I/O controllers. Device widths of 8-bits,16-bit and 32-bit are supported.

Revision 1.11 11


A Parity generation and checking option is supported for each bank of SDRAM or any other device on the mem-ory bus.

1.3 PCI Bus Interface

The GT–64115 interfaces directly with the PCI bus. It runs at a maximum frequency of 66MHz.

The PCI interface of the GT–64115 can be either a master initiating a PCI bus operation or a target responding to a PCI bus operation. The GT–64115 incorporates 96-bytes of posted write and read prefetch buffers for efficient data transfer between a PCI bus and memory.

The GT–64115 becomes a PCI bus master when the CPU bus or the internal DMA engine initiates a bus cycle to a PCI device. The following PCI bus cycles are supported:

• Memory Read/Write

• Interrupt Acknowledge

• Special

• I/O Read/Write

• Configuration Read/Write

The GT–64115 acts as a target when a PCI device initiates a memory access (or an I/O access in the case of inter-nal registers). It responds to all memory read/write accesses, as well as to all configuration and I/O cycles in the case of internal registers.

It is possible to program the PCI slave to retry all PCI transactions targeted to the GT–64115 until registers ini-tialization is done. The PCI slave performs PCI address remapping to resources.

The GT–64115 contains the required PCI configuration registers. All internal registers, including the PCI config-uration registers, can be accessed from both the CPU bus and the PCI bus. The GT–64115 configuration register set is PC Plug and Play compatible.

The GT–64115 supports PCI Power Management, PCI Hot-Plug and CompactPCI Hot-Swap capable require-ments.

The GT–64115 can also act as a PCI to Memory bridge, even without the presence of the CPU.

1.4 DMA Engines

The GT–64115 incorporates four high performance DMA engines.

Each DMA engine has the capability to transfer data between any of the following sources and destinations.:

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The DMA engine uses two internal 32-byte FIFOs for temporary storage of DMA data. Two internal FIFOs allows two DMA channels to work simultaneously. Each channel utilizes one FIFO. For example, channel 0 reads data from SDRAM into one FIFO while channel 2 writes data from the other FIFO to the PCI bus.

Source and destination addresses can be non-aligned on any byte address boundary.

The DMA channels can be programmed by the CPU bus, or by PCI masters, or without CPU bus intervention via a linked list of records. This linked list is loaded by the DMA controller into the channel’s working set when a DMA transaction ends. The DMA supports increment/decrement/hold on source and destination addresses inde-pendently and alignment of addresses towards source and destination. In addition, the GT–64115 provides an override capability of source/destination/record address mapping.

Four End of Transfer pins, EOT[3:0], act as inputs to the GT–64115 and allow for the ending of a DMA transfer on a certain channel. In case of chained mode, after the transfer is ended, it is possible to transfer the descriptor to CPU ownership which can then calculate the number of remaining bytes in the buffer associated with the closed descriptor.

Fly-by DMA is also supported. This allows data to be transferred directly between two residents on the device/memory bus without having to go into an internal DMA FIFO.

1.5 Multi-Purpose Pins (MPP)

The GT–64115 has eight multi-purpose pins that can be programmed for different functions according to a sys-tem’s configuration. These pins support:

• SDRAM and Device parity

• DMA End Of Transfer

• DMA Request

• VUMA

• Read bypass

Table 2 shows which pin can be used for which function:.

Table 1: DMA Source and Destinations

DMA Source DMA Destinat ion

SDRAM SDRAM, PCI, Device

PCI SDRAM, PCI, Device

Device SDRAM, PCI, Device

Table 2: MPP Pin Summary

Pin Functions

MPP[0] DMA_Req[0]*/EOT[3]/MREQ*/BypsOE*

MPP[1] DMA_Req[1]*/EOT[2]/MGNT*/BypsOE*

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NOTE: By default, MPP[3:0] function as DMA_Req[3:0] and MPP[7:4] functions as EOT[3:0].

MPP[2] DMA_Req[2]*/EOT[1]/TREQ/BypsOE*

MPP[3] DMA_Req[3]*/EOT[0]/BypsOE*

MPP[4] DP[0]/EOT[0]*/MREQ*/BypsOE*

MPP[5] DP[1]/EOT[1]*/MGNT*/BypsOE*

MPP[6] DP[2]/EOT[2]*/TREQ/BypsOE*

MPP[7] DP[3]/EOT[3]/BypsOE*

Table 2: MPP Pin Summary (Continued)

Pin Functions

14 Revision 1.11


2. PIN INFORMATION

Figure 1: Pin Information

VREFPClk

PAD [31:0]CBE [3:0]*

ParFrame*

IRdy*TRdy*Stop*Lock*IDSel

DevSel*Req*Gnt*

PErr*SErr*

Int*Rst*

CPUInterface

SDRAMand Devices

PCI Bus

ValidOut*ValidIn*WrRdy*

Release*SysAD [31:0]SysCmd [8:0]

Interrupt*TClk*

DWr*DAdr[2:0]/BAdr[2:0]DAdr[11:3]BankSel[1:0]AD[0]/BootCS*AD[1]/DevRW*AD[23:2]AD[27:24]/DMA_Ack[3:0]*AD[31:28]/CS[3:0]*SRAS*SCAS*SCS[3:0]*SDQM[3:0]*/Wr[3:0]CSTiming*ALEMPP[7:0]Ready*

Test*

Revision 1.11 15


2.1 Pin Assignment Table

Table 3: Pin Assignments

Pin Name I/O Ful l Name Descript ion

32-bit CPU Interface

Release* I Release Interface Signals to the GT–64115 that the CPU has released the SysAD and SysCmd buses to complete a read request.

WrRdy* O Write Ready The GT–64115 signals that it can accept a CPU write request (i.e. there is room in the write posting FIFO).

ValidIn* O Valid Input The GT–64115 signals that it is driving valid data on the SysAD bus and a valid data identi-fier on the SysCmd bus.

ValidOut* I Valid Output Signals that the CPU is driving valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. A pull-up resistor (4.7KOhm) is required on ValidOut* to VCC.

SysAD[31:0] I/O System Address/Data Bus A 32-bit address and data bus for communica-tion between the CPU and the GT–64115.

SysCmd[8:0] I/O System Command/Data Identi-fier Bus

A 9-bit bus for command and data identifier transmission between the CPU and the GT–64115. Only bits SysCmd[4:0] are used when supporting the VR4300 bus protocol.

Interrupt* I/O Interrupt An “OR” of all the internal interrupt sources on the GT–64115. This pin is also sampled as an input at reset for configuration purposes.

NOTE: This pin is sampled on RESET to con-figure the GT–64115 prior to boot-up, see Section 10. “Reset Configuration” on page 105.

TClk I Clock The input clock to the GT–64115 (up to 75MHz). TClk is used for both the SysAD and Device interface. TClk must be driven for all applications, including those that do not use the CPU bus.

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PCI Bus

Rst* I Reset Resets the GT–64115 to its initial state. This signal must be active for at least 0.5 mS. The period it takes for the PLL to become stable, see Section 16. “PLL Application Notes” on page 115. In the reset state, all PCI output pins are put into HIGH-Z and all open-drain signals are floated.

VREF I PCI Voltage Reference This pin must be connected directly to the 3.3V or the 5V power plane depending on which volt-age level PCI supports.

PClk I PCI Clock This pin provides the timing for the PCI transac-tions. The PCI clock range is between 0 and 66MHz. The PClk cycle must be higher than TClk cycle by at least 1ns. See Section 21.1 “TClk/PClk Restrictions” on page 178 for more information.

PAD[31:0] I/O PCI Address/Data 32-bit multiplexed PCI address and data lines. During the first clock of the transaction, PAD[31:0] contains a physical byte address (32 bits). During subsequent clock cycles, PAD[31:0] contains data.

CBE[3:0]* I/O PCI Command/Byte Enable During the address phase of the transaction, CBE[3:0]* provides the PCI bus command. During the data phase, these lines provide the byte enables.

Par I/O PCI Parity Calculated by the GT–64115 as an even parity bit for the PAD[31:0] and CBE[3:0]* lines.

Frame* I/O PCI Frame Asserted by the GT–64115 to indicate the beginning and duration of a master transaction. Frame* asserts to indicate the beginning of the cycle. While Frame* is asserted, data transfer continues. Frame* deasserts to indicate that the next data phase is the final data phase transaction. GT–64115 monitors Frame* when Frame* acts as a target.

IRdy* I/O PCI Initiator Ready Indicates the bus master’s ability to complete the current data phase of the transaction. A data phase is completed on any clock when both TRdy* and IRdy* are asserted. Wait cycles are inserted until TRdy* and IRdy* are asserted together.

Table 3: Pin Assignments (Continued)


Revision 1.11 17


PCI Bus (Continued)

TRdy* I/O PCI Target Ready Indicates the target agent’s ability to complete the current data phase of the transaction. A data phase is completed on any clock when both TRdy* and IRdy* are asserted. Wait cycles are inserted until TRdy* and IRdy* are asserted together.

Stop* I/O PCI Stop Indicates that the current target is requesting the bus master to stop the current transaction. As a master, the GT–64115 responds to the assertion of Stop* by disconnecting, retrying, or aborting. As a target, the GT–64115 asserts Stop* to retry or disconnect.

Lock* I PCI Lock Indicates an atomic operation that may require multiple transactions to complete. When the GT–64115 is a PCI target, Lock* is sampled on the rising edge of the PClk when Frame* is asserted. If Lock* is sampled asserted, the GT–64115 enters into a locked state and remains in this state until Lock* is sampled deasserted on the following rising edge of PClk.

IDSel I PCI Initialization Device Select Asserted to act as a chip select during PCI con-figuration read and write transactions.

DevSel* I/O PCI Device Select Asserted by the target of the current access. When the GT–64115 is bus master, it expects the target to assert DevSel* within 5 bus cycles, confirming the access. If the target does not assert DevSel* within the required bus cycles, the GT–64115 aborts the cycle. As a target, when the GT–64115 recognizes its transaction, it asserts DevSel* in a medium speed (two cycles after the assertion of Frame*).

Req* O PCI Bus Request Asserted by the GT–64115 to indicate to the PCI bus arbiter that it requires use of the PCI bus.

Gnt* I PCI Bus Grant Indicates to the GT–64115 that access to the PCI bus is granted.

PErr* I/O PCI Parity Error Asserted when a data parity error is detected. This pin features a sustained tri-state output.

SErr* O PCI System Error Asserted when a serious system error (not nec-essarily a PCI error) is detected. This pin fea-tures an open-drain output.



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PCI Bus (Continued)

Int* O PCI Interrupt Request Asserted by the GT–64115 when one of the unmasked internal interrupt sources is asserted. This pin features an open-drain out-put.

SDRAM & Devices

DWr* O SDRAM Write LOW when the GT–64115 writes to the SDRAM.

DAdr[2:0] /BAdr[2:0]

I/O SDRAM Address [2:0] / Burst Address [2:0]

These pins have two functions. In an access to a SDRAM bank, they function as SDRAM address bits. In access to device, they function as the device burst address.

NOTE: These pins are sampled on RESET to configure the GT–64115 prior to boot-up. See Section 10. “Reset Configu-ration” on page 105.

DAdr[11:3] I/O SDRAM Address [11:3] In SDRAM accesses, these pins function as the SDRAM address.

NOTE: This pin is sampled on RESET to con-figure the GT–64115 prior to boot-up. See the Section 10. “Reset Configura-tion” on page 105.

BankSel[1:0] I/O SDRAM Bank Select [1:0] In SDRAM accesses, this pins functions as bank select bits.

NOTE: This pin is sampled on RESET to con-figure the GT–64115 prior to boot-up. See theSection 10. “Reset Configura-tion” on page 105.

SRAS* O SDRAM Row Address Select Asserts to indicate an active ROW address is on the DAdr lines.

SCAS* O SDRAM Column Address Select Asserts to indicate an active COLUMN address is on the DAdr lines.

SCS[3:0]* O SDRAM Chip Selects SDRAM chip selects up to 4 banks.

SDQM[3:0]*/Wr[3:0]*

O SDRAM Byte Enables/Byte Write

In SDRAM accesses, these pins function as data byte enables. In device writes, these pins function as byte write enable indications to the bank bytes.

AD[0]/BootCS* I/O Address/Data [0]/ Boot Chip Select

In the data phase, this pin is data bit 0. In the address phase, it is the boot device chip select. Latching is done via ALE.



Revision 1.11 19


SDRAM & Devices (Continued)

AD[1]/DevRW* I/O Address/Data [1] / Device Read-Write

In the data phase, this pin is data bit 1. In the address phase, it indicates if an access to a device is a read (‘1’) or a write (‘0’). Latching is done via ALE.

AD[23:2] I/O Address/Data[23:2] Multiplexed address and data bus to the SDRAM (data only) and the devices (address and data).

AD[27:24]/DMAAck[3:0]*

I/O Address/Data [27:24] / DMA Acknowledge[3:0]

In the data phase, these pins function as data bits [27:24]. In the address phase, DMA Acknowledges are valid (and should be latched). They need to be qualified with the CSTiming* signal. Latching is done via ALE.

AD[31:28]/CS[3:0]*

I/O Address/Data [31:28] / Chip Select [3:0]

In the data phase, these pins function as data bits [31:28]. In the address phase, Device Chip Selects are valid (and should be latched). The Chip Selects need to be qualified with the CSTiming* signal. Latching is done via ALE.

CSTiming* I/O Chip Select Timing Active for the number of cycles that the device currently being accessed was programmed to in the respective device control register. Used to qualify the CS[3:0]*, BootCS and the DMAAck[3:0]* signals.

ALE O Address Latch Enable Used to latch the Address, BootCS*, CS[3:0]*, DevRW* and DMAAck[3:0]* from the AD bus.

Ready* I Ready A cycle extender. When inactive during a device access, an access will extend until Ready* is asserted.

MPP

MPP[0]: I/O

DMAReq[0]* DMA Request[0] DMA request by external devices to channel 0.

EOT[3] End Of Transfer[3] In DMA transfers, serves as an End Of Transfer indication for channel 3.

MREQ* VUMA Memory Bus Request Memory bus (AD) request by a device to sup-port UMA.

BypsOE* Bypass Output Enable Controls the output enable to, and for, bypass latches/buffers/switches. The bypass can be used when a 32-bit read transaction is exe-cuted from the CPU. The transaction is trans-ferred directly.



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MPP (Continued)

MPP[1] I/O

DMAReq [1]*

DMA Request[1] DMA request by external devices to channel 1.


MGNT* VUMA Memory Bus Grant Asserted in response to MREQ* in case UMA is enabled.

BypsOE* Bypass Output Enable Controls the output enable to, and for, bypass latches/buffers/switches. The bypass can be used when a 32-bit read transaction is exe-cuted from the CPU. The transaction is trans-ferred directly.

MPP[2] I/O



TREQ* VUMA Total Request For UMA operation, it indicates that there is a pending internal request in DRAM and Device interface that requires GT–64115 ownership of AD bus.

BypsOE* Bypass Output Enable Controls the output enable to for bypass latches/buffers/switches. The bypass can be used when a 32-bit read transaction is exe-cuted from the CPU. The transaction is trans-ferred directly.

MPP[3] I/O



BypsOE* Bypass Output Enable Controls the output enable to for bypass latches/buffers/switches. The bypass can be used when a 32-bit read transaction is exe-cuted from the CPU. The transaction will be transferred directly.



Revision 1.11 21


MPP (Continued)

MPP[4] I/O

DP[0] Data Parity[0] SDRAM and Device parity bit corresponds to data driven on AD[7:0].


MREQ* VUMA Memory Bus Request Memory bus (AD) request by a device to sup-port UMA.

BypsOE* Bypass Output Enable Controls the output enable to for bypass latches/buffers/switches. The bypass can be used when a 32-bit read transaction is exe-cuted from the CPU. Transactions will be trans-ferred directly.

MPP[5] I/O



MGNT* VUMA Memory Bus Grant Asserted in response to MREQ* in case UMA is enabled.


MPP[6] I/O



TREQ* VUMA Total Request For UMA operation, it indicates that there is a pending internal request in DRAM and Device interface that requires GT–64115 ownership of AD bus.




22 Revision 1.11


2.2 RC4640/RM523X to VR4300 Pins Multiplex Table

Table 4 shows which pins are used to support the 5-bit SysCmd bus of the VR4300.

The GT–64115 automatically detects which bus mode to be in during the first read transaction.

MPP (Continued)

MPP[7] I/O




TEST Interface

Test* I Test Mode Select: When asserted, GT–64115 enters test mode.

Table 4: Pins Used for VR4300 CPU Bus Mode

RC4640/RM523X VR4300

ValidOut* (pull-up to VCC via 4.7KOhm resistor) PValid* (pull-up to VCC via 4.7KOhm resistor)

Release* PMaster*

ValidIn* EValid*

WrRdy* EOK*

SysAd[31:0] SysAD[31:0]

SysCmd[4:0] SysCmd[4:0]

SysCmd[8:5] Not used (these pins must be pulled down).



Revision 1.11 23


3. ADDRESS SPACE DECODINGThe GT–64115 has a fully programmable address map.

Two address spaces exist: the CPU address space and the PCI address space (see Figure 2.) Both address maps use a two-stage decoding process. First, the major device regions are decoded. Second, the individual devices are sub-decoded.

Figure 2: Two Stage Address Decoding- Conceptual View

SDRAM BankSCS0-or-

SCS1

SDRAM BankSCS3-or-

SCS2

GalileoInternal

Registers

Devices(Multiple

Decoders)

Device Decoders

SCS0Bank

SCS1Bank

SCS2Bank

SCS3Bank

BootCS* CS0* CS1* CS2* CS3*

SDRAM BankSCS0-or-

SCS1

GalileoInternal

Registers

PCIMemory0Window

PCII/O

Window

Devices(Multiple

Decoders)

PCIMemory1Window

Internal Galileo Registers

To PCI Bus

Dev

ice

Bus

(A

DB

us)

Dev

ice

Con

trol

Sig

nals

PCI BaseAddressRegisters

ProcessorDecode

Registers

SDRAM BankSCS3-or-

SCS2

24 Revision 1.11


3.1 Two Stage Decoding Process

The system resources are divided into eight groups:

• SCS[1:0]

• SCS[3:2]

• CS[2:0]

• CS[3] and BootCS

• Internal registers

• PCI I/O

• PCI Memory0/1

Each group can have a minimum of 2Mbytes and a maximum of 256Mbytes of address space. The individual devices in the device groups (for example, SCS[0]) are further sub decoded to 1 Mbyte resolution. Table 5 shows the CPU decode and device sub-decode associations, Table 6 shows the same process for PCI.

Table 5: CPU and Device Decoder Mappings

CPU Decoder Associated Device Sub-Decoders

SCS[1:0] SCS0*

SCS1*

SCS[3:2] SCS2*

SCS3*

CS[2:0] CS0*

CS1*

CS2*

BootCS*/CS3* BootCS*

CS3*

PCI I/O None, accesses decoded for PCI I/O are bridged to PCI I/O transfers.

PCI Memory 0/1 None, accesses decoded for PCI Memory 0/1 are bridged to PCI Memory transfers.

Internal None, decodes to GT–64115 internal registers.

Revision 1.11 25


3.1.1 CPU Side Decoding Process

Decoding on the CPU side starts with the SysAD address being compared to the values in the various CPU Low and High decoder registers. For example, the SCS[1:0] CPU High and Low decoder registers set the address range in which the SCS0* and SCS1* signals are active (i.e. where DRAM banks 0 and 1 are located.) The com-parison works as follows:

1. Bits 31:28 of the SysAD address are compared against bits 10:7 in the various CPU Low decode regis-ters. These values must match exactly. This effectively sets a 256Mbyte “page” for the resource group.

2. Bits 27:21 of the SysAD address are then compared against bits 6:0 in the various CPU Low decode registers. The value of the SysAD bits must be greater than or equal to the Low decode value. This sets the lower boundary for the region.

3. Next, Bits 27:21 of the SysAD address are compared against the High decode registers. The value of the SysAD bits must be less than or equal to this value. This sets the upper boundary for the region.

4. If all of the above are true, the resource group is selected and a subdecode is performed to determine the specific resource.

Once a CPU resource group has been decoded, it must be subdecoded to determine which physical device should be accessed within that group. This decoding is controlled by the device Low and High decode registers. The comparison works as follows:

Table 6: PCI Base Address Register and Device Decoder Mappings

PCI Base Address Register (BAR) Decoder1 Associated Device Sub-Decoders

SCS[1:0]

- BAR 0 at 0x10

SCS0*

SCS1*

SCS[3:2]

- BAR 1 at 0x14

SCS2*

SCS3*

CS[2:0]

- BAR 2 at 0x18

CS0*

CS1*

CS2*

BootCS*/Cs3*

- BAR 3 at 0x1C

BootCS*

CS3*

Internal Registers (Memory)

- BAR 4 at 0x20

None, decodes PCI memory accesses to GT–64115 internal registers.

Internal Registers (I/O)

- BAR 5 at 0x24

None, decodes PCI I/O accesses to GT–64115 internal registers.

Expansion ROM

- BAR at 0x30

None, decodes directly to CS3*

1. This mapping also applies to the swap BARs located in PCI function 1, if enabled.

26 Revision 1.11


1. Bits 27:20 of the SysAD address are compared to the relevant device Low decode registers. The value of the SysAD bits must be greater than or equal to the Low decode value. This sets the lower boundary for the sub-decode region.

2. Bits 27:20 of the SysAD address are then compared against the relevant device High decode registers. The value of the SysAD bits must be less than or equal to this value. This sets the upper bound for the sub-decode region.

3. If all of the above are true, then the specific device is selected and that device is accused.

Examples of the CPU-side decode process are shown in Figure 3 and Figure 4.

Figure 3: CPU-Side Resource Group Decode Function and Example

= = = = >= >= >= >= >= >= >=

31 30 29 28 27 26 25 24 23 22 21 20


Figure 4: Device Sub-Decode Function and Example

= = = = >= >= >= >= >= >= >=

31 30 29 28 27 26 25 24 23 22 21 20


3.2 PCI Decoding Process

Decoding on the PCI side starts by comparing the PCI address to the values in the various Base Address registers (BAR). For example, the SCS[1:0] Base Address register sets the PCI base address range in which the SCS0* and SCS1* signals are active (i.e. where DRAM banks 0 and 1 are located in PCI space.)

The size of the “window” in the PCI space for each Base Address register is set by the Bank Size registers for each Base Address register. The Bank Size sets the address bits for the comparison between the active PCI address and the values in the Base Address registers (see Figure 5).

Figure 5: Bank Size Register Function Example (16Mbyte Decode)

The comparison works as follows:

1. Bits 31:N of the PCI address are compared to bits 31:N in the various Base Address registers. These val-ues must match exactly. The value of N is set by the least significant bit with a 0 in the Bank Size regis-ters (for example, N would be equal to 24 in the example shown in Figure 5.)

2. If the above is true, then the resource group is selected and a sub-decode is performed to determine the specific resource.

Once a resource group has been decoded by a BAR, it must be subdecoded to determine which physical device should be accessed within that group. This decoding is controlled by the Device Low and High decode registers.

NOTE: These registers are the same registers used for CPU-side decoding. This means that the PCI and SysAD memory maps are coupled at the device decoders. Address bits 27:20 (the bits compared by the Device decoders) for any given device overlap in both the PCI and SysAD maps.

The sub-decoding comparison works as follows:

1. Bits 27:20 of the PCI address are then compared to bits in the relevant device Low Decode registers. The value of the PCI address bits must be greater than or equal to the Low Decode value. This sets the lower boundary for the sub-decode region.

2. Bits 27:20 of the PCI address are then compared to the relevant device High decode registers. The value of the PCI address bits must be less than or equal to this value. This sets the upper bound for the sub-decode region.

3. If all of the above are true, then the specific device is selected and that device is accessed.

0 0 0 0 1 1 1

27 26 25 24 23 22 21 20

1 Bank SizeReg

PCI AddressBits

1 1 1 1 1 1 1

19 18 17 16 15 14 13 12

1

= = = = x x x x x x x x x x x x

’=’ values must match exactly’x’ values don’t need to match

Comparisonagainst PCI

address

0 0 0 0

= = = =

31 30 29 28

Revision 1.11 29


3.3 Disabling Address Decoders

CPU interface address decoders can be disabled by setting the Low decoder value higher than the High decoder value.

Device sub-decoder can be disabled by setting the Low decoder value higher than the High decoder value.

PCI address decoders can be disabled by setting the BAR’s corresponding bit in Base Address registers’ Enable to 1.

3.4 DMA Unit Address Decoding

The DMA controller uses the CPU interface address mapping.

Each DMA channel’s source/destination/next-record address is compared to the CPU interface address registers, so each channel can be programmed to transfer data from any source to any destination. For example, it can be programmed to transfer data from SDRAM to PCI and fetch next record from Device.

3.5 Address Space Decoding Errors

When the CPU tries to access an address from the SysAD that is not supported, the GT–64115 latches the address into the Bus Error register. It issues a bus error (over SysCmd[5]) if the access is a read access or an interrupt if it is a read or write access. This feature is especially useful during software debug, when errant code can cause fetches from unsupported addresses.

When an address matches one of the CPU interface address spaces and misses the associated subdecoders, the GT–64115 latches the address into the Address Decode Error register and sets the MemOut bit in the Interrupt Cause register (interrupt is asserted if not masked).

When a PCI access hits in a Base Address register and then misses in the associated subdecoders, the result will be random data returned on a read. Write data is discarded. The MemOut bit in the Interrupt Cause register is also set.

Accesses that miss all of the GT–64115 BAR results in no response from the GT–64115.

When a DMA accesses an unmapped address, DMAOut bit in the Interrupt Cause register is set and the address is latched into the CPU Bus Error register.

NOTE: Address space decoders must not be programmed to overlap; otherwise, unpredictable behavior will result.

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3.6 Default Memory Map

The default CPU memory map that is valid following RESET is shown in Table 7.

The default PCI map and BAR sizing information is shown in Table 8 and Table 9.

Table 7: CPU and Device Decoder Default Address Mapping

CPU DecodeRange and Size

Resource Group

Device DecodeRange and Size

Device Selected

0x0 to 0x00FF.FFFF

16 Mbytes

SCS[1:0] 0x0 to 0x007F.FFFF

8 Mbytes

SCS0*

0x0080.0000 to 0x00FF.FFFF

8 Mbytes

SCS1*

0x0100.0000 to 0x01FF.FFFF

16 Mbytes

SCS[3:2] 0x0100.0000 to 0x017F.FFFF

8 Mbytes

SCS2*

0x0180.0000 to 0x01FF.FFFF

8 Mbytes

SCS3*

0x0.1400.0000 to 0x0.1400.0FFF

4 Kbytes

Internal Reg-isters

No subdecode, access bridged directly to GT–64115 internal regis-ters

Internal Registers

0x1000.0000 to 0x11FF.FFFF

32 Mbytes

PCI I/0 No subdecode, access bridged directly to PCI I/O space

PCI

0x1200.0000 to 0x13FF.FFFF

32 Mbytes

PCI Mem0 No subdecode, access bridged directly to PCI memory space

PCI

0x1C00.0000 to 0x1E1F.FFFF1

~32 Mbytes

1. By default, OX1E00.0000 to OX1E1F.FFFF is allocated to CS[2:0] but is not accessible.The device decoders are not programmed to respond to a hit from this region.

CS[2:0] 0x1C00.0000 to 0x1C7F.FFFF

8 Mbytes

CS0*

0x1C80.0000 to 0x1CFF.FFFF

8 Mbytes

CS1*

0x1D00.0000 to 0x1DFF.FFFF

16 Mbytes

CS2*

0x1F00.0000 to 0x1FFF.FFFF

16 Mbytes

CS[3] and BootCS*

0x1F00.0000 to 0x1FBF.FFFF

12 Mbytes

CS3*

0x1FC0.0000 to 0x1FFF.FFFF

4 Mbytes

BootCS*

0xF200.0000 to 0xF3FF.FFFF

32 Mbytes

PCI Mem1 No subdecode, access bridged directly to PCI memory space

PCI

Revision 1.11 31


Table 8: PCI Function 0 and Device Decoder Default Address Mapping

PCI Function 0 DecodeRange and Size

Resource Group


Device Selected

0x0 to 0x00FF.FFFF

16 Mbytes in Memory Space


8 Mbytes

SCS0*

0x0080.0000 to 0x00FF.FFFF

8 Mbytes

SCS1*

0x0100.0000 to 0x01FF.FFFF


SCS[3:2] 0x0100.0000 to 0x017F.FFFF

8 Mbytes

SCS2*

0x0180.0000 to 0x01FF.FFFF

8 Mbytes

SCS3*

0x1400.0000 to 0x1400.0FFF

4 Kbytes in Memory Space

Internal Reg-isters

No subdecode Internal Registers

0x1400.0000 to 0x1400.0FFF

4 Kbytes in I/O Space

Internal Reg-isters

No subdecode Internal Registers

0x1C00.0000 to 0x1DFF.FFFF


CS[2:0] 0x1C00.0000 to 0x1C7F.FFFF

8 Mbytes

CS0*

0x1C80.0000 to 0x1CFF.FFFF

8 Mbytes

CS1*

0x1D00.0000 to 0x1DFF.FFFF

16 Mbytes

CS2*



CS[3] and BootCS*


12 Mbytes

CS3*


4 Mbytes

BootCS*


16 Mbytes (uses CS[3] and BootCS* size register)

PCI

Expansion ROM

No subdecode. This decoder is used only during PC BIOS initialization.

CS3*

Table 9: PCI Function 1 (Byte Order Swap) and Device Decoder Default Address Mapping


Resource Group


Device Selected

0x0 to 0x00FF.FFFF



8 Mbytes

SCS0*

0x0080.0000 to 0x00FF.FFFF

8 Mbytes

SCS1*

32 Revision 1.11


3.7 CPU PCI Override

By default, CPU interface supports 512Mbyte PCI memory address space (256Mbyte on PCI Mem0, 256Mbyte on PCI Mem1). The CPU PCI override feature enables larger PCI memory address space.

The CPU configuration register includes two PCI override bits. This bit pair controls whether the PCI window is:

• 2Gbytes.

• 1Gbyte.

• The complement of all other address windows.

• The default.

When PCI override bits are set to 01, if bits[31:30] of SysAD matches bits [10:9] of PCI Mem0 Low decode address register, the transaction is directed to PCI Mem0. This effectively sets a 1Gbyte window to PCI. If Bits[31:30] do not match bits [10:9] of PCI Mem0 Low decode address register, address is compared to all other address decode registers.

When PCI override bits are set to 10, if bit[31] of SysAD matches bit [10] of PCI Mem0 Low decode address register, the transaction is directed to PCI Mem0. This effectively sets a 2Gbyte window to PCI. If bit[31] does not match bit [10] of PCI Mem0 Low decode address register, address is compared against all other address decode registers.

When PCI override bits are set to 11, address is first compared to all address decode registers. If there is no match in any of them, the transaction is directed to PCI Mem0. This effectively sets a PCI window size of 4Gbyte, minus the sizes of all devices.

NOTE: If PCI override bits are set to 11 and there is not match with the Decode register addresses, there will be no indication of a bad CPU address. The CPUOut interrupt is never be asserted.

0x0100.0000 to 0x01FF.FFFF


SCS[3:2] 0x0100.0000 to 0x017F.FFFF

8 Mbytes

SCS2*

0x0180.0000 to 0x01FF.FFFF

8 Mbytes

SCS3*



CS[3] and BootCS*


12 Mbytes

CS3*


4 Mbytes

BootCS*

Table 9: PCI Function 1 (Byte Order Swap) and Device Decoder Default Address Mapping


Resource Group


Device Selected

Revision 1.11 33


3.8 CPU Address Remapping

The GT–64115 supports address remapping from CPU.

The resources that can be addressed by the CPU are:

• The SDRAM banks (SCS[1:0], SCS[3:2])

• The devices (CS[2:0], CS[3] & BootCS)

• PCI IO

• PCI Memory0/1

Each such resource has a Remap register associated with it. These registers are listed in the Register Section as part of Processor Address Space, see Section 18.4 “CPU Address Decode” on page 124.

Each Remap register is 11 bits wide.

An address presented on the SysAD bus by the CPU is decoded using the following steps:

1. Address bits [31:21] are checked for a hit in the CPU decoders.

2. Assuming there is a hit in the CPU decoders, bits 20:0 are left unchanged.

3. Bits[31:21] are remapped as follows; going from the MSB to LSB of the HIT address, any bit found matching to its respective bit in the LOW decode register’s bits [10:0] will cause the corresponding bit in the remap register to REPLACE the original address bit.

4. Upon first mismatch, all remaining LSBs of address bits[31:21] are unchanged.

5. Address bits [27:20] of the remapped address are checked to be a hit in the Device decoders.

6. Assuming there is a hit in the Device decoders, the HIT address is transferred to the resource.

See Figure 6 outlining this address remapping procedure.

NOTE: Although the DMA controllers use the CPU Address Decoders for decoding source and destination addresses, the source and destination addresses will NEVER be remapped by the CPU address remap-ping registers. The DMA controllers do not use the CPU Address Decoders for decoding source and destination addresses when the PCI override feature is used, see Figure 3.10 on page 37.

34 Revision 1.11


Figure 6: CPU Address Remapping to Resources

3.8.1 Writing to Decode Registers

When a LOW decode register is written, the associated remap register is written with the same value, simulta-neously. When a remap register is written, only its contents are affected.

Following RESET, the default value of a remap register is equal to its associated LOW Decode register. Unless a specific write operation to a remap register takes place, a 1:1 mapping is maintained. Also, changing LOW Decode register’s contents automatically returns its associated space to a 1:1 mapping. This allows for backward software compatibility with other Galileo Technology devices such as the GT-64111.

. . .

= = = = >= >= >= >= >= >= >=

31 30 29 28 27 26 25 24 23 22 21 20


3.9 PCI Address Remapping

The PCI slave interface has the ability to remap addresses of PCI transactions to memory using PCI remap regis-ters. These seven registers correspond to the following PCI Base Address registers:

• SCS[1:0]

• SCS[3:2]

• CS[2:0]

• CS[3] & BootCS

• Swapped SCS[1:0]

• Swapped SCS[3:2]

• Swapped CS[3] & BootCS

These registers are listed in the Register Section as part of PCI Internal registers, see Section 18.14 “PCI Inter-nal” on page 148. Each MAP register is 32-bits wide. Each Remap register is 32-bits wide, where bits [12:0] are Read Only.

When an address is presented on the PAD lines, the address decoder in the PCI slave will compare the PCI address to its base/size registers. If there is a HIT in one of the seven Base Address registers listed above, the address will undergo remapping in accordance to the right remap register in the non-masked address bits (by size register). An example of this is summarized in Table 10.

NOTE: The size register is programmed to 0x03FF.FFFF. This indicates that this BAR requires a hit in the six MSB (bits 31:26) bits of the PCI address for there to be a hit in the BAR. Therefore, the PCI address 0x1DXX.XXXX is a hit in a BAR programmed to 0x1FXX.XXXX as bits 31-26 of both of these addresses are 0b0001.11.

Then, according to the Remap register, these same bit locations are remapped to 0b001111. The rest of the PCI address bits (i.e. [25:0]) remain unchanged. This means that the final PCI slave address will be 0x3D987654.

3.9.1 Writing to Decode Registers

When a BAR register is written, the associated remap register is written, simultaneously.

When a remap register is written, only its contents are affected. Following RESET, the default value of a remap register is equal to its associated BAR decode register. Unless a specific write operation to a remap register takes place, a 1:1 mapping is maintained.

Table 10: PCI Address Remapping Example

PCI address 0x1D98.7654

SCS[1:0] BAR 0x1F00.0000

SCS[1:0] Size 0x03FF.FFFF

SCS[1:0] Remap Register 0x3F00.0000

Remapped PCI Address Presented to SDRAM 0x3D98.7654

36 Revision 1.11


Changing a BAR register’s contents automatically returns its associated space to a 1:1 mapping. This allows for backward software compatibility with other Galileo Technology devices such as the GT-64111.

In some applications, the operating system might reprogram the Base Address registers after the Remap registers were already programmed by the local driver. In such a case, the 1:1 mapping due to the BARs reprogramming is not desired.

NOTE: If bit[16] of the PCI Cmd register is set to 1, writing to the BARs will not result in the simultaneous writing of the value to the corresponding Remap registers.

3.10 DMA PCI Override

By default, the DMA controller uses CPU interface address decoding, as explained in Section 3.4 “DMA Unit Address Decoding” on page 30. However, the DMA controller also supports direct access to the PCI bus. Direct access to the PCI bus bypasses this address decoding.

In each of the four DMA channel control registers, there are three PCI override bits for source/destination/next-record address. Each bit controls whether the address should be directed to PCI memory space or run through CPU interface address decoding. For further information, see Section 18.11 “DMA Channel Control” on page 141.

Revision 1.11 37


4. CPU INTERFACEThe GT–64115 SysAD bus interface allows the CPU to gain access to the GT–64115’s internal registers, PCI interface, and the memory/device bus (AD bus). The SysAD bus supports accesses from one to 32 bytes in length.

The SysAD bus on the GT–64115 is a slave-only interface. The GT–64115 never masters the SysAD bus.

4.1 CPU Interface Signals

The CPU interface incorporates the following signals:

The SysAD bus is synchronous with respect to TClk and is locked with respect to the AD bus. The SysAD may be asynchronous with respect to the PCI bus or locked to the PCI bus for lower synchronization latency.

4.2 SysAD and SysCmd Buses (9-bit SysCmd Mode)

The SysAD and SysCmd bus protocol implemented by the GT–64115 is completely compatible with the 32-bit Orion bus protocol used by the IDT RC4640 and RC4650 and QED RM532X CPUs. The GT–64115 extends this protocol to support bursts less than eight 32-bit words. These extensions can be used by DMA engines on the SysAD bus for more efficient use of the interface.

The SysAD[31:0] bus is a 32-bit multiplexed address/data bus. The CPU drives address for a single cycle then either drives data (for a write) or floats the bus in anticipation of returned data (for a read).

Table 11: CPU Interface Signals

Signal Description

SysAD[31:0] Master Address/Data.

This bus transfers multiplexed address/data.

SysCmd[8:0] Master Port Command.

The SysCmd bus transfers information about the access (read/write, size) and the data identifier (good/bad, last word.) Only SysCmd[4:0] are used in VR4300 mode.

ValidOut* Indicates that the CPU is driving valid address/data/command on the CPU bus.

ValidIn* Indicates that the GT–64115 is driving valid data/data identifier on the CPU bus.

WrRdy* Indicates that the GT–64115 is capable of accepting a write transaction up to eight words in length.

Release* Indicates to the GT–64115 that the CPU will not drive the SysAD after the current clock cycle. For example, the CPU is floating the SysAD and SysCmd bus for completion of a read.

38 Revision 1.11


The SysCmd[8:0] bus conveys information about the transaction such as the direction (read/write), the size (byte, short, word, multi-word) and the status of the data (good/bad/last.) SysCmd is driven by the CPU during the address phase of a transaction (with direction/size information) and for the duration of a write (with good/bad/last information.) The GT–64115 drives SysCmd during the data phase of read transactions.

The encodings, and a summary of their usage, for SysCmd[8:0] are shown in tables Table 12, Table 13, Table 14, and Table 15.

NOTE: Many encodings are not defined; these encodings are reserved and must not be used. A summary of bit usage is shown below.

Table 12: SysCmd Bit Summary

SysCmd Bit Function

SysCmd[8] 0 = Transaction information (read/write/size)

1 = Data information (good/bad/last)

SysCmd[7] Indicates last data/not last data during data cycles.

Must be ‘0’ for address cycles.

SysCmd[6] 0 = Read transaction (during address cycles)

1 = Write transaction (during address cycles)

Must be ‘0’ for data cycles.

SysCmd[5] Indicates error status for data cycles.

Must be ‘0’ for address cycles.

SysCmd[4] CPU mode select

0 - VR4300 mode

1 - RC4640/RM523X mode

SysCmd[3:0] Encoded to indicate size of the transfer.

Table 13: Address Phase SysCmd [8:0] Encodings (driven by CPU)

SysCmd[8:0] Encoding1Command Mnemonic Command Description8 7 6 5 4 3 2 1 0

0 0 0 0 1 1 0 0 0 RdByte Read a single byte

0 0 0 0 1 1 0 0 1 RdShort Read 2 bytes

0 0 0 0 1 1 0 1 0 RdTriByte Read 3 bytes

0 0 0 0 1 1 0 1 1 RdWord Read 4 bytes (single word)

0 0 0 0 1 1 1 X X Rd2Words Read 2 words (8 bytes) in a burst

0 0 0 0 1 0 X X 0 Rd4Words Not supported.

0 0 0 0 1 0 X X 1 Rd8Words Read 8 words (32 bytes) in a burst

0 0 1 0 1 1 0 0 0 WrByte Write a single byte

Revision 1.11 39


0 0 1 0 1 1 0 0 1 WrShort Write 2 bytes

0 0 1 0 1 1 0 1 0 WrTriByte Write 3 bytes

0 0 1 0 1 1 0 1 1 WrWord Write 4 bytes (single word)

0 0 1 0 1 1 1 X X Wr2Words Write 2 words (8 bytes) in a burst

0 0 1 0 1 0 X X 0 Wr4Words Not supported.

0 0 1 0 1 0 X X 1 Wr8Words Write 8 words (32 bytes) in a burst

1. ‘X’ denotes “don’t care” but ‘X’ signals must be driven to a valid 0/1.

Table 14: Data Identifier SysCmd[8:0] Encodings (driven by GT–64115)


1 0 0 E X X X X X REOD Indicates last valid data in a burst.

E = 0 Data is good

E = 1 Data is erroneous

1 1 0 E X X X X X RD Indicates valid data within a burst.

E = 0 Data is good


1. ‘X’ denotes “don’t care” but ‘X’ signals are driven to a valid 0/1 by GT–64115.

Table 15: CPU Data Identifier SysCmd[8:0] Encodings (driven by CPU)


1 0 1 E X X X X X WEOD Indicates last valid data in a burst.

E = 0 Data is good


1 1 1 E X X X X X WD Indicates valid data within a burst.

E = 0 Data is good


Table 13: Address Phase SysCmd [8:0] Encodings (driven by CPU) (Continued)


40 Revision 1.11


4.2.1 SysAD Read Protocol

SysAD read occurs in a three phase, burst read:

1. The address phase. Information is driven on the SysAD bus and command information is driven on SysCmd.

2. The mid-burst data phase. The GT–64115 drives data on the SysAD bus and a data identifier on SysCmd. Only used for transactions longer than 32 bits

3. The last data phase. The GT–64115 drives data on the SysAD bus and a read end-of-data (REOD) data identifier on SysCmd.

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Galileo Revision 1.11 System Controller for RC4640, RM523X,Galileo GT–64115 System Controller for...

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