Fuzzy Logic Arbiters for Fuzzy Logic Arbiters for Multiple-Bus Multiprocessor Multiple-Bus Multiprocessor Systems Systems by by Hassan B. Hassan B. DiabDiab,, Senior Mem. IEEE

Presented ByPresented By Ali Rıza KONANAli Rıza KONAN Bogazici UniversityBogazici University

Computer Eng. Computer Eng. DepartmentDepartment

FallFall 2004 2004

Outline Introduction

Interconnection Networks Fuzzy Logic

Implementation System Configuration Assumptions Steps for fuzzy arbiters

Simulation Description I/O interface for the simulator Flowchart / Execution steps

Comparative Results Conclusions

INTRODUCTIONINTRODUCTION

Introduction:Interconnection Networks (INs)

Sharing a set of main memory modules and, possibly I/O devices

Sharing capability for INs between the processor and mem. modules between the processor and I/O subsystem

Types of INs Single bus architecture Multiple-bus multiprocessor organization Crossbar configuration Multistage Interconnection Networks (MINs)

Introduction: Fuzzy Logic

Proved to be an innovative and successful design methodology Simplicity Sensitivity Robustness Easy optimization

Typical “fuzzy goods” in control systems Washing machines Air conditioners Cameras, camcorders etc. Audio systems

Why not use for INs?

Introduction: Fuzzy Logic (Cont’d)

Generalization of the classical/crisp set The crisp set

dichotomise the individuals into two groups: members and nonmembers

sharp, unambigious distinction btw. members and nonmembers

The fuzzy set boundaries are vague the transition from member to nonmember

appears gradual rather than abrupt

Characteristic function of a crisp set assigns a value of either 1 or 0 discrimination btw. members and

nonmembers of the crisp set

Characteristic function of a fuzzy set the values assigned to the elements fall

within a specified range values indicate the membership grade of an

element larger values denote higher degree of set

membership

Introduction: Fuzzy Logic (Cont’d)

Introduction: Fuzzy Logic (Cont’d)

Let X denote a universal set. Then, the membership function by which fuzzy set is usually defined has the form:

fA: X [0,1]

For ex., we can define a possible membership function for the fuzzy set of real numbers close to 0 as follows:

The presented paper introduces a novel methodology in the use of fuzzy logic arbiters for multiple-bus multiprocessor systems Inputs of the arbiters: the requests from the

conflicting sources, i.e. Procesors Output: the selected resource appropriate membership func. for fuzzy

arbiters such rules to maximize the acceptance

probability of the processors regarding fairness

Introduction:Fuzzy Logic in Multiproc. Conf.

IMPLEMENTATIONIMPLEMENTATION

Implementation:System Configuration

Two-stage arbitration scheme

First stage: memory conflicts are resolved by m 1-of-N arbiters,

one for each memory module each arbiter selects one processor from from several

requesting processors to the same memory module fixed priority and fuzzy scheme

Second stage: the processor requests selected by the memory

arbiters are then allocated a bus by using a b-of-m arbiters

Implementation:System Configuration (Cont’d)

Performance metrics of the multiprocessor system: EMBW (Effective Memory Bandwidth): average number of the memory

modules (MMs) busy in a cycle Acceptance probability of a processor: the probability that the request from

that processor will be accepted in any cycle

Implementation:System Configuration (Cont’d)

A new memory request is placed at the beginning of each cycle by idle processors with a probability R, where R is the average number of new requests generated per cycle by each processor

Processors issue requests at the beginning of a cycle

Processors’ requests are uniformly distributed over all MMs

Denied processors resubmit their request in the following memory cycle

Implementation:Assumptions

During a cycle, the requests to each MM are resolved on the basis of the processor priority the processor with the highest priority is chosen

from those currently requesting the MM priority is dynamic and implemented in the fuzzy

arbiters buses are assigned to those selected processors

which have higher priorities and the other processors’ requests are resubmitted the next cycle

Implementation:Assumptions (Cont’d)

A maximum of three simultaneous requests to the same MM is allowed in a cycle to limit the number of inputs to the Fuzzy

Inference (FI) system to reduce the number of rules used any additional requests to the same MM are

discarded and a new one is generated in the same memory cycle. It is shown later that this has a negligible effect on the results.

Implementation:Assumptions (Cont’d)

The fuzzy logic is implemented in the memory arbiters

A fixed priority scheme is implemented in the bus arbiters

The current acceptance rate of each processor is calculated in each cycle and used as input to the fuzzy arbiters

Implementation:Assumptions (Cont’d)

Step 1.Fuzzify Inputs : The first step is to take the inputs and

determine the degree to which they belong to each of the appropriate fuzzy sets via membership functions

Membership function a curve that defines how each point in the input

space is mapped to a membership value (or degree)

Inputs in this case are chosen to be the current acceptance probability of each processor

Implementation:Steps for Fuzzy Arbiters

Implementation:Steps for Fuzzy Arbiters (Cont’d) The input is a crisp numerical value limited to the

universe of discourse which is in this case [0,1] Three membership functions are defined for each

input; low, medium, and high

Step 2.Apply Fuzzy Operator : Once the inputs have been fuzzified, we know

the degree to which each part of the antecedent has been satisfied for each rule

A set of rules have been defined for a fuzzy arbiter of two inputs and three inputs

For ex., if two processors request the same memory module, then the current acceptance rate is calculated and used as inputs to the fuzzy arbiter

The output is then the processor selected

Implementation:Steps for Fuzzy Arbiters (Cont’d)

Implementation:Steps for Fuzzy Arbiters (Cont’d)The listing of the rules for a two-input system is shown below:

AP1, AP2: current acceptance rates of input 1 and input 2

Implementation:Steps for Fuzzy Arbiters (Cont’d)

Any number of well-defined methods can fill in for the AND operation or the OR operation

AND operator is used to represent the minimum method

(fuzzy membership values are 0.6 and 0.8, respectively)

Step 3. Apply Implication Method :

The input for the implication process is a single number given by the antecedent, and the output is a fuzzy set

Implication is implemented in each rule

Various methods are used and they are the same functions that are used by the AND method:

min (minimum), which truncates the output fuzzy set prod (product), which scales the output fuzzy set.

Implementation:Steps for Fuzzy Arbiters (Cont’d)

Step 4. Aggregate All Outputs : Includes all the singletons by using the

maximum method

Step 5. Defuzzify : As the aggregation of a fuzzy set includes

many singletons each obtained from the rules, defuzzification is needed to obtain the crisp value from the set

The defuzzification method used is Weighted Average Method

Implementation:Steps for Fuzzy Arbiters (Cont’d)

SIMULATION SIMULATION DESCRIPTIONDESCRIPTION

Simulation Description:Simulator

A simulator for a multiple-bus system was developed using Visual C++

A system with N processors, m memories, and b buses

Each processor have a dynamic priority controlled by a fuzzy logic controller

Inputs of the program # of processors, N # memory modules, m # of buses, b Request rate of processors, [0…1] Priority scheme used (fixed or fuzzy) Max. # of simultaneous proc. requests # of cycles to be simulated

Outputs of the program Prob. of acceptance of requests for each

processor Overall system BW

Simulation Description:I/O interface

1-) For each processor Pi, select1 and select2

var.s are initialized to 0 select1 & select2 both 1 means that processor

has been granted the requested MM and the bus

2-) Check Pi’s state if it’s in the wait state, then check the next.

otherwise, generate a random MM request if total # of requests to that is greater than

max. # of simultaneous access (MNSA), then regenerate another MM request.

after placing the request, change the processor to the wait state and increment the # of MM requests made by this processor (nreq) by 1

Simulation Description:Execution Steps

3-) For each Mj build a list containing the processor numbers

that requesting this MM select the highest priority processor from the list

using the fuzzy model and set select1=1

4-) Build a list which contains processor numbers having select1=1, and for each

bus select the highest priority processor from the list grant this processor the memory transfer by

setting select2=1

Simulation Description:Execution Steps (Cont’d)

5-) For each processor Pi if both select1 & select2 equals 1, then

increment EBMW by 1 if the request is accepted in the same

cycle, then increment accept by 1 accept: # of accepted processors in the

same cycle used to calculate current acceptance rate

later set processor state as idle set select1 and select2 as 0

Simulation Description:Execution Steps (Cont’d)

Simulation Description:Execution Steps (Cont’d)6-) Increment simulation clock by 1

Go to step 1 in the vase of # cycles simulated is less than the specified # by the user

7-) Calculate perf. metrics as follows

COMPARATIVECOMPARATIVE RESULTSRESULTS

Comparative Results:Tabulated Results 1

Comparative Results:Tabulated Results 2

Comparative Results:Fixed Priority Scheme

Comparative Results:Fuzzy Scheme

Comparative Results:Acceptance Rate for Fixed & Fuzzy

Acceptance rate for fixed and fuzzy arbiters (16x16 system, R = 1)

CONCLUSIONSCONCLUSIONS

Conclusions Implementation of a fuzzy inference system in

the arbiters of multiple-bus multiprocessor system has been introduced

Results of simulation runs using fuzzy arbiters are reported and compared to fixed priority schemes

It is shown that there is an increase in the average acceptance rate of processors

Also, in fuzzy scheme, there is a nearly uniform distribution of the acceptance rate

Results show close agreement with already published simulation results in literature

References Diab, H.B., Fuzzy Logic Arbiters for Multiple-Bus

Multiprocessor Systems, 2004 IEEE Transactions on Systems, Man, and Cybernetics Part C: Applications and Reviews, 2004 August

K. Hwang and F. Briggs, Computer Architecture and Parallel Processing. New York: McGraw-Hill, 1985

L. A. Zadeh, “Fuzzy sets,” Inf. Contr., vol. 8, no. 3, pp. 338–353, June 1965

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