Future Memory System Seminar

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ABSTRACTThe improvement of the computer system performance is constrained by the well-known memory wall and power wall. It has been recognized that the memory architecture and the interconnect architecture are becoming the overwhelming bottleneck in computer performance. Disruptive technologies, such as emerging non-volatile memory (NVM) technologies, 3D integration, and optical interconnects, are envisioned as promising future memory and interconnect technologies that can fundamentally change the landscape of the future computer architecture design with profound impact. This invited survey paper gives a brief introduction of these future memory and interconnect technologies, discusses the opportunities and challenges of these new technologies for future computer system designs.

INTRODUCTIONThe evolution of the computing landscape is leading to a dichotomy of computers into relatively simple mobile devices, and large server farms, also called warehousescale computers. Mobile devices are expected primarily to access a web-based information infrastructure, with most intensive computing relegated to servers housed in large datacenters. It is clear that the primary challenge to scaling such computing systems into the exascale realm is the ecient supply of large amounts of data to hundreds or thousands of compute cores. Increasing socket, core, and thread counts, combined with large datasets in modern scientic and commercial workloads will exert extreme pressure on the memory system. Further, these demands will have to be satised under increasingly constrained power budgets, while utilizing increasingly unreliable components. The memory interface will thus be operating under challenging conditions, and should be designed carefully in order to provide low latency, high bandwidth, low power, strong fault-tolerance, and extreme scalability. Consider the following technological trends that will strongly inuence the design of the next generation of memory systems.