Future Heterogeneous Device and System Process … · Future Heterogeneous Device and System...
Transcript of Future Heterogeneous Device and System Process … · Future Heterogeneous Device and System...
Future Heterogeneous Device and System
Process Technology: towards
Zero intrinsic variability and Zero Power
Simon Deleonibus,
Université Grenoble Alpes, CEA, Leti
MINATEC Campus, 38054 Grenoble, Franceemail address: [email protected]
Zero Intrinsic Variability and Zero Power :
necessity for the future in the realm of HeterogeneityIn 2025, World Gross Domestic Product will depend by 25 % on
Information and Communication Technologies (ICT): pervasion of ICT in
healthcare, communication, transport , energy, food, ...(MGI Disruptive technologies Full report May2013, ACEEE)
Exploding demand for information exchanges (zettabyte 10 21 in 2017)
(www.Cisco) : IoT !!
Energy Efficiency and materials scarcity: major future questions to ICT/
ecological footprint
@ materials, active devices, functional and system levels.
Main market drivers based on Nomadic, Autonomous, Heterogeneous,
High Performance and Ultra Low Power Systems => Appeal Zero Power
Dimensional scaling sub 10 nm and materials low dimensionality
=> Appeal Zero Intrinsic Variability.
3
Since 2005: A complete set of research platforms…
interacting daily with R & D platforms worldwide (ST Crolles, IBM Albany, …)
CEA LETI (1800 CEA researchers, 300 M€ budget, filing 300 patents/year )collaborating in MINATEC campus (3000 researchers)
300mmCMOS Integration
& adv. modules
200mm‘CMOS’ new concepts
& Beyond CMOS
More Than Moore200mm
NanoscaleCharacterization
Design
MicroTechsfor bio
Education
Outline•Introduction
•Issues for scaling Silicon and thin films devices: towards Zero Intrinsic Variability
• Role of Fully depleted devices towards Low Power /High Perfomance
• Aiming at Zero Intrinsic Variability@sub10nm level and new active materials integration (approaching molecular and atomicdimensions)
•Heterogeneous Co-integration of scalable (More Moore) and diversification (More than Moore) devices .
• New opportunities for Computing and Sensing
• 3D as a strong asset at the functional and system levelstowards Zero Power
•Conclusion
LETI, ST Micro, SOITEC : O.Weber et al., VLSI Symp 20 14 , IEDM 2008; C.Fenouillet-Béranger et al., IEDM 2007, VLSI Symp 2010 V.Barral et al., IEDM2007 ; S. Morvan et al, VLSI Sy mp 2011; R. Coquand et al. VLSI, Symp 2011; S.Barraud et al, VLSI Symp 2013
14 nm node 300mm wafers TSi=6nm
TBox=20nm
Energy efficient FDSOIThin Films Undoped channelsIdeal Electrostatic control
*Record-high VT matching performance (AVT=1mV.µm)*Low Power and High performance -strainengineering (Tsi=6nm)( bi-ax, CESL, ESD) => outperfroms bulk(leakage, delay,Pwxdelay)* Scalability from 28 to 8 nm proven
LG=8nm
1000 wafers
FDSOI outperforms state of the art bulk counterpartIncreased energy efficiency
Novathor® platform : 35% performance increase;
(28 nm node) 25% lower power consumption; simpler design
R. Wilson et al, ISSCC 2014; E. Beigne, DATE 2013
DSP S=1mm2
5 Million MOST
SOI: Threshold voltage thickness dependence
Valid for any Thin Film Channel ( FDSOI, FinFET, Trigate,…)V
T(V
)
Tsi(nm)
222
2
×=∞
chen T
n
mE
hπQuantum confinement:
111 2
2ox
chAffbT C
TqNVV ++= φFully depleted channel:
Bulk or PD SOI like
FDSOI
Quantum confinement
LETI: J.Lolivier et al, ECS Spring 2002
AnyThin film channel will follow the sameregimes if Fully Depleted (space charge region> thickness):-Strong dependence of VT on TSi (Tch)-Quantum confinement@ ultra thin film
(degeneracy / band splitting)
N+ poly gate
Mobility degradation @ thinfilms – multi subbandrepopulation
Multigate: relaxes on channelfilm thickness scaling.
Tunnel FETs : towards sub 0.5V VDD with steep subthreshold slopes
BOx
S D
GP mode N mode
Vth
VG
Log ID
IOFF
ideal switch
TFETMOSFET
Vth
VG
Log ID
IOFF
ideal switch
TFETMOSFET
L=100nm T=300K
Experimental demonstrationof Tunnel FET operation
⇒ down to 33mV/dec
Co-integration w. CMOS
min. 60mV/dec
F.Mayer et al., IEDM 2008 ; A.Villalon et al, VLSI Tech , 2012, Intel: U.E. Avci et al, VLSI Tech 2011
Tunnel FETs : towards sub 0.5V VDD with steep subthreshold slopes
BOx
S D
GP mode N mode
Vth
VG
Log ID
IOFF
ideal switch
TFETMOSFET
Vth
VG
Log ID
IOFF
ideal switch
TFETMOSFET
L=100nm T=300K
Experimental demonstrationof Tunnel FET operation
⇒ down to 33mV/dec
Co-integration w. CMOS
min. 60mV/dec
F.Mayer et al., IEDM 2008 ; A.Villalon et al, VLSI Tech , 2012, Intel: U.E. Avci et al, VLSI Tech 2011
Mastering variability @forefront
Sub 10nm & VDD<0.5V
Approaching Zero Intrinsic Variability
at sub-10nm devices level on Si
and challenging materials
Main topics to be addressed :
� Dopant control at the single atomic level:
deterministic doping
� Monodisperse patterning:
resist self assembly, self limiting chemical dry etching,…
� Interconnect with monodisperse features and objects :
CNT, DNA templates,…
� Are Atomically thin active 2D Semiconductors
Challenging Si ?
2nm
CEA-LETI&CEA-INAC: M. Pierre et al. , Nature Nano. 5, 133, 2010R. Wacquez et al. , VLSI symposium 2010R. Wacquez et al. , Silicon NanoWorkshop 2010(*) D. Cooper, by courtesy
SINGLE ELECTRON- SINGLE ATOM EFFECTS Characterized at low temperature but important up to 30 0K: control the SS @300K
Discrete nature of dopants distributedrandomly affects MOSFET device behaviour at
small sizes
TOWARDS SINGLE ATOM CONTROLLED TRANSISTOR
CEA-LETI&CEA-INAC: M. Pierre et al. , Nature Nano. 5, 133, 2010R. Wacquez et al. , VLSI symposium 2010R. Wacquez et al. , Silicon NanoWorkshop 2010(*) D. Cooper, by courtesy
SINGLE ELECTRON- SINGLE ATOM EFFECTS Characterized at low temperature but important up to 30 0K: control the SS @300K
Discrete nature of dopants distributedrandomly affects MOSFET device behaviour at
small sizes
TOWARDS SINGLE ATOM CONTROLLED TRANSISTOR
CIRCUIT IN ONE DEVICE : electron pump by association of 2 dopants in a MOSFET channelRoche B. et al., Nature Comm., 4, n° 1581
Deterministic Doping
Physical methods : Single Ion Implantation Ions are selected through chopper. The number ofimplanted ions is controlled by secondary electrondetection. Shinada et al., IEDM, 2011
Challenges: tune & align to transistor channel & S-D
Chemical methods : Grafting on Silicon or SiO 2(*)
Boron (p type dopant P) uniform positioning throughlinking molecule Surface Density: 1.7x10 14 at.cm -2
Ho et al., Nature Materials, 2008
(*)L.Matthey et al., SSDM, 2013
UNSW: Fuechsle et al, Nature Nanotech ,2012
Placement of dopants by CVD following STM lithography
ARKEMA – LETI partnership
� Today : polymers in 300 mm pilotline in LETI : PS-b-PMMA withresolutions about 15 nm
High χ BCPPS-b-PMMA BCP
200 nm 200 nm
CD ≈ 15nm CD ≈ 15nm
� Tomorrow : new polymers with resolutions < 10nm
Carnot Institute project, LETI-LTM/Minos
Lithography based on Block-Co -Polymers:monodisperse lines, spaces and holes
χ : Flory Huggins interaction parameter
CEA-LETI, CNRS-LTM, ARKEMA: R. Tiron et al, , 37th SPIE - 2012
Interconnect: contact heterostructures
and monodisperse features
� Heterostructures by (non-alloyed contacts and
Atomic Layer Epitaxy
� CNT, graphene metallic wires &viasMeindl et al., Banerjee et al, Dijon et al.
� Metallation of DNA HF Sleiman et al,Clavé et al.
Remaining issues:- trapping @heterostructures- bundles- deterministic placement…
(c) 2D-graphene
DNA metallation by Cu 5-
(d) 1D-nanotube
2D Crystals offer new spaces and add-ons to Si
2D crystals
Jena et al, 2014 SNW
Atom-thick, hexagonally arranged 2D sheets :graphene, hBN, silicene, germanene , layered oxides and chalcogenides (MoS2 , WSe2 , Bi2Se3 , Bi2Te3)
FlexibleTransparentHighly conductive
Ma & Jena, PHYS. REV. X 4, 011043 (2014)K. F. Mak et al, Phys. Rev. Lett. 105, 136805 (2010) .
MoS2
2D Crystals offer new spaces and add-ons to Si
2D crystals
Jena et al, 2014 SNW
Atom-thick, hexagonally arranged 2D sheets :graphene, hBN, silicene, germanene , layered oxides and chalcogenides (MoS2 , WSe2 , Bi2Se3 , Bi2Te3)
FlexibleTransparentHighly conductive
Ma & Jena, PHYS. REV. X 4, 011043 (2014)K. F. Mak et al, Phys. Rev. Lett. 105, 136805 (2010) .
MoS2
Direct bandgap @ 1ML Electroluminescent and PV heterostructure
Silicon Photonics
O.Lopez-Sanchez, ACS Nano, 2014
State of the art characterization tools
In line characterization in LETI 300 mm clean room
State of the art characterization tools
In line characterization in LETI 300 mm clean room
Off line dedicated 2D materials characterization
State of the art characterization tools
In line characterization in LETI 300 mm clean room
Off line dedicated 2D materials characterizationBN surface
(HREH)impurities
Outline•Introduction
•Issues for scaling Silicon and thin films devices: towards Zero Intrinsic Variability
• Role of Fully depleted devices towards Low Power /High Perfomance
• Aiming at Zero Intrinsic Variability@sub10nm level and new active materials integration (approaching molecular and atomicdimensions)
•Heterogeneous Co-integration of scalable (More Moore) and diversification (More than Moore) devices .
• New opportunities for Computing and Sensing
• 3D as a strong asset at the functional and system levelstowards Zero Power
•Conclusion
(100)
(110)
P.Batude et al., IEDM 2009, 2011 VLSI Tech Symp , VLSI-TSA 2013
C.Fenouillet-Beranger et al. IEDM 2014
-Cold end process(bonding) & Low Thermal Budget -Opportunities for other SC(Ge and alloysIII-V, C, ...) -Layout Improvement by partitioning(40% area 6T SRAM cell)- High density Embedded intelligence(sensors, actuators,…)
3D sequential process: Highly Performing Heterogeneous Co -Integration
3D-Xbar Memory stacked on Logic: towards high system performance and NV-Logic
NV Logic proven in 2D withMagnetic Tunnel Junctions, FeRAM, ReRAMTohoku Univ., Hitachi, S.Matsunaga et al., Appl.Phys. Express(2008); ROHM; LETI: Vianello et al, IEDM 2014
Resistive switches (CBRAM, OxRAM, PCM)Suri et al. IEDM 2011 , Vianello et al IEDM 2014 Toshiba, Stanford Univ.: K.Abe et al, ICICDT 2008; Logic + Stacked Memories:
High bandwith-wide I/Os (DRAMs) ex: 32 nm node : > 1TB/s per 1mm2,
Reduced Power consumption, latency,NV-SRAM (NVM), …
Reconfigurable, Neuromimetic(NVM)
Advanced Devices and Systems Future Vision based on FDSOI
See also “Intelligent Integrated Systems”, PanStanford S eries on Intelligent Nanosystems, vol.1, S.Deleonibu s, Editor, Singapore, (2014).
CEA-LETI: J.Arcamone et al. , IEDM 2011
Q=870 resonatorGauge width = 80 nm
Mass detection
Improvement of Noise figures,
Power Consumption and Speed
thanks to CMOS co-integrationSensing: multigas analysis with NEMS
Computing: Ultra Low
Power Consumption
Houri S. et al., to be published
CEA-LETI: J.Arcamone et al. , IEDM 2011
Q=870 resonatorGauge width = 80 nm
Mass detection
Improvement of Noise figures,
Power Consumption and Speed
thanks to CMOS co-integrationSensing: multigas analysis with NEMS
Computing: Ultra Low
Power Consumption
Houri S. et al., to be published
CEA-LETI: J.Arcamone et al. , IEDM 2011
Q=870 resonatorGauge width = 80 nm
Mass detection
Improvement of Noise figures,
Power Consumption and Speed
thanks to CMOS co-integrationSensing: multigas analysis with NEMS
Computing: Ultra Low
Power Consumption
Houri S. et al., to be published
-contact resistance
van der Walls forces
surface roughness
-endurance, performance
-actuation mode
System On Wafer: Heterogeneous co-Integrated Systems (Parallel 3D)
Packaging(thin films) taken intoaccount at the 3D wafer level
System On Wafer: Heterogeneous co-Integrated Systems (Parallel 3D)
Packaging(thin films) taken intoaccount at the 3D wafer level
Commercial products- image on board VGA camera, - mixed nodes & modes, - High I/Os w. high density TSV
Cross talks:-delay, matching, -power dissipation (global temp. increase, hot spots, reliability,…)
. ,
WLPackaging & Interposer: => thin films, autonomous,
communication, biocompatibilty
Multiphysicselectronics, photonics, optics, piezoelectricty, spintronics,
NewProgressLaws-application specific
Education , Training
Tomorrow driving embedded sensing applications ?
Autonomous & Heterogeneous co-integration:
3D “play ground”Moore
90nm
65nmStrained
45nmHigh-k
32nm
22nm3D Tr
Battery
Memory
Processor
MEMS
DNA Chip
Image Sensor
RF Chip
Lab on chip Capsule endoscope
Integrated / wearable
Sensors
Medicine
nano-robot
3D die stacking
3D circuit
3D transistor
Adapted from Kwon et al, 2007 DAC
Ultra-low power needed for all devices Energy storage(thin films) and harvesting
=> Zero Power from a gridExtendable to other sectors (automotive, communication,energy,… )
Energy to be cleverly savedtoday’s World citizen has to keep in mind :
the most useful energy is … the one you do
not waste!!� Low power sensors and actuators, data processing,
communication � Energy Harvesting is one thing… from unwasted energy!� Energy Storage is another important issue in the energ y
problematics!!!
no concentration
Energy to be cleverly savedtoday’s World citizen has to keep in mind :
the most useful energy is … the one you do
not waste!!� Low power sensors and actuators, data processing,
communication � Energy Harvesting is one thing… from unwasted energy!� Energy Storage is another important issue in the energ y
problematics!!!
no concentration
Energy to be cleverly savedtoday’s World citizen has to keep in mind :
the most useful energy is … the one you do
not waste!!� Low power sensors and actuators, data processing,
communication � Energy Harvesting is one thing… from unwasted energy!� Energy Storage is another important issue in the energ y
problematics!!!
0,0001
0,001
0,01
0,1
1
10
100
PV Mechanicalvibration/Piezo
electricity
Glucose Thermoelectricity,magnetostriction,
ferroelectricity
(mW/cm2)
Energy harvesting
indoor
outdoor
no concentration
On Bio compatible ceramics On Polymer
Energy Storage: thin films batteries
flexible
LGA 5x5 mm
SIP
BGA 8x8 mm
Above IC
Coin cell ( and its socket ) replacement
16 µ-batteries 100x100µm
co-integration
on chipLiPON typical values
Capacity
250 µAh.cm-2.µm-1
Conclusion : Nanoelectronics CMOS from Devices to Systems Perspectives
� Innovation from strong association System/Device/Materials Science and Engineering
� Si CMOS: Nanoelectronics Base platform beyond ITRS:
aiming at Zero Intrinsic Variability Major interest for sub 10nm
� Low Power consumption: major challenge & sub 0.5 VDD Device/ system architecture optimization
(GAA nanowires, low slopes TFET, 3D, design, computing architecture)
Opportunities for new materials(Ge &SiGe based alloys,revised low BG III-V, Carbon, 2D materials)
� Heterogeneous 3D co-Integration on Si. Towards Zero Power:Add Functionalities for diversification. NonCMOS & CMOS 3rd dimension in device, Stacked mixed functions, System On Wafer
Energy Harvesting, Storage and Management. Nomadic/Autonomous systems
� Sustainable Low Power solutions: health, environment, quality of life, IST,…
Merci de votre attention
Thank you for your attention
Electronic Device Architectures for the Nano-CMOS EraFrom Ultimate CMOS Scaling to Beyond CMOS Devicesedited by Simon Deleonibus (CEA-LETI, France) Cloth July 2008 978-981-4241-28-1
� Discusses the scaling limits of CMOS, the leverage brought by new materials, processes and device architectures (HiK and metal gate, SOI, GeOI, Multigate transistors, and others), the fundamental physical limits of switching based on electronic devices and new applications based on few electrons operation
� Weighs the limits of copper interconnects against the challenges of implementation of optical interconnects
� Reviews different memory architecture opportunities through the strong low-power requirement of mobile nomadic systems, due to the increasing role of these devices in future circuits
� Discusses new paths added to CMOS architectures based on single-electron transistors, molecular devices, carbon nanotubes, and spin electronic FETs
Available at Amazon.com or any good bookstores.