Fundamentals on Electronics: A Design Oriented Teaching ...
Transcript of Fundamentals on Electronics: A Design Oriented Teaching ...
01st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
1st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Jose Silva-Martinez
Department of Electrical and
Computer Engineering
Texas A&M University
Fundamentals on Electronics: A Design
Oriented Teaching Methodology
11st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Mixed-Signal Integrated Circuits
Mobile DevicesMedical Imaging
Sensing and Biometrics
Amplifiers, Filters and Analog-to-Digital Converters: Interfacing with the world
21st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Market Growth in Wireless Communications
Smartphones By 2016 market > 2B units*
*Business Insider: The global smartphone market report
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Important Features: Wireless; 5G and Beyond
f
Carrieragregation
GHz
singlecarrier
High bandwidth (160 MHz)
β’ Carrier aggregation
β’ Full band capture
High resolution (>10 bit)
β’ Presence of blockers requires high dynamic range
β’ Better Linearity (Co-existence)
Low power consumption
β’ Extent battery life of wireless receivers.
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There are multiple architectures to select, depending on your bandwidth and resolution requirements.
4
6
8
10
12
14
0.1 1 10 100 1000
EN
OB
(b
its
)
BW (MHz)
Ξ£Ξ
Pipeline
SAR
Flash,
t.i. SAR
Sigma delta (Ξ£Ξ) and pipeline ADCs are the bestarchitectures for broadband wireless receivers
6 8 10 12 14 16 18
0.0
1 0
.1 1
1
0
Cable TV
Spectrum
Analizers
Ultrasound
Radar
Automotive
Wireless
InfrastructureFlat Panel
Defense
Communications
RadarSonet
Digital
Oscilloscope
Emerging
802.11ax
Effective number of bits
Sig
na
l B
an
dw
idth
(G
Hz)
Mixed-Signal Integrated Circuits
51st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Technology Trend: Increased throughput
Low-Noise and Linear Amplifiers
High Performance Filters
High performance Up/Down Converters
High-performance Frequency Synthesizers
High performance A/D and D/A
But technology trend is towards faster and smaller
transistors but limited performance for Analog Functions:
Back to fundamentals: Linear feedback (Calibration) is a
suitable option
61st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
How to prepare for these challenges?
β’ Teaching electronics:
β’ Millman-Halkias: One of the most popular books in the 70βs and early 80βs.
β’ Nicely written and large number of examples. 75% Analog and 25% Digital
β’ Sedra-Smith: Replaced Millman-Halkias. The most popular textbook on electronics during the last 20 years. Many authors follow this style. Less algebra and more insight. >1800 pages, 50% Analog and 50% digital electronics.
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Teaching Electronics:
β’ Ravazi: Recent book, becoming very popular. Updated material. Nice book with videos available through youtube.
β’ A large number of excellent textbooks are available, but students have to digest the material in 14-15 weeks.
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Challenges in todayβs education
Big books with plenty of derivations help with the analysis of circuits, but make
difficult for students to digest properly the concepts;
Too compact, we endup with a cook book; hard to understand the most relevant
concepts;
Analysis with the aim of obtaining DC and AC equations do not necessarily help
students to understand the fundamentals;
Major device limitations should be emphasized as well;
Design approach: Students must be able to design working circuits, not just analysis;
Proper management of the simulators;
Hands on experience is essential to fully digest the material;
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Outline
First part:Revising BJT FundamentalsSmall-signal Model for the BJT: A Linear Approximation.Transistor characterization and design approach.Design examples
CMOS Fundamentals (same topics as in BJTs)
10 minutes break
101st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Outline
Second part:CMOS (Integrated circuits) blocks
Technology, modeling and noise
Current mirrors
Differential pair
OPAMPs
Advanced Amplifiers for ADCsPipeline ADCs
SD Modulators
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Outline
Hands-On Experience Sessions: 2:30pm-4:45pm
Undergraduate examples: Please download LTSpice before the session; google LTSpice)Jose Silva-Martinez: Connecting theory with simulations
Tanwei Yan: Use of AD2 as oscilloscope, frequency synthesizer, network analyzer, vector analyzer
Advanced Mixed-Mode Systems: Pipeline ADC as an example Junning Jiang: Macromodels in Cadence (can also be built in LT Spice with
some limitations)
Amr Hassan: Transistor level realization of the first ADC stage, and simulations results and interpretations
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Bipolar Junction Transistor Circuits
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5.2 DC Characteristics of the BJT (Input)
β’ π°πͺ vs π½π©π¬ plot
ππΆ = πΌπ πππ΅πΈπππ» β 1
(in active region)
β’ Forward bias current
β’ ππ΅πΈ = 0.7, for reasonable πΌπΆ
β’ Typical reverse saturation current πΌπ < 0.1ππ΄
IC (A)
VBE (V)0.6 0.8
QCQ
VBEQ
0.40.20.0-0.2-0.4
πΌπΆ vs ππ΅πΈ
141st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.2 DC Characteristics of the BJT (Output)
β’ π°πͺ vs π½πͺπ¬ plot
β’ ππ΅πΈ is fixed for each sweep
β’ Two region of operation
β’ ππΆπΈ β₯ 300ππ β Active region
β’ ππΆπΈ < 300ππ β Saturation region
β’ Active region / Linear region
β’ ππΆ = πΌπ πππ΅πΈπππ» β 1
β’ Saturation region
β’ ππ = Depends on ππΆπΈ and ππ΅πΈ
C
VBE1
VCE
VBE4
VBE2
VBE3
VBE0
πΌπΆ vs ππΆπΈ
β’ Cut-off regionβ’ ππ΅πΈ < 0.5πβ’ πΌπΆ , πΌπΈ and πΌπ΅ are nearly zero
Saturation region
Active/Linear region
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5.3 Small-signal Model for the BJT
RC
vbe
+
-
vCE
+
-
iC
How to analyze this circuit?
VBE
ππ΅πΈ + π£ππ Q
VBE + vbe
ICQ + ic
Tim
e
Time
iC (A)
VBE (V)0.6 0.80.40.20.0
β’ Base-emitter voltage is mapped into collector-emitter current
β’ Larger ππ΅πΈ implies larger πΌπΆπ
β’ Larger input signal π£ππ generates larger collector/emitter current
ππΆ = πΌπ πππ΅πΈ+π£ππ
ππ‘β β 1 β πΌππππ΅πΈππ‘β π
π£ππππ‘β = πΌπΆπ β π
π£ππππ‘β
ππΆ = πΌπΆπ + πΌπΆπ
π£ππ
ππ‘β+
πΌπΆπ
2
π£ππ
ππ‘β
2
+πΌπΆπ
6
π£ππ
ππ‘β
3
+. . . .
161st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
BJTβs Large-signal Model
VBE
RC
vbe
+
-
vCE
+
-
iC
ππ΅πΈ + π£ππ
β’ ππΆ = πΌπΆπ + πΌπΆππ£ππ
ππ‘β+
πΌπΆπ
2
π£ππ
ππ‘β
2+
πΌπΆπ
6
π£ππ
ππ‘β
3+. . . .
β’ If the AC input signal is π£ππ = πππsin(π0π‘), then
β’ ππ = πΌπΆπ +πΌπΆπ
4
πππ
ππ‘β
2+
πΌπΆπ
ππ‘ββ
πΌπΆπ
8
πππ
ππ‘β
2πππ sin π0π‘ β
πΌπΆπ
4ππ‘β
πππ
ππ‘βπππ sin 2π0π‘ +
πΌπΆπ
24ππ‘β
πππ
ππ‘β
2πππsin(3π0π‘) Quasi linear
term
2nd Order term 3rd Order term
2nd , 3rd, β¦ Harmonics cause distortion in circuits
171st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.3 Small-signal Model for the BJT
β’ If we assume πππ < 0.4ππ‘β (small signal)
β’ ππΆ = πΌπΆπ +πΌπΆπ
ππ‘βπ£ππ ( Linear approximation)
β’ AC current linearly dependent on AC voltage
β’ Slope of πΌπΆ vs ππ΅πΈ is Transconductance
ππ = πππΆ
ππ£π΅πΈ π=
πΌπΆπ
ππ‘β
This model does not capture amplifierβs non-linearities
Since the resulting circuit is linear, you can use any amplitude
Q
VBEQ
ICQ
iC (A)
VBE (V)0.6 0.80.40.20.0
QBE
Cm
v
ig
181st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.3 Small-signal Model for the BJT
β’ Modelling BJT
β’ ππ is modelled as CCCS with ππ =πΌπΆπ
ππ‘β
β’ Forward biased diode across Emitter and Collector
β’ Diode can be modelled as resistor ππ and voltage source 0.7π series
β’ ππ =1
ππ=
πππ΅
ππ£π΅πΈ π=
πΌπ΅π
ππ‘β
E
IC+gmvbeiB
B
C
iE
iC
Q
VBEQ
ICQ
iC (A)
VBE (V)0.6 0.80.40.20.0
QBE
Cm
v
ig
E
IC+gmvbeiB
B
C
ie
ic
r
+
0.7V
-
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5.4.4 π and T model for BJT
E
r
gmvbeib
C
rce
ie
ic
re
ie
ieib
C
rce
ic
π β hybrid model for BJT π β model for BJT
β’ πππ is the finite output resistance of BJT
β’ Choose model with makes solving circuit easier
β’ πππ =πΌπΆπ
ππππππ¦
β’ ππ =1
ππ=
πππ΅
ππ£π΅πΈ π=
πΌπ΅π
ππ‘β
β’ πππ =πΌπΆπ
ππππππ¦
β’ ππ =1
ππ=
πππΈ
ππ£π΅πΈ π=
πΌπΈπ
ππ‘β
Hence
ππ =ππ‘β
πΌπΈπ=
ππ‘β
1 + π½ πΌπ΅π=
ππ1 + π½
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5.4.1 DC analysis
β’ What is maximum tolerable value of π£ππ ?
β’ BJT should be in active region always
β’ Lowest possible value of ππΆ = ππ΅-0.4V
iC
VCE
Q
VCEQ
ICQ VBEQ
VCC
VCC/RC
0.3V
linear range
vbe-peak
vce-peak
RC
vbe
+
-
vCE
+
-
iC
VBE
ππ΅πΈ + π£ππ
Input signal swing
Output signal swing
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5.4.5 Practical limitations
β’ ππΆπΈ > 300ππ needed to maintain linear mode of operation
β’ Non-ideal effects limit max. current densityβ’ Maximum achievable π½ is limited
β’ Temperature sensitivity of parametersβ’ ππ, ππ, and π½ are sensitive to temperature
β’ Very large ππΆπΈ cause large πΌπ. β’ P-N junction breakdown
β’ Current gain (π½) reduces with frequencyβ’ poles due to internal resistance and capacitance
IC(mA)0.01
27ΒΊ
0.1 1.0 10 100
250
200
150
110ΒΊ
-50ΒΊ
350
300
VCE
VBE1
VBE2
VBE3
VBE4
VBE5
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5.5.1 Common emitter amplifier
VCC
RC
vbe
voiC
CC
RL
VBEQ+
- E
r
gmvbeib
B
RC
ie
C
vbe
vo
CC
RL
VCEQ
+
-
Small signal equivalent
Input Output
β’ AC solution
β’ Use KCL & KVL on above circuit
β’ π£π = βπππ πΆπ π πΏπΆπΆ
1+π (π πΆ+π πΏ) πΆπΆπ£ππ
β’ DC solution
β’ πΌπΆπ = πΌππ
ππ΅πΈπ
ππ‘β
β’ ππΆπΆ = ππΆπΈπ + πΌπΆππ πΆ
231st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.5.1 Common emitter amplifier
π£π = βπ πΆπ πΏ
π πΆ + π πΏπππ£ππ = β
π πΆπ πΏ
π πΆ + π πΏππ
β’ Gain higher with static loading
β’ Gain reduction due to loading should be taken into account during design
iC
VCE
QICQ
VCC
VCC/RC
0.3V
static load
line (1/RC)
VCEQ
VBEQ
iC
VCE
QICQ
VCC
VCC/RC
0.3V VCEQ
static load
line (1/RC)dynamic load
line (1/[RC||RL])
VBEQ
241st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.5.2 Common-emitter amplifier with resistive biasing.
β’ ππ΅π΅ =π π΅
π 1ππΆπΆ = πΌπ΅ππ π΅ + 0.7π
β’ ππΆπΆ = ππΆπΈπ + πΌπΆππ πΆ
Here πΌπ΅π =πΌπΆπ
π½
Two equations, Four variables
π 1, π 2, π π and πΌπΆπ
VCC
RCICQ
RB
VB
+
-CC
B VR
R
1
+
-
VCEQ
IBQ
DC equivalent circuitβ’ ππ΅π΅ =
π π΅
π 1ππΆπΆ = πΌπ΅ππ π΅ + 0.7π
πΌπ΅π =
π π΅π 1
ππΆπΆ β 0.7
π π΅
πΌπΆπ =
π π΅π 1
ππΆπΆ β 0.7
π½ π π΅
β’ πΌπΆπ varies a lot, mainly due to π½ variability.
251st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.5.2 Common-emitter amplifier with resistive biasing.
β’ π£be π>ππ=
ππ
ππ+π π΅
π π΅
ππ||π π΅π£π β π£π ,
ππ =1
ππ||π π΅ πΆπ΅β
1
πππΆπ΅
β’ Following earlier circuit analysis
β’ Has two poles. Each due to blocking capacitors πΆπ΅ and πΆπΆ
β’ If π β« ππ1 and π β« ππ2 then
RC
vo
RB +
vbe
-
CB
CC
RL
i
BB
BBv
CsR1
CsR
E
rgmvbe
ie
CB
iL
AC equivalent circuit
π£π = βπ π πΏπΆπΆ
1 + π π πΆ + π πΏ πΆπΆπππ πΆ π£ππ = β
π π πΏπΆπΆ
1 + π π πΆ + π πΏ πΆπΆ
π π π΅πΆπ΅
1 + π ππ||π π΅ πΆπ΅
ππππ + π π΅
πππ πΆ π£π
ππβππππ’π‘ = ππ1 = β1
ππ||π π΅ πΆπ΅and ππβππ’π‘ππ’π‘ = ππ2 = β
1
π πΆ+π πΏ πΆπΆ
π£π
π£πβ βππ
π πΆπ πΏ
π πΆ + π πΏ= βππ π πΆ||π πΏ
261st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.6.1 Common-emitter amplifier
β’ Aim β Design Common Emitter amplifier with a high-frequency gain = 34 dB.
β’ Q2N222 BJT used for this design
β’ In general π½π΄πΆ β 200 and π½π·πΆ β 200
β’ DC Transistor Characterizationβ’ Use this configuration to plot ππ΅πΈ vs πΌπβ’ Use ππΆπΈ = 1π, Since ππΆπΈ > 0.3π β
Linear region on
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5.6.1 Common-emitter amplifierMeasure π π¦
β’ ππ =ππΌπ
πππ΅πΈ
β’ Slope of curve
β’ Compare this value
with ππ =πΌπΆπ
ππ‘β
β’ How to find out π πΆ?
Slope = gm @ IC=1.2mA
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5.6.1 Common-emitter amplifier
Measure πΉπ
β’ Plot πΌπ vs ππΆπΈ for ππ΅πΈπ =0.65π
β’ Slope=1
RπΆ=
ππΌπΆ
πππΆπΈ;
Zoomed in version of above plot
πΌπΆ vs ππΆπΈ
Slope = 1
π π
291st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.6.1 Common-emitter amplifier
Measure ππ
β’ Plot πΌπ΅ vs ππ΅πΈat ππΆπΈ = 1π
β’ Slope =1
ππ= ππ
β’ ππ =ππΌπ΅
πππ΅πΈSlope = g @ IB=5mA
301st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Common emitter Circuit with source degeneration
β’ Previous design issueβ’ Difficult to control operating point (πΌπ)
β’ π πΈ1 and π πΈ2 are added at emitter
β’ πΆπΈ to regain some of lost gain
β’ Advantages:β’ Circuit less sensitive to temperatureβ’ More control over πΌπ and gainβ’ Higher input impedance
β’Drawbacks:β’ Reduced small signal gain
β’
VCC
RC
vi
vC
RB1
RB2
vB
RE1
RE2 CE
CBRS
RL
vo
CL
311st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
DC analysis
πͺπ© and πͺπ³ are treated as open
ππ΅π΅ =π π΅
π π΅1ππΆπΆ = πΌπ΅ππ π΅ + 0.7π + πΌπΈπ π πΈ1 + π πΈ2
= 0.7π + πΌπΆπ
π π΅
π½+
1
πΌπ πΈ1 + π πΈ2
π π΅ = π π΅1||π π΅2
ππΆπΆ = ππΆπΈπ + πΌπΆππ πΆ + πΌπΈπ π πΈ1 + π πΈ2
= ππΆπΈπ + πΌπΆπ π πΆ +π πΈ1 + π πΈ2
πΌ
VCC
RC
vi
vC
RB1
RB2
vB
RE1
RE2 CE
CBRS
RL
vo
CL
VCC
RCRB1
RB2
vB
RE1+RE2
VCEQ
ICQ
IEQ
+
-
Amplifier
DC equivalent circuit
πΆπ΅ and πΆπΏ are treated as open
321st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
DC analysis
ππ΅π΅ =π π΅
π π΅1ππΆπΆ = πΌπ΅ππ π΅ + 0.7π + πΌπΈπ π πΈ1 + π πΈ2
= 0.7π + πΌπΆππ π΅
π½+
1
πΌπ πΈ1 + π πΈ2 -- (1)
πΌπΆπ =ππ΅π΅ β 0.7
π π΅π½
+1πΌ
π πΈ1 + π πΈ2
ππΆπΆ = ππΆπΈπ + πΌπΆππ πΆ + πΌπΈπ π πΈ1 + π πΈ2
ππΆπΈπ = ππΆπΆ + πΌπΆπ π πΆ +π πΈ1 + π πΈ2
πΌ
VCC
RC
vi
vC
RB1
RB2
vB
RE1
RE2 CE
CBRS
RL
vo
CL
VCC
RCRB1
RB2
vB
RE1+RE2
VCEQ
ICQ
IEQ
+
-
DC equivalent circuit
πΆπ΅ and πΆπΏ are treated as open
331st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
AC analysis
β’ πΆπ΅ and πΆπΏ are treated as short
β’ Also we assume π π βͺ ππ
π§π =π£π
ππ=
π£π
ππ/(1 + π½)= 1 + π½ ππ + π πΈ1
π§π = ππ + 1 + π½ π πΈ1
β’ Input impedance increased
- Good for design vi
RE1
reie
iezb RC||RL
vo
RB
ib
zi
VCC
RC
vi
vC
RB1
RB2
vB
RE1
RE2 CE
CBRS
RL
vo
CL
Amplifier
DC equivalent circuit
341st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
AC analysis
π£π = βπΌππ π πΆ π πΏ Where
ππ =π£π
ππ + π πΈ1=
π£ππΌ
ππ+ π πΈ1
=ππ
πΌ + πππ πΈ1π£π
β’ π΄π =π£0
π£π= β
πΌππ π πΆ π πΏ
πΌ+πππ πΈ1
β βπΆ πΉπͺ πΉπ³
πΉπ¬πif πΌ βͺ πππ πΈ1
β’ Gain reduced due to πππ πΈ1
β’ Voltage gain is well controlled
β’ Larger π ππ lower πΊπππ
vi
RE1
reie
iezb RC||RL
vo
RB
ib
zi
VCC
RC
vi
vC
RB1
RB2
vB
RE1
RE2 CE
CBRS
RL
vo
CL
Amplifier
AC equivalent circuit
351st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Design employing a Graphical approach
Design Constrains
β’ Expected maximum amplitude Vomax of the output signal (often called the βmaximum output swingβ)
β’ Required voltage gain AV
β’ Input and load impedance requirements
β’ Restricted supply voltage VCC
VCC
RC
vC
RB1
RB2
vBCB
RL
vo
CL
vi
361st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Common-Emitter: Design approach
β’ For DC operating pointβ’ ππΆπΆ = ππΆπΈπ + πΌπΆππ πΆ
β’ ππΆπΈπ should be large enough to support ACβ’ ππΆπΈπππ = ππΆπΈπ β ππππ > ~300ππ
β’ We choose ππΆπΈπππ = 500ππ
β’ πΌπΆπ <ππΆπΆβππΆπΈπππ
π πΆ=
ππΆπΆβππππβ0.5
π πΆ-- (1)
β’ ππΆπΈπ shouldnβt be close to ππΆπΆ
β’ πΌπΆπ >ππππ
π πΆ-- (2)
VCC
vbe
RC
vo
VCE
CC
RL
+
-
ICQRC
+
-
+
-VBB
Vomax
Vomax
VCC
ICQRC
VCEmin
VCEQ-VCEmin
VCEQ
371st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.10.1 Common-Emitter: Design approach
β’ Gain of amplifier gives constrain
β’ π΄π =π£π
π£ππ= ππ π πΆ π πΏ =
πΌπΆπ π πΆ π πΏ
ππ‘β
β’ πΌπΆπ = π΄π β ππ‘βπ πΆ+π πΏ
π πΆπ πΏ-- (3)
β’ What is the range of values of π πΆthat satisfy all constrains?
β’ We can plot equations to find the solution
VCC
vbe
RC
vo
VCE
CC
RL
+
-
ICQRC
+
-
+
-VBB
Vomax
Vomax
VCC
ICQRC
VCEmin
VCEQ-VCEmin
VCEQ
381st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.10.1 Common-Emitter: Design approach
β’ Using VCC = 5V, Vomax = 1 V, Vth = 26 mV, RL = 10KΞ©
Eq. (1)
Av=-100
=-40
=-20
=-10Eq. (2)
Eq. (3) Av=-20
Acceptable current
Acceptable resistance
1E+3 1E+4 1E+5
Rc (Ohms)
0.01
0.10
1.00
10.00
I c( m
A)
After finding πΌπ, π π΅ can be solved using
π π΅
π 1ππΆπΆ = πΌπ΅π π΅ + 0.7π
And
πππ = ππ π π΅ =πππ π΅
ππ + π π΅=
ππ
1 +πππ π΅
391st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.10.2 Example
β’ Design of a common-emitter amplifier with larger input impedance but limited voltage gain
β’ We assume π π΅ β« π½π πΈ β« ππ
β’ ππ = ππ + π πΈ 1 + π½ π π΅ β 1 + π½ πΌππ‘β
πΌπΆπ+ π πΈ
β’ π πΈ =ππ
1+π½β πΌ
ππ‘β
πΌπΆπ
β’ Bias current
β’ πΌπΆπ <ππΆπΆβππΆπΈπππ
π πΆ+π πΈπΌ
β€ππΆπΆβππππβππππβ0.5π
π πΆ+π πΈπΌ
β ππΆπΆβππππ 1+
1
π΄πβ0.5π
π πΆ+πππ½
VCC
RC
vi
R1
R2
vb
RE
CBRS
RL
vo
CL
401st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
5.10.2 Example
β’ Bias current upper limit is
β’ πΌπΆπ >ππππ
π πΆ
β’ Gain is given by
β’π£π
π£π= πΌ
π πΆ π πΏ
ππ+π πΈ= πΌ
π πΆ π πΏππ‘βπΌπΆπ
+π πΈ
β’ When source resistance is included
β’π£π
π£π=
π£π
π£π
π£π
π£π=
ππ
ππ+π ππΌ
π πΆ π πΏ
ππ+π πΈβ πΌ
π πΆ π πΏ
ππ+π πΈ+π π
1+π½
- (5)
β’ Harmonics are generated from ππ£ππππ‘β = 1 +
π£ππ
ππ‘β+
1
2
π£ππ
ππ‘β
2+
1
6
π£ππ
ππ‘β
3+. .
VCC
RC
vi
R1
R2
vb
RE
CBRS
RL
vo
CL
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5.10.2 Example
β’ We limit π£ππβππ
ππ‘β< 1/4 to limit harmonics
β’π£ππβππ
π£πβππ=
ππ
ππ+π π
ππ
ππ+π πΈ=
ππ
ππ+π πΈ+π π
1+π½
β’π£πβππ
π£πβππβ πΌ
π πΆ π πΏ
ππ
π£ππβππ
π£πβππ=
πΌπΆπ π πΆ π πΏ
ππ‘β
π£ππβππ
π£πβππ
β’ Equation rearranges to πΌπΆπ β ππ‘β
π πΆ π πΏ
π£πβππ
π£ππβπππ΄π£ -
β’ Then
β’ πΌπΆπ β π½ππ‘β
ππ
π£πβππ
π£ππβππβ 1
VCC
RC
vi
R1
R2
vb
RE
CBRS
RL
vo
CL
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5.10.2 Example
β’ Plot made for β’ π½ = 200, Zi 150 k,
RL = 10 k, Vomax = 1 Vpk, and VCC = 5V
β’ There is no solution exist for πππ = 10π and π΄π = 10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2000 4000 6000 8000 10000 12000
Col
lect
or c
urre
nt (m
A)
Collector resistance RC
Equation 5.66; VCC=10
Equation 5.66; VCC=5
Equation 5.72b; |AV|=10
Equation 5.72b; |AV|=5
Equation 5.73; Zi=150kΞ©Acceptable solution
Equation (3); Vcc=10V
Equation (7); |π΄π|=10Equation (7); |π΄π|=5
Equation (8); ππ = 150πΞ© Equation (3); Vcc=5V
πΌπΆπ
πΌππ‘β
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30 dB gain amplifier driving a load of 10kΞ©Relative small input impedance ( r)Robust?Tolerant to temperature and beta variations?
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30 dB gain amplifier driving a load of 10kΞ©
Voltage at collector terminal DC level is around 3.12V Gain 40*1.88 *10/22= 34dB
Voltage at the load impedance
451st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Temperature variations: -500, 270 and 1000
461st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Source Degeneration benefits: More stable operating point Better linearity More stable frequency response More accurate voltage gain Higher input impedance
Source Degeneration drawbacks: Reduced voltage gain
R6 and R5 make the operating point more stable and less sensitive to both T and variations
R6 stabilize the voltage and increase amplifierβs input impedance
Temperature variations: -500, 270 and 1000
Source degenerated amplifier: Temperature sensitivity
471st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Source Degeneration benefits: More stable operating point. The DC voltage at the collector varies from 2.6V till 3.3V; Reduced voltage gain: Voltage gain reduces, and determined by overall load resistance and overall emitter
resistance ~ 14dB; Voltage gain is little sensitive to PVT (process-voltage-temperature) variations; Input impedance >> r
481st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Without Source Degeneration With Source Degeneration
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Without Source Degeneration With Source Degeneration
501st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Summary
β’ DC and AC Analysis of BJT based circuits
β’ Different Amplifier configuration analysisβ’ Common-Emitter, Common β Base and Common Collector
β’ Design procedure based on circuit constrains
β’ Cascade of amplifiers and their analysis
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Field-effect MOS transistors
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Outline
β’ CMOS Transistors Fundamentals.
β’ MOS Transistor Operating in the Saturation Region.
β’ Common-Source Amplifier.
β’ Common-Source Amplifier with Source Degeneration.
β’ Common-gate Amplifier.
β’ Common-Drain Amplifier.
β’ Design Considerations and Examples.
531st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.1 CMOS Transistors Fundamentals.
β’ CMOS transistors β 4 terminal devicesβ’ Source(S), Drain(D), Gate(G), Bulk(B)
β’ N-MOS Transistorβ’ Source & Drain β N-type doping
β’ Bulk (Substrate) β P-type doping
β’ Gate β Metal terminal, Separated with Gate Oxide (Insulator material. Eg: SiO2)
β’ Bulk β B-S and B-D p-n junction reverse biasedβ’ Bulk β Lowest potential in device
B S G D
iD
Thin SiOx
N+
N+
N+
P-type Substrate
Metal Channel Thick
Oxide
G DSB
L
W
vG
VD
VS
VB
iD
N-MOS Cross section view
N-MOS Top view
N-MOS Symbol
541st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.3 MOS Transistor Operating in the Saturation Region
β’ Transistor in saturation region β’ ππΊπ > ππ and ππ·π > ππ·ππ΄π
β’ Drain current equation
β’ πΌDS =πΎπ
2
π
πΏππΊπ β ππ
2 1 + πππ·π
β’ Here π β 1
πΏππππππ¦
β’ Also written as πΌDS =π½
21 + πππ·π ππ·ππ΄π
2
D
VGS
VDS
lID
Triode region
Saturation region
VDS=VDSAT
vg
vd
vs
vb
ids
551st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.2.1 AC model in triode region
β’ Partial derivative of drain current equation gives
πDS β πΌDS + π½π
πππ
ππ£ππ π
π£ππ +πππ
ππ£ππ ππ£ππ +
1
2
π2ππ
ππ£ππ 2
π
π£ππ 2 + 2
π2ππ
ππ£ππ ππ£ππ π
π£ππ π£ππ +π2ππ
ππ£ππ 2
ππ£ππ
2 +
1
6
π3ππ
ππ£ππ 3
π
π£ππ 3 + 3
π3ππ
ππ£ππ 2ππ£ππ π
π£ππ 2π£ππ + 3
π3ππ
ππ£ππ ππ£ππ 2
π
π£ππ π£ππ 2 +
π3ππ
ππ£ππ 2
ππ£ππ
3 +. . .
Where π½π = πΎππ
πΏ
Small signal current πds = π½ππ·π π£ππ + π½ ππ·ππ΄π β ππ·π π£ππ = πππ£ππ + πππ
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6.3.1 Small β Signal Model
β’ Transconductance
ππ = πππππ£ππ
π
= π½ππ·ππ΄π 1 + πππ·π
β’ if πππ·ππ΄π βͺ 1 then we can use ππ β π½ππ·ππ΄π
β’ Drain β Source conductance (output impedance)
πππ = πππππ£ππ π
=π½
2ππ·ππ΄π
2 β π β πΌπ·π β π
β’ Gate-Source capacitance
πΆππ β ππΏπππ₯
π‘ππ₯
vs
vdids
gmvgs
+
vgs
-
vg
gdsCgs
ig=0
1
vs
vd
gmvgs
+
vgs
-
gds
gm
ig=0
Cgs
vg
1
1
π - model
π - model
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6.3.2 Harmonic Distortion
β’ Earlier discussed equation should be used to calculate harmonic terms
π»π·2 =1
1 βπππ·ππ΄π
8 1 + πππ·π
π£ππ π£ππ
β πππ βππ
4ππ·ππ΄π
β’ Note that HD2 for BJT was 1
4
πππ
ππ‘β, where ππ‘β = 25ππ
β’ BJT has higher HD2 than MOSFET
π»π·3 =π΄ππππ·ππ΄π
12 1 + πππ·π +π΄ππππ·ππ΄π
2
π£ππ βππ
ππ·ππ΄π
2
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6.4 Common-Source Amplifier
β’ Like Common-Emitter amplifier in BJT: Use of superposition: DC first then AC analysis
β’ Input β Between Gate & Source
β’ Output β Between Drain & Source
β’ πΆ1 and πΆ2 are coupling capacitors
β’ π πΊ1 and π πΊ2 set DC voltage at Gate
C1 C2
RG1
RG2
RD
RL+
vi
-
vo
VDD
vg
vd
591st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.4.1 DC analysis: Notice that IG=0
β’ Solve these equations to find VG, IDS and VDS
ππΊ = ππΊπ =π πΊ2
π πΊ1+π πΊ2ππ·π·
πΌDS =π½
2ππΊπ β ππ
2
πDS = ππ·π· β πΌDSπ π·
IG=0
IDS
VGSVT
2
2TGSDS VVI
GV
Q
IDS
RG
RD
VDD
VG
+
-
VGS+
-
VD
IDS
601st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.4.2 AC analysis: routine techniques
π£π
π£π= β
π π πΊπΆ1
1 + π π πΊ(πΆ1 + πΆππ )
π π π·||πππ πΆ2
1 + π π π·||πππ + π πΏ πΆ2
πππ πΏ
Further simplifies to
π£π
π£π= β
π ππ1
1 +π
ππ1
π ππ2
1 +π
ππ1
πππ πΏ
C1
C2
RG=
RG1||RG2
RL
+
vi
-
vo
vd
vs
gmvgs
+
-vgs
rs=
1/gm
i=0
Cgs
Zi
vg
rds||RD
Here ππ1 =1
π πΊπΆ1; ππ2 =
1
π π·||πππ πΆ2
ππ1 =1
π πΊ πΆ1+πΆππ ; ππ2 =
1
π π·||πππ πΆ2
AC Small signal equivalent circuit
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6.4.2 AC analysis: conventional analysis
β’ If πΆ1 β« πΆππ and π β«ππ1, ππ2 then
π£π
π£π= βππ β π π·||πππ ||π πΏ
β’ If πΆ1 and πΆππ are comparable and π β«ππ1, ππ2 then
π£ππ
π£πβ
πΆ1
πΆ1 + πΆππ
π£π
π£π= βππ β π π· πππ π πΏ
πΆ1
πΆ1+πΆππ
(log)
40 dB/decade
P1 P2
20 dB/decade
mLdsD
gs
gR||r||RCC
Clog
1
11020
dBi
o
v
v
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6.4.3 Practical Design Considerations
β’ Transistor should remain in Saturation region at all time instances
β’ For negative peak of output
ππ·π = ππ·π· β πΌπ·ππ π· > ππ·ππ΄π + π£πβππ
β’ For positive peak of output
ππ·π = ππ·π· β πΌπ·ππ π· < ππ·π· β π£πβππ
β’ Combining two inequalities we get ππ·π· β ππ·ππ΄π β π£πβππ
π π·> πΌπ·π >
π£πβππ
π π·
Vomax
Vomax
VDD
IDQRD
VDSat
631st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.4.3 Practical Design Considerations
β’ π£πβππ < ππ·ππ΄π to avoid clipping at input side
vGS
Q
VT
VDSAT
VGS
iDS
VDD
vDS
VDS=VDSAT
Q1
Q2
vGS1
vGS2
iDS
Static load
line
VDD/RD
Input side
output side
β’ππ·π·βππ·ππ΄πβπ£πβππ
π π·> πΌπ·π >
π£πβππ
π π·
to avoid clipping at output side
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6.4.4 Harmonic Distortion
Using earlier defined relation
π»π·2 β
πΆ1πΆ1 + πΆππ
1 βπππ·ππ΄π
8 1 + πππ·π
π£ππ π£ππ
π£πβππ
4ππ·ππ΄π
With π£ππ
π£ππ β ππ
πππ π πΏ
πππ +π πΏ; If we also make the approximation π is very small
π»π·2 β πΆ1
πΆ1+πΆππ
π£πβππ
4ππ·ππ΄π=
πΆ1
πΆ1+πΆππ
ππβππ
8πΌπ·π
We have ππβππ
π£πβππ= ππ =
2πΌπ·π
ππ·ππ΄π
Minimum value of πΌπ· required can be calculated as
πΌπ·π β₯πΆ1
πΆ1 + πΆππ
π£πβππ
8 β π»π·2 β π πΏ||π π·
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6.5.1 DC analysis
β’ For DC Analysisβ’ ππΊ = ππΊπ + πΌDSπ π
β’ πΌDS =π½
2ππΊπ β ππ
2 ππ ππΊπ = ππ +2
π½πΌDS
1/2
C1 C2
RG1
RG2
RD
RL+
vi
-
vo
VDD
vg
vd
RS
RG1
RG2
RD
VDD
VG
VD
RS
RG
RD
VDD
VGRS
+
-
VGS+
-
VD
661st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.5.1 DC analysis
β’ We have ππΊ = ππΊπ + πΌDSπ π
β’ πΌDS =π½
2ππΊπ β ππ
2 ππ ππΊπ = ππ +2
π½πΌDS
1/2
β’ Combining two equations we get
πΌDS +1
π π
2
π½πΌDS β
ππΊ β ππ
π π= 0
β’ Solving this equations and picking the meaningful solution we get
πΌDS =1
π½π π2 1 + π½π π ππΊ β ππ β 1 + 2π½π π ππΊ β ππ
Operating point
VGSVT
2
2TGSDS VVI
S
GSGDS
R
VVI
S
GDS
R
VI
GV
Q
IDS
RG1
RG2
RD
VDD
VG
VD
RS
RG
RD
VDD
VGRS
+
-
VGS+
-
VD
671st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.5.1 DC analysis
β’ From πΌπ·π equations we can calculate
dIDSdVπ
=1
π πβ1 +
1
1 + 2π½π π ππΊ β ππ
With π π = 0 equation simplifies to dIDSdVπ
= βπ½ ππΊ β ππ
β’ If we compare the current variability with π π = 0; and when π π β 0
dIDSdVπ π€ππ‘βπ πβ 0
dIDSdVπ π€ππ‘βπ π=0
=
β1 +1
1 + 2π½π π ππΊ β ππ
π½π π ππΊ β ππ
The larger Rs the more stable the current is, then better amplifier
681st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.5.2 AC analysis
β’ Voltage division at input givesπ£π
π£ππ=
π π πΊπΆ1
1 + π π πΊπΆ1
β’ KCL analysis at drain node gives
π£π
π£π= β
π π·
ππ + π π
1 + π π πΏπΆ2
1 + π π π· + π πΏ πΆ2
β’ Voltage division at output node gives
π£0
π£π=
π π πΏπΆ2
1 + π π πΏπΆ2
C1
C2
RG=
RG1||RG2
RL+
vi
-
vo
vd
vs
gmvgs
+
-vgs
rs=1/gm
i=0
Zi
vg
RS
RD
idAC small signal equivalent
β’ Total gain π£0
π£ππ= β
π π·
ππ + π π
π π πΊπΆ1
1 + π π πΊπΆ1
π π πΏπΆ2
1 + π π π· + π πΏ πΆ2
β’ At high frequencyπ£0
π£ππ
β βπ π·||π πΏ
ππ + π π
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6.5.3 Nonlinearity analysis
β’ Taylor series expansion of drain current gives
ππ·π =1 + 2π½π π ππΊ β ππ β 1
2
2π½π π2 +
1 β 1 + 2π½π π ππΊ β ππβ
12
π ππ£ππ +
π½
2(1 + 2π½π π ππΊ β ππ )β
32π£ππ
2 βπ½2π π
21 + 2π½π π ππΊ β ππ
β52π£ππ
3 + β―
β’ Harmonic distortion simplifies to equation
π»π·2 =1
1 + 2π½π π ππΊ β ππ
π½π π
4 1 + 2π½π π ππΊ β ππ1/2
β 1π£ππ
DC Linear term
2nd Order term 3rd Order term
Find expression for HD3 in same way
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6.8.1 Design Example I
β’ For positive swing min drain current requirement is calculated
πΌπ·π >π£πβππ
π π·
β’ When πΆ1 β« πΆππ harmonic distortion condition limits minimum drain current as
πΌπ·π β₯π£πβππ
8β π»π·2β π πΏ||π π·- (2)
β’ Amplifier voltage gain sets required drain current as
πΌπ·π =1
2π½
π£ππ£π
π π·||π πΏ
2
- (3)
C1 C2
RG1
RG2
RD
RL+
vi
-
vo
VDD
vg
vd
711st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
5.0E+03 1.0E+04 1.5E+04 2.0E+04 2.5E+04
Dra
in C
urr
ent
Drain Resistance
Eq. 3Av=6
Eq. 3Av=4
Eq. 1
Eq. 2
6.8.1 Design Example I
Notice that Gain = 4 has a region of possible solutions
Acceptable π π· region is 6.5πΞ© to 15πΞ© πΌπ· in the region 380ππ΄ -1050ππ΄
Gain = 6 doesnβt have a feasible solution region
721st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.8.1 Design Example I
β’ Circuit is simulated in LT spice with π π· = 10πΞ© and πΌπ· = 600ππ΄
Gain vs frequency plot
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6.8.1 Design Example I
Transient response for 1kHz input and amplitude 60ππππ
Signal swing at Drain
Signal swing at Output node
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6.8.1 Design Example I
Harmonic distortion for a 1kHz input and amplitude 60ππππ
β’ Fundamental amplitude of -15
β’ -60 dB second-order harmonic distortion component.
β’ HD2 = -15 - (-60) dB = -55 dB.
β’ The HD3 is around -95 dB with respect to the fundamental component.
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6.8.1 Design Example II
β’ Sensitivity of non source degenerated amplifier to threshold voltage
π₯πΌπ·πΌπ·
π₯ππππ
β
ππΌπ·πΌπ·
πππππ
=ππ
πΌπ·
ππΌπ·πππ
= β2ππ
ππΊπ β ππ
β’ ππ variations can be as high as Β±20%β’ Higher drain current variations
β’π₯πΌπ·
πΌπ·β β
2ππ
ππΊπβππ
π₯ππ
ππ
Common-source Amplifier with DC Source Degeneration
C1 C2
RG1
RG2
RD
RL+
vi
-
vo
VDD
vg
vd
RS
761st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.8.1 Design Example II
β’ Drain current sensitivity for source degenerated current source
π₯πΌπ·πΌπ·
π₯ππππ
β dIDSdVπ
ππ
πΌDS= β
1+2π½π π ππΊβππ β1
1+2π½π π ππΊβππ
ππ
π ππΌDS
β’ Higher the π π less πΌπ·π variations with ππ
β’ But higher voltage drop across π π
β’π₯πΌπ·
πΌπ·β
1β 1+2π½π π ππΊπβππ+π ππΌDS
1+2π½π π ππΊπβππ+π ππΌDS
ππ
π ππΌDS
π₯ππ
ππ
-2.0E+0
-1.8E+0
-1.6E+0
-1.4E+0
-1.2E+0
-1.0E+0
-8.0E-1
-6.0E-1
-4.0E-1
0 1000 2000 3000 4000 5000
Sen
siti
vity
Fu
nct
ion
Source Resistance
771st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
6.8.1 Design Example II
β’ At the lowest voltage swing at output node
πDS = ππ·π· β πΌDS π π + π π· > π£πβππ + ππΊπ β ππ
β’ If we assume πΌπ·ππ π = 2.5π
πDS = ππ·π· β 2.5 β π£πβππ > πΌDSπ π· + ππΊπ β ππ
β’ Proceeding as previous example to find sensitivity
πΌπ·π β€ππ·π·β2.5βπ£πβππ
π π·+
1
2π½π π·2 β
1
2π½π π·
2
- (4)
Vomax
Vomax
VDD
IDQRD
VDSQ-VDSat
781st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
5.0E+03 1.0E+04 1.5E+04 2.0E+04 2.5E+04
Dra
in C
urr
ent
Drain Resistance
6.8.1 Design Example II
β’ No solution exists for π΄π£ = 6 or higher
β’ Range of resistance = 7πΞ© β 13πΞ©
β’ Acceptable range of drain current is 400ππ΄ β 850ππ΄
Eq. 3Av=6
Eq. 3Av=4
Eq. 4
Eq. 2
791st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Summary
β’ DC and AC Analysis of MOSFET based circuits
β’ Different Amplifier configuration analysis
β’ Common Source Amplifier
β’ With and without source degeneration
β’ Design procedure based on circuit constrains
β’ The design process is multi-dimensional where PVT variations must be considered!