Fundamentals of Logic Design 6th Edition Chapter 13
8
91 Unit 13 Problem Solutions Z depends on the input X, so this is a Mealy machine. Because there are more than 2 state variables, we cannot put the state table in Karnaugh Map order (i.e. 00, 01, 11, 10), but we can still read the next state and output from the Karnaugh map. For example, when the input is X = 1 and the state is Q 1 Q 2 Q 3 = 110, we can read the next state and output from the XQ 1 Q 2 Q 3 = 1110 position in the Karnaugh maps for Q 1 + , Q 2 + , Q 2 + , and Z. So in this case, the next state is Q 1 + Q 2 + Q 3 + = 101 and the output is Z = 0. The entire table can be derived from the Karnaugh maps in this manner. Note: We can also fill in the state table directly from the equations, without using Karnaugh maps. See FLD p. 653 for the state table and state graph. Notice that this is a shift register. At each falling clock edge, Q 3 takes on the value Q 2 had right before the clock edge, Q 2 takes on the value Q 1 had right before the clock edge, and Q 1 takes on the value X had right before the clock edge. For example, if the initial state is 000 and the input sequence is X = 1100, the state sequence is = 100, 110, 011, 001, and the output sequence is Z = (0)0011. Z is always Q 3 , which does not depend on the present value of X. So it’s a Moore machine. See FLD p. 653 for the state graph. 13.2 A + = AK A ' + A'J A = A (B' + X) + A'(BX' + B'X) B + = B'J B + BK B ' = AB'X + B (A' + X') Z = AB Present State Next State (A + B + ) Z AB X = 0 X = 1 00 00 10 0 01 11 01 0 11 01 10 1 10 10 11 0 13.3 (a) A+ X AB 0 1 00 01 11 10 0 1 1 0 1 0 1 1 B+ X AB 0 1 00 01 11 10 0 1 0 1 0 1 1 0 10 0 11 1 01 0 00 0 1 1 1 0 1 0 0 0 X = 0 1 1 0 0 AB = 00 00 10 11 01 11 Z = (0) 0 0 1 0 1 13.3 (b) See FLD p. 653 for solution. 13.3 (c) 13.4 (a) Q 1 + =D 1 X Q1 Q2 Q3 00 01 11 10 00 01 11 10 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 Q 2 + = D 2 X Q1 Q2 Q3 00 01 11 10 00 01 11 10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Q 3 + =D 3 X Q1 Q2 Q3 00 01 11 10 00 01 11 10 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 Z X Q1 Q2 Q3 00 01 11 10 00 01 11 10 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 13.4 (b - d) See FLD p. 654 for solutions.
description
Textbook chapter 13
Transcript of Fundamentals of Logic Design 6th Edition Chapter 13
91
Unit 13 Problem Solutions
Z depends on the input X so this is a Mealy machine Because there are more than 2 state variables we cannot put the state table in Karnaugh Map order (ie 00 01 11 10) but we can still read the next state and output from the Karnaugh map For example when the input is X = 1 and the state is Q1Q2Q3 = 110 we can read the next state and output from the XQ1Q2Q3 = 1110 position in the Karnaugh maps for Q1
+ Q2+ Q2
+ and Z So in this case the next state is Q1
+Q2+Q3
+ = 101 and the output is Z = 0 The entire table can be derived from the Karnaugh maps in this manner Note We can also fill in the state table directly from the equations without using Karnaugh maps See FLD p 653 for the state table and state graph
Notice that this is a shift register At each falling clock edge Q3 takes on the value Q2 had right before the clock edge
Q2 takes on the value Q1 had right before the clock edge and Q1 takes on the value X had right before the clock edge
For example if the initial state is 000 and the input sequence is X = 1100 the state sequence is = 100 110 011 001 and the output sequence is Z = (0)0011 Z is always Q3 which does not depend on the present value of X So itrsquos a Moore machine See FLD p 653 for the state graph
132
A+ = AKA + AJA= A (B + X) + A(BX + BX) B+ = BJB + BKB = ABX + B (A + X) Z = AB
Present State
Next State (A+B+)
ZAB X = 0 X = 100 00 10 001 11 01 011 01 10 110 10 11 0
133 (a)
A+X
A B 0 100
01
11
10
0
1
1
0
1
0
1
1
B+X
A B 0 100
01
11
10
0
1
0
1
0
1
1
0100
111
010
000
111
01
00
0
X = 0 1 1 0 0AB = 00 00 10 11 01 11Z = (0) 0 0 1 0 1
133 (b) See FLD p 653 for solution133 (c)
134 (a)
Q1+ = D1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
Q2+ = D2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q3+ = D3
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
134 (b - d) See FLD p 654 for solutions
92 93
136 (a)
137 (a)
Mealy machine because the output Z depends on the input X as well as the present state
135 (a) 135 (b) ZX A
B C 00 01 11 1000
01
11
10
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
Note Not all Karnaugh map entries are needed See FLD p 654 for the state table
135 (c - d) See FLD p 654 for solutions
After a rising clock edge it takes 4 ns for the flip-flop outputs to change Then the ROM will take 8 ns to respond to the new flip-flop outputs The ROM outputs must be correct at the flip-flop inputs for at least the setup time of 2 ns before the next rising clock edge So the minimum clock period is (4 + 8 + 2) ns = 14 ns
136 (b) The correct output sequence is 0101 See FLD p 655 for the timing diagram
136 (c) Read the state transition table from ROM truth table See FLD p 655 for the state graph and table
Present State
Next State (Q1
+Q2
+) ZQ1Q2 X = 0 X = 1 X = 0 X = 1
00 10 10 0 001 00 11 0 010 11 01 0 111 01 11 1 1
Alternate solution Using Karnaugh map order swap states S2 and S3 in the graph and table
StatePresent State
Next State (Q1
+Q2+) Z
Q1Q2 X = 0 X = 1 X = 0 X = 1S0 00 00 01 0 1S1 01 01 10 1 0S2 11 11 00 1 0 S3 10 10 00 0 1
Alternate solution Swap states S2 and S3
Q1+
XQ1 Q2 0 1
00
01
11
10
0
0
1
1
0
1
0
0
Q2+
XQ1 Q2 0 1
00
01
11
10
0
1
0
1
1
0
0
0
Z
XQ1 Q2 0 1
00
01
11
10
0
1
0
1
1
0
1
0
Notice that Z depends on the input X so this is a Mealy machineQ1
+ = J1Q1 + K1Q1 = XQ1Q2 + XQ1Q2
+ = J2Q2 + K2Q2 = XQ1Q2 + XQ2Z = Q2 oplus X = XQ2 + XQ2
92 93
138 (a)
ClockX
Z
Q1Q2
false
11
S0
01
00
S2
S3 S110
00
11
10
01
137 (a) (contd)
StatePresent State
Next StateX1X2 Z
Q1Q2 00 01 11 10S0 00 00 01 01 01 0S1 01 01 01 11 11 0S2 11 11 11 10 11 0S3 10 00 00 10 00 1
Clock
X
X2
1
Q1
Q2
Z
138 (b)
Correct output Z = 0 0 0 1 1 0
139
ClockX
Z
Q1Q2
false
Q3
Correct output Z = 1 0 1 1
Q1+
X1 X2Q1 Q2 00 01 11 10
00
01
11
10
0
0
0
1
0
0
0
1
0
1
0
1
0
1
1
1
Q2+
X1 X2Q1 Q2 00 01 11 10
00
01
11
10
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0 Z
Q1Q2 0 1
0
1
0
0
1
0
Notice that Z does not depend on this input X so this is a Moore machine Q1
+ = X1X2Q1 + Q1Q2 + X1Q2Q2
+ = Q1 (X1 + X2) + Q2 (X1 + X2) = X1Q1 + X2Q1 + X1Q2 + X2Q2Z = Q1Q2
S00
S10
S31
S20
00
01 10 11
00 01
10 1100 01 10
11
11 00 01 10
137 (b)
94 95
1310 ClockX
Z
Q1Q2
false
Q3
false
Correct output Z = 0 0 1 1
1311 (a)X Q1
Q2 Q3 00 01 11 1000
01
11
10
0
0
1
0
0
0
1
0
1
1
1
1
0
0
1
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
Q +3D =3 Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 101 0 1S1 001 011 111 0 1S2 010 110 101 1 0S3 011 010 111 1 0S4 100 001 001 0 1S5 101 011 011 0 1S6 110 110 101 1 0S7 111 010 011 1 0
S3 S6
S4
S1
S7 S2
S0
S5
00
11
11
10
01
01
10
01
01
10
10
0011
0011
00
ClockX
Z
Q1Q2
false
Q3
1311 (b) 1311 (c)
1311 (d)
From diagram 0 1 (0) 1 0 1From graph 0 1 1 0 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
94 95
1312 (a)
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Q +3D =3
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 100 011 1 0S1 001 000 011 0 1S2 010 100 000 1 0S3 011 000 000 0 1S4 100 110 011 1 0S5 101 000 011 0 1S6 110 111 011 1 0S7 111 001 001 0 1
Q
3
Q
1
Q
2
Z
false
X
Clock
Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1312 (c)
1312 (d)
From diagram 1 0 1 (0) 1 1From graph 1 0 1 1 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
1312 (b)
1313 Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 1 Q1
+Q2+ = 01
2 Q1Q2 = 01 X = 0 rArr Z = 0 X = 1 rArr Z = 1 Q1+Q2
+ = 113 Q1Q2 = 11 X = 1 rArr Z = 1 X = 0 rArr Z = 0 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 005 Q1Q2 = 00 X = 1 rArr Z = 0 Q1
+Q2+ = 10
6 Q1Q2 = 10 X = 1 rArr (Z = 0) X = 0 rArr (Z = 1) Q1+Q2
+ = 117 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr (Z = 1) Q1
+Q2+ = 01
8 Q1Q2 = 01 X = 1 rArr (Z = 1) X = 0 rArr (Z = 0) Q1+Q2
+ = 009 Q1Q2 = 00 X = 0 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 01 10 1 001 00 11 0 110 11 00 1 011 10 01 0 1
00
01
10
01
1100
10
11
01
11
00
10
S2
S4
S3
S1 S7
S0
S5
00
11
01
10
01
10
10
0011 S6
10
01
0011
11
00
01
96 97
1314
1315
Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 0 Q1
+Q2+ = 10
2 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 013 Q1Q2 = 01 X = 1 rArr Z = 0 X = 0 rArr Z = 1 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr (Z = 1) Q1+Q2
+ = 115 Q1Q2 = 11 X = 0 rArr Z = 0 Q1
+Q2+ = 11
6 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr Z = 1 Q1+Q2
+ = 017 Q1Q2 = 01 X = 1 rArr (Z = 0) Q1
+Q2+ = 00
8 Q1Q2 = 00 X = 1 rArr Z = 1 Q1+Q2
+ = 119 Q1Q2 = 11 X = 1 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 10 11 0 101 10 00 1 010 11 01 1 011 11 01 0 1
0010
11
01
10
11
01
10
00 0
1
11
00
Clock Cycle Information Gathered1 Q1Q2 = 00 X1X2 = 01 rArr Z1Z2 = 10 Q1
+Q2+ = 01
2 Q1Q2 = 01 X1X2 = 01 rArr Z1Z2 = 01 X1X2 = 10 rArr Z1Z2 = 10 Q1+Q2
+ = 103 Q1Q2 = 10 X1X2 = 10 rArr Z1Z2 = 00 X1X2 = 11 rArr Z1Z2 = 00 Q1
+Q2+ = 01
4 Q1Q2 = 01 X1X2 = 11 rArr Z1Z2 = 11 X1X2 = 01 rArr (Z1Z2 = 01) Q1+Q2
+ = 115 Q1Q2 = 11 X1X2 = 01 rArr Z1Z2 = 01
Note When Q1Q2 = 01 the outputs Z1Z2 vary depending on the inputs X1X2 so this is a Mealy machine
Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 11 10 00 01 11 1000 01 10 01 11 10 01 11 1011 01 10 01 00 00
1316 (a)
X2
Clock
Q1
Q2
Z1
X1
Z2
falseCorrect output Z1Z2 = 10 10 00 01
96 97
00
10
01
11
0010
0110
10101110
00001000
00001001
0100
1101
100111
11
01001100
00000110
1316 (b) Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 10 11 00 01 10 1100 00 00 01 01 10 10 10 1001 11 11 10 10 00 10 01 1110 11 00 11 00 00 00 01 0111 10 01 10 01 00 00 00 00
1317
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 011 0 0S1 001 010 011 0 0S2 010 001 011 0 1S3 011 100 000 0 0S4 100 011 000 0 1
Clock
X
Q
3
Q
1
Q
2
Z
1318 (a)
Clock
X
A
B
JA
KA
5ns 10ns 15ns 20ns 25ns 30ns 35ns
JB = KB
Z
Correct output Z = 0 0 1 0 0 1
All flip-flop inputs are stable for more than the setup time before each falling clock edge So the circuit is operating properly
1318 (b) If X is changed early enoughMinimum clock period = Flip-flop propagation delay + Two NAND-gate delays + Setup time = 4 + (3 + 3) + 2 = 12 nsX can change as late as 8 ns (two NAND-gate delays plus the setup time) before the next falling edge without causing improper operation
Transition table using a straight binary state assignment
98
1319Clock
A
B
C
X
Z
false
Correct output Z = 1 0 1 0 1
A+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
B+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
C+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
ZX A
B C 00 01 11 1000
01
11
10
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
S0
S3
S1
S2
0100
0110
0100
1000
10111100
1100
000110011100
1000
0000
1100
0011
1000
0010
Deriving the State TableJK flip-flop equation Q+ = JQ + KQthere4 A+ = (XC + XC) A + XA
[As JA = XC + XC KA = X Q = A]= AXC + AXC + XA
Similarly B+ = XC + XA + XACC+ = 0 C + (XBA) C = C + XBAZ = XB + XC + XBA
From the Karnaugh maps we can get the state table that follows
StatePresent State
Next State (A+B+C+) Z
ABC X = 0 X = 1 X = 0 X = 1S0 000 000 110 1 0S1 001 111 001 0 0S2 010 000 110 1 1S3 011 111 001 0 1S4 100 100 011 1 0S5 101 101 011 1 0S6 110 100 010 1 1S7 111 101 011 0 1
R = X2 (X1 + B)S = X2 (X1 + B)A+ = A[(X2 ) (X1 + B)] + X2 (X1 + B)
= A (X2 + X1B) + X2X1 + X2BA+ = AX2 + AX1B + X2X1 + X2B
T = X1BA + X1BAB+ = BT + BT
= B(X1BA + X1BA) B (X1BA + X1BA)= B [(X1BA) (X1BA)] + X1BA= B [(X1 + B + A) (X1 + B + A)] + X1BA = (BX1 + BA) (X1 + B + A) + X1BA= BX1 + BX1 + BX1A + BAX1 + BA + X1BA= X1B(1 + 1 + A + A) + A (B + X1B)= X1B + AB + X1A
1320
StatePresent State
A+B+
X1X2=Z1Z2
X1X2=
AB 00 01 10 11 00 01 10 11S0 00 11 01 10 00 10 10 00 00S1 01 11 01 01 01 11 00 11 00S2 10 10 00 10 10 01 00 01 00S3 11 10 00 11 01 00 00 00 00
1320 (contd)
92 93
136 (a)
137 (a)
Mealy machine because the output Z depends on the input X as well as the present state
135 (a) 135 (b) ZX A
B C 00 01 11 1000
01
11
10
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
Note Not all Karnaugh map entries are needed See FLD p 654 for the state table
135 (c - d) See FLD p 654 for solutions
After a rising clock edge it takes 4 ns for the flip-flop outputs to change Then the ROM will take 8 ns to respond to the new flip-flop outputs The ROM outputs must be correct at the flip-flop inputs for at least the setup time of 2 ns before the next rising clock edge So the minimum clock period is (4 + 8 + 2) ns = 14 ns
136 (b) The correct output sequence is 0101 See FLD p 655 for the timing diagram
136 (c) Read the state transition table from ROM truth table See FLD p 655 for the state graph and table
Present State
Next State (Q1
+Q2
+) ZQ1Q2 X = 0 X = 1 X = 0 X = 1
00 10 10 0 001 00 11 0 010 11 01 0 111 01 11 1 1
Alternate solution Using Karnaugh map order swap states S2 and S3 in the graph and table
StatePresent State
Next State (Q1
+Q2+) Z
Q1Q2 X = 0 X = 1 X = 0 X = 1S0 00 00 01 0 1S1 01 01 10 1 0S2 11 11 00 1 0 S3 10 10 00 0 1
Alternate solution Swap states S2 and S3
Q1+
XQ1 Q2 0 1
00
01
11
10
0
0
1
1
0
1
0
0
Q2+
XQ1 Q2 0 1
00
01
11
10
0
1
0
1
1
0
0
0
Z
XQ1 Q2 0 1
00
01
11
10
0
1
0
1
1
0
1
0
Notice that Z depends on the input X so this is a Mealy machineQ1
+ = J1Q1 + K1Q1 = XQ1Q2 + XQ1Q2
+ = J2Q2 + K2Q2 = XQ1Q2 + XQ2Z = Q2 oplus X = XQ2 + XQ2
92 93
138 (a)
ClockX
Z
Q1Q2
false
11
S0
01
00
S2
S3 S110
00
11
10
01
137 (a) (contd)
StatePresent State
Next StateX1X2 Z
Q1Q2 00 01 11 10S0 00 00 01 01 01 0S1 01 01 01 11 11 0S2 11 11 11 10 11 0S3 10 00 00 10 00 1
Clock
X
X2
1
Q1
Q2
Z
138 (b)
Correct output Z = 0 0 0 1 1 0
139
ClockX
Z
Q1Q2
false
Q3
Correct output Z = 1 0 1 1
Q1+
X1 X2Q1 Q2 00 01 11 10
00
01
11
10
0
0
0
1
0
0
0
1
0
1
0
1
0
1
1
1
Q2+
X1 X2Q1 Q2 00 01 11 10
00
01
11
10
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0 Z
Q1Q2 0 1
0
1
0
0
1
0
Notice that Z does not depend on this input X so this is a Moore machine Q1
+ = X1X2Q1 + Q1Q2 + X1Q2Q2
+ = Q1 (X1 + X2) + Q2 (X1 + X2) = X1Q1 + X2Q1 + X1Q2 + X2Q2Z = Q1Q2
S00
S10
S31
S20
00
01 10 11
00 01
10 1100 01 10
11
11 00 01 10
137 (b)
94 95
1310 ClockX
Z
Q1Q2
false
Q3
false
Correct output Z = 0 0 1 1
1311 (a)X Q1
Q2 Q3 00 01 11 1000
01
11
10
0
0
1
0
0
0
1
0
1
1
1
1
0
0
1
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
Q +3D =3 Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 101 0 1S1 001 011 111 0 1S2 010 110 101 1 0S3 011 010 111 1 0S4 100 001 001 0 1S5 101 011 011 0 1S6 110 110 101 1 0S7 111 010 011 1 0
S3 S6
S4
S1
S7 S2
S0
S5
00
11
11
10
01
01
10
01
01
10
10
0011
0011
00
ClockX
Z
Q1Q2
false
Q3
1311 (b) 1311 (c)
1311 (d)
From diagram 0 1 (0) 1 0 1From graph 0 1 1 0 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
94 95
1312 (a)
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Q +3D =3
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 100 011 1 0S1 001 000 011 0 1S2 010 100 000 1 0S3 011 000 000 0 1S4 100 110 011 1 0S5 101 000 011 0 1S6 110 111 011 1 0S7 111 001 001 0 1
Q
3
Q
1
Q
2
Z
false
X
Clock
Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1312 (c)
1312 (d)
From diagram 1 0 1 (0) 1 1From graph 1 0 1 1 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
1312 (b)
1313 Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 1 Q1
+Q2+ = 01
2 Q1Q2 = 01 X = 0 rArr Z = 0 X = 1 rArr Z = 1 Q1+Q2
+ = 113 Q1Q2 = 11 X = 1 rArr Z = 1 X = 0 rArr Z = 0 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 005 Q1Q2 = 00 X = 1 rArr Z = 0 Q1
+Q2+ = 10
6 Q1Q2 = 10 X = 1 rArr (Z = 0) X = 0 rArr (Z = 1) Q1+Q2
+ = 117 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr (Z = 1) Q1
+Q2+ = 01
8 Q1Q2 = 01 X = 1 rArr (Z = 1) X = 0 rArr (Z = 0) Q1+Q2
+ = 009 Q1Q2 = 00 X = 0 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 01 10 1 001 00 11 0 110 11 00 1 011 10 01 0 1
00
01
10
01
1100
10
11
01
11
00
10
S2
S4
S3
S1 S7
S0
S5
00
11
01
10
01
10
10
0011 S6
10
01
0011
11
00
01
96 97
1314
1315
Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 0 Q1
+Q2+ = 10
2 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 013 Q1Q2 = 01 X = 1 rArr Z = 0 X = 0 rArr Z = 1 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr (Z = 1) Q1+Q2
+ = 115 Q1Q2 = 11 X = 0 rArr Z = 0 Q1
+Q2+ = 11
6 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr Z = 1 Q1+Q2
+ = 017 Q1Q2 = 01 X = 1 rArr (Z = 0) Q1
+Q2+ = 00
8 Q1Q2 = 00 X = 1 rArr Z = 1 Q1+Q2
+ = 119 Q1Q2 = 11 X = 1 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 10 11 0 101 10 00 1 010 11 01 1 011 11 01 0 1
0010
11
01
10
11
01
10
00 0
1
11
00
Clock Cycle Information Gathered1 Q1Q2 = 00 X1X2 = 01 rArr Z1Z2 = 10 Q1
+Q2+ = 01
2 Q1Q2 = 01 X1X2 = 01 rArr Z1Z2 = 01 X1X2 = 10 rArr Z1Z2 = 10 Q1+Q2
+ = 103 Q1Q2 = 10 X1X2 = 10 rArr Z1Z2 = 00 X1X2 = 11 rArr Z1Z2 = 00 Q1
+Q2+ = 01
4 Q1Q2 = 01 X1X2 = 11 rArr Z1Z2 = 11 X1X2 = 01 rArr (Z1Z2 = 01) Q1+Q2
+ = 115 Q1Q2 = 11 X1X2 = 01 rArr Z1Z2 = 01
Note When Q1Q2 = 01 the outputs Z1Z2 vary depending on the inputs X1X2 so this is a Mealy machine
Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 11 10 00 01 11 1000 01 10 01 11 10 01 11 1011 01 10 01 00 00
1316 (a)
X2
Clock
Q1
Q2
Z1
X1
Z2
falseCorrect output Z1Z2 = 10 10 00 01
96 97
00
10
01
11
0010
0110
10101110
00001000
00001001
0100
1101
100111
11
01001100
00000110
1316 (b) Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 10 11 00 01 10 1100 00 00 01 01 10 10 10 1001 11 11 10 10 00 10 01 1110 11 00 11 00 00 00 01 0111 10 01 10 01 00 00 00 00
1317
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 011 0 0S1 001 010 011 0 0S2 010 001 011 0 1S3 011 100 000 0 0S4 100 011 000 0 1
Clock
X
Q
3
Q
1
Q
2
Z
1318 (a)
Clock
X
A
B
JA
KA
5ns 10ns 15ns 20ns 25ns 30ns 35ns
JB = KB
Z
Correct output Z = 0 0 1 0 0 1
All flip-flop inputs are stable for more than the setup time before each falling clock edge So the circuit is operating properly
1318 (b) If X is changed early enoughMinimum clock period = Flip-flop propagation delay + Two NAND-gate delays + Setup time = 4 + (3 + 3) + 2 = 12 nsX can change as late as 8 ns (two NAND-gate delays plus the setup time) before the next falling edge without causing improper operation
Transition table using a straight binary state assignment
98
1319Clock
A
B
C
X
Z
false
Correct output Z = 1 0 1 0 1
A+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
B+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
C+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
ZX A
B C 00 01 11 1000
01
11
10
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
S0
S3
S1
S2
0100
0110
0100
1000
10111100
1100
000110011100
1000
0000
1100
0011
1000
0010
Deriving the State TableJK flip-flop equation Q+ = JQ + KQthere4 A+ = (XC + XC) A + XA
[As JA = XC + XC KA = X Q = A]= AXC + AXC + XA
Similarly B+ = XC + XA + XACC+ = 0 C + (XBA) C = C + XBAZ = XB + XC + XBA
From the Karnaugh maps we can get the state table that follows
StatePresent State
Next State (A+B+C+) Z
ABC X = 0 X = 1 X = 0 X = 1S0 000 000 110 1 0S1 001 111 001 0 0S2 010 000 110 1 1S3 011 111 001 0 1S4 100 100 011 1 0S5 101 101 011 1 0S6 110 100 010 1 1S7 111 101 011 0 1
R = X2 (X1 + B)S = X2 (X1 + B)A+ = A[(X2 ) (X1 + B)] + X2 (X1 + B)
= A (X2 + X1B) + X2X1 + X2BA+ = AX2 + AX1B + X2X1 + X2B
T = X1BA + X1BAB+ = BT + BT
= B(X1BA + X1BA) B (X1BA + X1BA)= B [(X1BA) (X1BA)] + X1BA= B [(X1 + B + A) (X1 + B + A)] + X1BA = (BX1 + BA) (X1 + B + A) + X1BA= BX1 + BX1 + BX1A + BAX1 + BA + X1BA= X1B(1 + 1 + A + A) + A (B + X1B)= X1B + AB + X1A
1320
StatePresent State
A+B+
X1X2=Z1Z2
X1X2=
AB 00 01 10 11 00 01 10 11S0 00 11 01 10 00 10 10 00 00S1 01 11 01 01 01 11 00 11 00S2 10 10 00 10 10 01 00 01 00S3 11 10 00 11 01 00 00 00 00
1320 (contd)
92 93
138 (a)
ClockX
Z
Q1Q2
false
11
S0
01
00
S2
S3 S110
00
11
10
01
137 (a) (contd)
StatePresent State
Next StateX1X2 Z
Q1Q2 00 01 11 10S0 00 00 01 01 01 0S1 01 01 01 11 11 0S2 11 11 11 10 11 0S3 10 00 00 10 00 1
Clock
X
X2
1
Q1
Q2
Z
138 (b)
Correct output Z = 0 0 0 1 1 0
139
ClockX
Z
Q1Q2
false
Q3
Correct output Z = 1 0 1 1
Q1+
X1 X2Q1 Q2 00 01 11 10
00
01
11
10
0
0
0
1
0
0
0
1
0
1
0
1
0
1
1
1
Q2+
X1 X2Q1 Q2 00 01 11 10
00
01
11
10
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0 Z
Q1Q2 0 1
0
1
0
0
1
0
Notice that Z does not depend on this input X so this is a Moore machine Q1
+ = X1X2Q1 + Q1Q2 + X1Q2Q2
+ = Q1 (X1 + X2) + Q2 (X1 + X2) = X1Q1 + X2Q1 + X1Q2 + X2Q2Z = Q1Q2
S00
S10
S31
S20
00
01 10 11
00 01
10 1100 01 10
11
11 00 01 10
137 (b)
94 95
1310 ClockX
Z
Q1Q2
false
Q3
false
Correct output Z = 0 0 1 1
1311 (a)X Q1
Q2 Q3 00 01 11 1000
01
11
10
0
0
1
0
0
0
1
0
1
1
1
1
0
0
1
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
Q +3D =3 Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 101 0 1S1 001 011 111 0 1S2 010 110 101 1 0S3 011 010 111 1 0S4 100 001 001 0 1S5 101 011 011 0 1S6 110 110 101 1 0S7 111 010 011 1 0
S3 S6
S4
S1
S7 S2
S0
S5
00
11
11
10
01
01
10
01
01
10
10
0011
0011
00
ClockX
Z
Q1Q2
false
Q3
1311 (b) 1311 (c)
1311 (d)
From diagram 0 1 (0) 1 0 1From graph 0 1 1 0 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
94 95
1312 (a)
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Q +3D =3
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 100 011 1 0S1 001 000 011 0 1S2 010 100 000 1 0S3 011 000 000 0 1S4 100 110 011 1 0S5 101 000 011 0 1S6 110 111 011 1 0S7 111 001 001 0 1
Q
3
Q
1
Q
2
Z
false
X
Clock
Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1312 (c)
1312 (d)
From diagram 1 0 1 (0) 1 1From graph 1 0 1 1 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
1312 (b)
1313 Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 1 Q1
+Q2+ = 01
2 Q1Q2 = 01 X = 0 rArr Z = 0 X = 1 rArr Z = 1 Q1+Q2
+ = 113 Q1Q2 = 11 X = 1 rArr Z = 1 X = 0 rArr Z = 0 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 005 Q1Q2 = 00 X = 1 rArr Z = 0 Q1
+Q2+ = 10
6 Q1Q2 = 10 X = 1 rArr (Z = 0) X = 0 rArr (Z = 1) Q1+Q2
+ = 117 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr (Z = 1) Q1
+Q2+ = 01
8 Q1Q2 = 01 X = 1 rArr (Z = 1) X = 0 rArr (Z = 0) Q1+Q2
+ = 009 Q1Q2 = 00 X = 0 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 01 10 1 001 00 11 0 110 11 00 1 011 10 01 0 1
00
01
10
01
1100
10
11
01
11
00
10
S2
S4
S3
S1 S7
S0
S5
00
11
01
10
01
10
10
0011 S6
10
01
0011
11
00
01
96 97
1314
1315
Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 0 Q1
+Q2+ = 10
2 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 013 Q1Q2 = 01 X = 1 rArr Z = 0 X = 0 rArr Z = 1 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr (Z = 1) Q1+Q2
+ = 115 Q1Q2 = 11 X = 0 rArr Z = 0 Q1
+Q2+ = 11
6 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr Z = 1 Q1+Q2
+ = 017 Q1Q2 = 01 X = 1 rArr (Z = 0) Q1
+Q2+ = 00
8 Q1Q2 = 00 X = 1 rArr Z = 1 Q1+Q2
+ = 119 Q1Q2 = 11 X = 1 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 10 11 0 101 10 00 1 010 11 01 1 011 11 01 0 1
0010
11
01
10
11
01
10
00 0
1
11
00
Clock Cycle Information Gathered1 Q1Q2 = 00 X1X2 = 01 rArr Z1Z2 = 10 Q1
+Q2+ = 01
2 Q1Q2 = 01 X1X2 = 01 rArr Z1Z2 = 01 X1X2 = 10 rArr Z1Z2 = 10 Q1+Q2
+ = 103 Q1Q2 = 10 X1X2 = 10 rArr Z1Z2 = 00 X1X2 = 11 rArr Z1Z2 = 00 Q1
+Q2+ = 01
4 Q1Q2 = 01 X1X2 = 11 rArr Z1Z2 = 11 X1X2 = 01 rArr (Z1Z2 = 01) Q1+Q2
+ = 115 Q1Q2 = 11 X1X2 = 01 rArr Z1Z2 = 01
Note When Q1Q2 = 01 the outputs Z1Z2 vary depending on the inputs X1X2 so this is a Mealy machine
Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 11 10 00 01 11 1000 01 10 01 11 10 01 11 1011 01 10 01 00 00
1316 (a)
X2
Clock
Q1
Q2
Z1
X1
Z2
falseCorrect output Z1Z2 = 10 10 00 01
96 97
00
10
01
11
0010
0110
10101110
00001000
00001001
0100
1101
100111
11
01001100
00000110
1316 (b) Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 10 11 00 01 10 1100 00 00 01 01 10 10 10 1001 11 11 10 10 00 10 01 1110 11 00 11 00 00 00 01 0111 10 01 10 01 00 00 00 00
1317
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 011 0 0S1 001 010 011 0 0S2 010 001 011 0 1S3 011 100 000 0 0S4 100 011 000 0 1
Clock
X
Q
3
Q
1
Q
2
Z
1318 (a)
Clock
X
A
B
JA
KA
5ns 10ns 15ns 20ns 25ns 30ns 35ns
JB = KB
Z
Correct output Z = 0 0 1 0 0 1
All flip-flop inputs are stable for more than the setup time before each falling clock edge So the circuit is operating properly
1318 (b) If X is changed early enoughMinimum clock period = Flip-flop propagation delay + Two NAND-gate delays + Setup time = 4 + (3 + 3) + 2 = 12 nsX can change as late as 8 ns (two NAND-gate delays plus the setup time) before the next falling edge without causing improper operation
Transition table using a straight binary state assignment
98
1319Clock
A
B
C
X
Z
false
Correct output Z = 1 0 1 0 1
A+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
B+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
C+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
ZX A
B C 00 01 11 1000
01
11
10
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
S0
S3
S1
S2
0100
0110
0100
1000
10111100
1100
000110011100
1000
0000
1100
0011
1000
0010
Deriving the State TableJK flip-flop equation Q+ = JQ + KQthere4 A+ = (XC + XC) A + XA
[As JA = XC + XC KA = X Q = A]= AXC + AXC + XA
Similarly B+ = XC + XA + XACC+ = 0 C + (XBA) C = C + XBAZ = XB + XC + XBA
From the Karnaugh maps we can get the state table that follows
StatePresent State
Next State (A+B+C+) Z
ABC X = 0 X = 1 X = 0 X = 1S0 000 000 110 1 0S1 001 111 001 0 0S2 010 000 110 1 1S3 011 111 001 0 1S4 100 100 011 1 0S5 101 101 011 1 0S6 110 100 010 1 1S7 111 101 011 0 1
R = X2 (X1 + B)S = X2 (X1 + B)A+ = A[(X2 ) (X1 + B)] + X2 (X1 + B)
= A (X2 + X1B) + X2X1 + X2BA+ = AX2 + AX1B + X2X1 + X2B
T = X1BA + X1BAB+ = BT + BT
= B(X1BA + X1BA) B (X1BA + X1BA)= B [(X1BA) (X1BA)] + X1BA= B [(X1 + B + A) (X1 + B + A)] + X1BA = (BX1 + BA) (X1 + B + A) + X1BA= BX1 + BX1 + BX1A + BAX1 + BA + X1BA= X1B(1 + 1 + A + A) + A (B + X1B)= X1B + AB + X1A
1320
StatePresent State
A+B+
X1X2=Z1Z2
X1X2=
AB 00 01 10 11 00 01 10 11S0 00 11 01 10 00 10 10 00 00S1 01 11 01 01 01 11 00 11 00S2 10 10 00 10 10 01 00 01 00S3 11 10 00 11 01 00 00 00 00
1320 (contd)
94 95
1310 ClockX
Z
Q1Q2
false
Q3
false
Correct output Z = 0 0 1 1
1311 (a)X Q1
Q2 Q3 00 01 11 1000
01
11
10
0
0
1
0
0
0
1
0
1
1
1
1
0
0
1
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
Q +3D =3 Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 101 0 1S1 001 011 111 0 1S2 010 110 101 1 0S3 011 010 111 1 0S4 100 001 001 0 1S5 101 011 011 0 1S6 110 110 101 1 0S7 111 010 011 1 0
S3 S6
S4
S1
S7 S2
S0
S5
00
11
11
10
01
01
10
01
01
10
10
0011
0011
00
ClockX
Z
Q1Q2
false
Q3
1311 (b) 1311 (c)
1311 (d)
From diagram 0 1 (0) 1 0 1From graph 0 1 1 0 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
94 95
1312 (a)
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Q +3D =3
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 100 011 1 0S1 001 000 011 0 1S2 010 100 000 1 0S3 011 000 000 0 1S4 100 110 011 1 0S5 101 000 011 0 1S6 110 111 011 1 0S7 111 001 001 0 1
Q
3
Q
1
Q
2
Z
false
X
Clock
Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1312 (c)
1312 (d)
From diagram 1 0 1 (0) 1 1From graph 1 0 1 1 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
1312 (b)
1313 Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 1 Q1
+Q2+ = 01
2 Q1Q2 = 01 X = 0 rArr Z = 0 X = 1 rArr Z = 1 Q1+Q2
+ = 113 Q1Q2 = 11 X = 1 rArr Z = 1 X = 0 rArr Z = 0 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 005 Q1Q2 = 00 X = 1 rArr Z = 0 Q1
+Q2+ = 10
6 Q1Q2 = 10 X = 1 rArr (Z = 0) X = 0 rArr (Z = 1) Q1+Q2
+ = 117 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr (Z = 1) Q1
+Q2+ = 01
8 Q1Q2 = 01 X = 1 rArr (Z = 1) X = 0 rArr (Z = 0) Q1+Q2
+ = 009 Q1Q2 = 00 X = 0 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 01 10 1 001 00 11 0 110 11 00 1 011 10 01 0 1
00
01
10
01
1100
10
11
01
11
00
10
S2
S4
S3
S1 S7
S0
S5
00
11
01
10
01
10
10
0011 S6
10
01
0011
11
00
01
96 97
1314
1315
Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 0 Q1
+Q2+ = 10
2 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 013 Q1Q2 = 01 X = 1 rArr Z = 0 X = 0 rArr Z = 1 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr (Z = 1) Q1+Q2
+ = 115 Q1Q2 = 11 X = 0 rArr Z = 0 Q1
+Q2+ = 11
6 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr Z = 1 Q1+Q2
+ = 017 Q1Q2 = 01 X = 1 rArr (Z = 0) Q1
+Q2+ = 00
8 Q1Q2 = 00 X = 1 rArr Z = 1 Q1+Q2
+ = 119 Q1Q2 = 11 X = 1 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 10 11 0 101 10 00 1 010 11 01 1 011 11 01 0 1
0010
11
01
10
11
01
10
00 0
1
11
00
Clock Cycle Information Gathered1 Q1Q2 = 00 X1X2 = 01 rArr Z1Z2 = 10 Q1
+Q2+ = 01
2 Q1Q2 = 01 X1X2 = 01 rArr Z1Z2 = 01 X1X2 = 10 rArr Z1Z2 = 10 Q1+Q2
+ = 103 Q1Q2 = 10 X1X2 = 10 rArr Z1Z2 = 00 X1X2 = 11 rArr Z1Z2 = 00 Q1
+Q2+ = 01
4 Q1Q2 = 01 X1X2 = 11 rArr Z1Z2 = 11 X1X2 = 01 rArr (Z1Z2 = 01) Q1+Q2
+ = 115 Q1Q2 = 11 X1X2 = 01 rArr Z1Z2 = 01
Note When Q1Q2 = 01 the outputs Z1Z2 vary depending on the inputs X1X2 so this is a Mealy machine
Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 11 10 00 01 11 1000 01 10 01 11 10 01 11 1011 01 10 01 00 00
1316 (a)
X2
Clock
Q1
Q2
Z1
X1
Z2
falseCorrect output Z1Z2 = 10 10 00 01
96 97
00
10
01
11
0010
0110
10101110
00001000
00001001
0100
1101
100111
11
01001100
00000110
1316 (b) Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 10 11 00 01 10 1100 00 00 01 01 10 10 10 1001 11 11 10 10 00 10 01 1110 11 00 11 00 00 00 01 0111 10 01 10 01 00 00 00 00
1317
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 011 0 0S1 001 010 011 0 0S2 010 001 011 0 1S3 011 100 000 0 0S4 100 011 000 0 1
Clock
X
Q
3
Q
1
Q
2
Z
1318 (a)
Clock
X
A
B
JA
KA
5ns 10ns 15ns 20ns 25ns 30ns 35ns
JB = KB
Z
Correct output Z = 0 0 1 0 0 1
All flip-flop inputs are stable for more than the setup time before each falling clock edge So the circuit is operating properly
1318 (b) If X is changed early enoughMinimum clock period = Flip-flop propagation delay + Two NAND-gate delays + Setup time = 4 + (3 + 3) + 2 = 12 nsX can change as late as 8 ns (two NAND-gate delays plus the setup time) before the next falling edge without causing improper operation
Transition table using a straight binary state assignment
98
1319Clock
A
B
C
X
Z
false
Correct output Z = 1 0 1 0 1
A+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
B+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
C+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
ZX A
B C 00 01 11 1000
01
11
10
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
S0
S3
S1
S2
0100
0110
0100
1000
10111100
1100
000110011100
1000
0000
1100
0011
1000
0010
Deriving the State TableJK flip-flop equation Q+ = JQ + KQthere4 A+ = (XC + XC) A + XA
[As JA = XC + XC KA = X Q = A]= AXC + AXC + XA
Similarly B+ = XC + XA + XACC+ = 0 C + (XBA) C = C + XBAZ = XB + XC + XBA
From the Karnaugh maps we can get the state table that follows
StatePresent State
Next State (A+B+C+) Z
ABC X = 0 X = 1 X = 0 X = 1S0 000 000 110 1 0S1 001 111 001 0 0S2 010 000 110 1 1S3 011 111 001 0 1S4 100 100 011 1 0S5 101 101 011 1 0S6 110 100 010 1 1S7 111 101 011 0 1
R = X2 (X1 + B)S = X2 (X1 + B)A+ = A[(X2 ) (X1 + B)] + X2 (X1 + B)
= A (X2 + X1B) + X2X1 + X2BA+ = AX2 + AX1B + X2X1 + X2B
T = X1BA + X1BAB+ = BT + BT
= B(X1BA + X1BA) B (X1BA + X1BA)= B [(X1BA) (X1BA)] + X1BA= B [(X1 + B + A) (X1 + B + A)] + X1BA = (BX1 + BA) (X1 + B + A) + X1BA= BX1 + BX1 + BX1A + BAX1 + BA + X1BA= X1B(1 + 1 + A + A) + A (B + X1B)= X1B + AB + X1A
1320
StatePresent State
A+B+
X1X2=Z1Z2
X1X2=
AB 00 01 10 11 00 01 10 11S0 00 11 01 10 00 10 10 00 00S1 01 11 01 01 01 11 00 11 00S2 10 10 00 10 10 01 00 01 00S3 11 10 00 11 01 00 00 00 00
1320 (contd)
94 95
1312 (a)
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Q +1D =1
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
Q +2D =2
X Q1Q2 Q3 00 01 11 10
00
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Q +3D =3
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 100 011 1 0S1 001 000 011 0 1S2 010 100 000 1 0S3 011 000 000 0 1S4 100 110 011 1 0S5 101 000 011 0 1S6 110 111 011 1 0S7 111 001 001 0 1
Q
3
Q
1
Q
2
Z
false
X
Clock
Z
X Q1Q2 Q3 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1312 (c)
1312 (d)
From diagram 1 0 1 (0) 1 1From graph 1 0 1 1 1
(they are the same except for the false output)
Change the input on the falling edge of the clock (assuming negligible circuit delays)
1312 (b)
1313 Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 1 Q1
+Q2+ = 01
2 Q1Q2 = 01 X = 0 rArr Z = 0 X = 1 rArr Z = 1 Q1+Q2
+ = 113 Q1Q2 = 11 X = 1 rArr Z = 1 X = 0 rArr Z = 0 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 005 Q1Q2 = 00 X = 1 rArr Z = 0 Q1
+Q2+ = 10
6 Q1Q2 = 10 X = 1 rArr (Z = 0) X = 0 rArr (Z = 1) Q1+Q2
+ = 117 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr (Z = 1) Q1
+Q2+ = 01
8 Q1Q2 = 01 X = 1 rArr (Z = 1) X = 0 rArr (Z = 0) Q1+Q2
+ = 009 Q1Q2 = 00 X = 0 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 01 10 1 001 00 11 0 110 11 00 1 011 10 01 0 1
00
01
10
01
1100
10
11
01
11
00
10
S2
S4
S3
S1 S7
S0
S5
00
11
01
10
01
10
10
0011 S6
10
01
0011
11
00
01
96 97
1314
1315
Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 0 Q1
+Q2+ = 10
2 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 013 Q1Q2 = 01 X = 1 rArr Z = 0 X = 0 rArr Z = 1 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr (Z = 1) Q1+Q2
+ = 115 Q1Q2 = 11 X = 0 rArr Z = 0 Q1
+Q2+ = 11
6 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr Z = 1 Q1+Q2
+ = 017 Q1Q2 = 01 X = 1 rArr (Z = 0) Q1
+Q2+ = 00
8 Q1Q2 = 00 X = 1 rArr Z = 1 Q1+Q2
+ = 119 Q1Q2 = 11 X = 1 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 10 11 0 101 10 00 1 010 11 01 1 011 11 01 0 1
0010
11
01
10
11
01
10
00 0
1
11
00
Clock Cycle Information Gathered1 Q1Q2 = 00 X1X2 = 01 rArr Z1Z2 = 10 Q1
+Q2+ = 01
2 Q1Q2 = 01 X1X2 = 01 rArr Z1Z2 = 01 X1X2 = 10 rArr Z1Z2 = 10 Q1+Q2
+ = 103 Q1Q2 = 10 X1X2 = 10 rArr Z1Z2 = 00 X1X2 = 11 rArr Z1Z2 = 00 Q1
+Q2+ = 01
4 Q1Q2 = 01 X1X2 = 11 rArr Z1Z2 = 11 X1X2 = 01 rArr (Z1Z2 = 01) Q1+Q2
+ = 115 Q1Q2 = 11 X1X2 = 01 rArr Z1Z2 = 01
Note When Q1Q2 = 01 the outputs Z1Z2 vary depending on the inputs X1X2 so this is a Mealy machine
Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 11 10 00 01 11 1000 01 10 01 11 10 01 11 1011 01 10 01 00 00
1316 (a)
X2
Clock
Q1
Q2
Z1
X1
Z2
falseCorrect output Z1Z2 = 10 10 00 01
96 97
00
10
01
11
0010
0110
10101110
00001000
00001001
0100
1101
100111
11
01001100
00000110
1316 (b) Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 10 11 00 01 10 1100 00 00 01 01 10 10 10 1001 11 11 10 10 00 10 01 1110 11 00 11 00 00 00 01 0111 10 01 10 01 00 00 00 00
1317
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 011 0 0S1 001 010 011 0 0S2 010 001 011 0 1S3 011 100 000 0 0S4 100 011 000 0 1
Clock
X
Q
3
Q
1
Q
2
Z
1318 (a)
Clock
X
A
B
JA
KA
5ns 10ns 15ns 20ns 25ns 30ns 35ns
JB = KB
Z
Correct output Z = 0 0 1 0 0 1
All flip-flop inputs are stable for more than the setup time before each falling clock edge So the circuit is operating properly
1318 (b) If X is changed early enoughMinimum clock period = Flip-flop propagation delay + Two NAND-gate delays + Setup time = 4 + (3 + 3) + 2 = 12 nsX can change as late as 8 ns (two NAND-gate delays plus the setup time) before the next falling edge without causing improper operation
Transition table using a straight binary state assignment
98
1319Clock
A
B
C
X
Z
false
Correct output Z = 1 0 1 0 1
A+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
B+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
C+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
ZX A
B C 00 01 11 1000
01
11
10
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
S0
S3
S1
S2
0100
0110
0100
1000
10111100
1100
000110011100
1000
0000
1100
0011
1000
0010
Deriving the State TableJK flip-flop equation Q+ = JQ + KQthere4 A+ = (XC + XC) A + XA
[As JA = XC + XC KA = X Q = A]= AXC + AXC + XA
Similarly B+ = XC + XA + XACC+ = 0 C + (XBA) C = C + XBAZ = XB + XC + XBA
From the Karnaugh maps we can get the state table that follows
StatePresent State
Next State (A+B+C+) Z
ABC X = 0 X = 1 X = 0 X = 1S0 000 000 110 1 0S1 001 111 001 0 0S2 010 000 110 1 1S3 011 111 001 0 1S4 100 100 011 1 0S5 101 101 011 1 0S6 110 100 010 1 1S7 111 101 011 0 1
R = X2 (X1 + B)S = X2 (X1 + B)A+ = A[(X2 ) (X1 + B)] + X2 (X1 + B)
= A (X2 + X1B) + X2X1 + X2BA+ = AX2 + AX1B + X2X1 + X2B
T = X1BA + X1BAB+ = BT + BT
= B(X1BA + X1BA) B (X1BA + X1BA)= B [(X1BA) (X1BA)] + X1BA= B [(X1 + B + A) (X1 + B + A)] + X1BA = (BX1 + BA) (X1 + B + A) + X1BA= BX1 + BX1 + BX1A + BAX1 + BA + X1BA= X1B(1 + 1 + A + A) + A (B + X1B)= X1B + AB + X1A
1320
StatePresent State
A+B+
X1X2=Z1Z2
X1X2=
AB 00 01 10 11 00 01 10 11S0 00 11 01 10 00 10 10 00 00S1 01 11 01 01 01 11 00 11 00S2 10 10 00 10 10 01 00 01 00S3 11 10 00 11 01 00 00 00 00
1320 (contd)
96 97
1314
1315
Clock Cycle Information Gathered1 Q1Q2 = 00 X = 0 rArr Z = 0 Q1
+Q2+ = 10
2 Q1Q2 = 10 X = 0 rArr Z = 1 X = 1 rArr Z = 0 Q1+Q2
+ = 013 Q1Q2 = 01 X = 1 rArr Z = 0 X = 0 rArr Z = 1 Q1
+Q2+ = 10
4 Q1Q2 = 10 X = 0 rArr (Z = 1) Q1+Q2
+ = 115 Q1Q2 = 11 X = 0 rArr Z = 0 Q1
+Q2+ = 11
6 Q1Q2 = 11 X = 0 rArr (Z = 0) X = 1 rArr Z = 1 Q1+Q2
+ = 017 Q1Q2 = 01 X = 1 rArr (Z = 0) Q1
+Q2+ = 00
8 Q1Q2 = 00 X = 1 rArr Z = 1 Q1+Q2
+ = 119 Q1Q2 = 11 X = 1 rArr (Z = 1)
Note Information inside parentheses was already obtained in a previous clock cycle
Present State
Next State (Q1
+Q2+) Z
0 1Q1Q2 X = 0 X = 100 10 11 0 101 10 00 1 010 11 01 1 011 11 01 0 1
0010
11
01
10
11
01
10
00 0
1
11
00
Clock Cycle Information Gathered1 Q1Q2 = 00 X1X2 = 01 rArr Z1Z2 = 10 Q1
+Q2+ = 01
2 Q1Q2 = 01 X1X2 = 01 rArr Z1Z2 = 01 X1X2 = 10 rArr Z1Z2 = 10 Q1+Q2
+ = 103 Q1Q2 = 10 X1X2 = 10 rArr Z1Z2 = 00 X1X2 = 11 rArr Z1Z2 = 00 Q1
+Q2+ = 01
4 Q1Q2 = 01 X1X2 = 11 rArr Z1Z2 = 11 X1X2 = 01 rArr (Z1Z2 = 01) Q1+Q2
+ = 115 Q1Q2 = 11 X1X2 = 01 rArr Z1Z2 = 01
Note When Q1Q2 = 01 the outputs Z1Z2 vary depending on the inputs X1X2 so this is a Mealy machine
Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 11 10 00 01 11 1000 01 10 01 11 10 01 11 1011 01 10 01 00 00
1316 (a)
X2
Clock
Q1
Q2
Z1
X1
Z2
falseCorrect output Z1Z2 = 10 10 00 01
96 97
00
10
01
11
0010
0110
10101110
00001000
00001001
0100
1101
100111
11
01001100
00000110
1316 (b) Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 10 11 00 01 10 1100 00 00 01 01 10 10 10 1001 11 11 10 10 00 10 01 1110 11 00 11 00 00 00 01 0111 10 01 10 01 00 00 00 00
1317
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 011 0 0S1 001 010 011 0 0S2 010 001 011 0 1S3 011 100 000 0 0S4 100 011 000 0 1
Clock
X
Q
3
Q
1
Q
2
Z
1318 (a)
Clock
X
A
B
JA
KA
5ns 10ns 15ns 20ns 25ns 30ns 35ns
JB = KB
Z
Correct output Z = 0 0 1 0 0 1
All flip-flop inputs are stable for more than the setup time before each falling clock edge So the circuit is operating properly
1318 (b) If X is changed early enoughMinimum clock period = Flip-flop propagation delay + Two NAND-gate delays + Setup time = 4 + (3 + 3) + 2 = 12 nsX can change as late as 8 ns (two NAND-gate delays plus the setup time) before the next falling edge without causing improper operation
Transition table using a straight binary state assignment
98
1319Clock
A
B
C
X
Z
false
Correct output Z = 1 0 1 0 1
A+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
B+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
C+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
ZX A
B C 00 01 11 1000
01
11
10
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
S0
S3
S1
S2
0100
0110
0100
1000
10111100
1100
000110011100
1000
0000
1100
0011
1000
0010
Deriving the State TableJK flip-flop equation Q+ = JQ + KQthere4 A+ = (XC + XC) A + XA
[As JA = XC + XC KA = X Q = A]= AXC + AXC + XA
Similarly B+ = XC + XA + XACC+ = 0 C + (XBA) C = C + XBAZ = XB + XC + XBA
From the Karnaugh maps we can get the state table that follows
StatePresent State
Next State (A+B+C+) Z
ABC X = 0 X = 1 X = 0 X = 1S0 000 000 110 1 0S1 001 111 001 0 0S2 010 000 110 1 1S3 011 111 001 0 1S4 100 100 011 1 0S5 101 101 011 1 0S6 110 100 010 1 1S7 111 101 011 0 1
R = X2 (X1 + B)S = X2 (X1 + B)A+ = A[(X2 ) (X1 + B)] + X2 (X1 + B)
= A (X2 + X1B) + X2X1 + X2BA+ = AX2 + AX1B + X2X1 + X2B
T = X1BA + X1BAB+ = BT + BT
= B(X1BA + X1BA) B (X1BA + X1BA)= B [(X1BA) (X1BA)] + X1BA= B [(X1 + B + A) (X1 + B + A)] + X1BA = (BX1 + BA) (X1 + B + A) + X1BA= BX1 + BX1 + BX1A + BAX1 + BA + X1BA= X1B(1 + 1 + A + A) + A (B + X1B)= X1B + AB + X1A
1320
StatePresent State
A+B+
X1X2=Z1Z2
X1X2=
AB 00 01 10 11 00 01 10 11S0 00 11 01 10 00 10 10 00 00S1 01 11 01 01 01 11 00 11 00S2 10 10 00 10 10 01 00 01 00S3 11 10 00 11 01 00 00 00 00
1320 (contd)
96 97
00
10
01
11
0010
0110
10101110
00001000
00001001
0100
1101
100111
11
01001100
00000110
1316 (b) Present State
Q1+Q2
+
X1X2=Z1Z2
X1X2=
Q1Q2 00 01 10 11 00 01 10 1100 00 00 01 01 10 10 10 1001 11 11 10 10 00 10 01 1110 11 00 11 00 00 00 01 0111 10 01 10 01 00 00 00 00
1317
StatePresent State
Next State (Q1
+Q2+Q3
+) ZQ1Q2Q3 X = 0 X = 1 X = 0 X = 1
S0 000 001 011 0 0S1 001 010 011 0 0S2 010 001 011 0 1S3 011 100 000 0 0S4 100 011 000 0 1
Clock
X
Q
3
Q
1
Q
2
Z
1318 (a)
Clock
X
A
B
JA
KA
5ns 10ns 15ns 20ns 25ns 30ns 35ns
JB = KB
Z
Correct output Z = 0 0 1 0 0 1
All flip-flop inputs are stable for more than the setup time before each falling clock edge So the circuit is operating properly
1318 (b) If X is changed early enoughMinimum clock period = Flip-flop propagation delay + Two NAND-gate delays + Setup time = 4 + (3 + 3) + 2 = 12 nsX can change as late as 8 ns (two NAND-gate delays plus the setup time) before the next falling edge without causing improper operation
Transition table using a straight binary state assignment
98
1319Clock
A
B
C
X
Z
false
Correct output Z = 1 0 1 0 1
A+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
B+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
C+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
ZX A
B C 00 01 11 1000
01
11
10
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
S0
S3
S1
S2
0100
0110
0100
1000
10111100
1100
000110011100
1000
0000
1100
0011
1000
0010
Deriving the State TableJK flip-flop equation Q+ = JQ + KQthere4 A+ = (XC + XC) A + XA
[As JA = XC + XC KA = X Q = A]= AXC + AXC + XA
Similarly B+ = XC + XA + XACC+ = 0 C + (XBA) C = C + XBAZ = XB + XC + XBA
From the Karnaugh maps we can get the state table that follows
StatePresent State
Next State (A+B+C+) Z
ABC X = 0 X = 1 X = 0 X = 1S0 000 000 110 1 0S1 001 111 001 0 0S2 010 000 110 1 1S3 011 111 001 0 1S4 100 100 011 1 0S5 101 101 011 1 0S6 110 100 010 1 1S7 111 101 011 0 1
R = X2 (X1 + B)S = X2 (X1 + B)A+ = A[(X2 ) (X1 + B)] + X2 (X1 + B)
= A (X2 + X1B) + X2X1 + X2BA+ = AX2 + AX1B + X2X1 + X2B
T = X1BA + X1BAB+ = BT + BT
= B(X1BA + X1BA) B (X1BA + X1BA)= B [(X1BA) (X1BA)] + X1BA= B [(X1 + B + A) (X1 + B + A)] + X1BA = (BX1 + BA) (X1 + B + A) + X1BA= BX1 + BX1 + BX1A + BAX1 + BA + X1BA= X1B(1 + 1 + A + A) + A (B + X1B)= X1B + AB + X1A
1320
StatePresent State
A+B+
X1X2=Z1Z2
X1X2=
AB 00 01 10 11 00 01 10 11S0 00 11 01 10 00 10 10 00 00S1 01 11 01 01 01 11 00 11 00S2 10 10 00 10 10 01 00 01 00S3 11 10 00 11 01 00 00 00 00
1320 (contd)
98
1319Clock
A
B
C
X
Z
false
Correct output Z = 1 0 1 0 1
A+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
B+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
C+X A
B C 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
ZX A
B C 00 01 11 1000
01
11
10
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
S0
S3
S1
S2
0100
0110
0100
1000
10111100
1100
000110011100
1000
0000
1100
0011
1000
0010
Deriving the State TableJK flip-flop equation Q+ = JQ + KQthere4 A+ = (XC + XC) A + XA
[As JA = XC + XC KA = X Q = A]= AXC + AXC + XA
Similarly B+ = XC + XA + XACC+ = 0 C + (XBA) C = C + XBAZ = XB + XC + XBA
From the Karnaugh maps we can get the state table that follows
StatePresent State
Next State (A+B+C+) Z
ABC X = 0 X = 1 X = 0 X = 1S0 000 000 110 1 0S1 001 111 001 0 0S2 010 000 110 1 1S3 011 111 001 0 1S4 100 100 011 1 0S5 101 101 011 1 0S6 110 100 010 1 1S7 111 101 011 0 1
R = X2 (X1 + B)S = X2 (X1 + B)A+ = A[(X2 ) (X1 + B)] + X2 (X1 + B)
= A (X2 + X1B) + X2X1 + X2BA+ = AX2 + AX1B + X2X1 + X2B
T = X1BA + X1BAB+ = BT + BT
= B(X1BA + X1BA) B (X1BA + X1BA)= B [(X1BA) (X1BA)] + X1BA= B [(X1 + B + A) (X1 + B + A)] + X1BA = (BX1 + BA) (X1 + B + A) + X1BA= BX1 + BX1 + BX1A + BAX1 + BA + X1BA= X1B(1 + 1 + A + A) + A (B + X1B)= X1B + AB + X1A
1320
StatePresent State
A+B+
X1X2=Z1Z2
X1X2=
AB 00 01 10 11 00 01 10 11S0 00 11 01 10 00 10 10 00 00S1 01 11 01 01 01 11 00 11 00S2 10 10 00 10 10 01 00 01 00S3 11 10 00 11 01 00 00 00 00
1320 (contd)
