Fundamentals of Digital Design

Part 1: combinational circuits

Krzysztof Świentek

AGH University of Science and Technology

Faculty of Physics and Applied Computer Science

Krakow, Poland

Design of CMOS integrated circits, 2019

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Outline

1. Introduction– logic gates– boolean function

2. Logic synthesis – Karnaugh tables

3. Transistors – a base elements for building digital gates

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1. Introduction

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Contents of this course – integrated circuits

• Prototyping of IC is expensive.

• Prototype cost as car cost:– old technology 350nm

(lab) – a small car– modern tech. 130nm – a

good car– frontier technology 20nm

– a Bentley or more!!

• We will make a design only, which is based on computer simulations

• An integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material that is normally silicon.

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Voltage as a logic value

• Only High (near power supply) and Low (near ground) voltages are significant

• High state or logic 1• Low state or logic 0

• Logic values may be combined into– binary numbers– Boolean algebra

possible disturbances (1.5V)

possible disturbances (1.5V)

Supply voltage:• TTL 5,0 V• Typical CMOS 3,3 V• Modern CMOS 0,9 – 1,2 V

Lab

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Base logic gates 1

Logic gate = base logic function

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Boolean algebra laws

• Associativity – x+(y+z) = (x+y)+z

– x*(y*z) = (x*y)*z

• Commutativity

– x+y = y+x

– x*y = y*x

• Identity– x+0 = x

– x*1 = x

• Anihilation (+)

– x*0 = 0

• Distributivity (* over +)

– x*(y+z) = x*y+x*z

• Absorption– x*(x+y) = x

– x+(x*y) = x

• Idempotence

– x+x=x

– x*x=x

• Anihilation (*)– x+1 = 1

• Distributivity (+ over *)

– x+(y*z) = (x+y)*(x+z)

Obvious algebraiclaws

Not so obvious boolean laws

• Complementation

– x + x = 1

– x * x = 0

• Double negation– x = x

• De Morgan(!!)

– x + y = x*y– x * y = x+y

Negation related laws

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Exercise 1 – boolean algebra laws

1. Proof using truth tables– Anihilation (*)

• x+1 = 1

– Idempotence• x+x=x• x*x=x

2. Proof using other laws– Absorption

• x*(x+y) = x• x+(x*y) = x

3. Remove multiplication using de Morgan laws– (y + z) * (x + y) * (y + z)

4. Remove addition using de Morgan laws– (x * y) + (x * z) + (y * z)

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Base logic gates 2

x y= x*y + x*y x y = x*y + x*y

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Schematic of boolean function

• Each boolean function is equivalent to some electrical circuit

• Example f(a,b,c) = a b + a*b + c

a

b

c

f(a,b,c)

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Equivalent gate symbols

xy

z xy

z x+y = x*y

x*y = x+y xy

z xy

z

• Alternative symbols for inverter

x y x y

• Direct formula to schematic conversion may lead to different symbols for the same gate – e.g. de Morgan's laws

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Schematic may be directly transformed using boolean laws

a

b

c

f(a,b,c)

Buffer

• Buffer is a logically neutral gate

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Exercise 2 – schematics of boolean functions

1. Draw schematic of below functions – f1(x,y,z) = (y + z) * (x + y) * (y + z)

– f2(x,y,z) = (x * y) + (x * z) + (y * z)

2. Transform schematics to remove + or * operation – a tip: use double negation law x = x

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2. Logic synthesis

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Synthesis – how to create a logic function?

• Synthesis is a process by which a specification of desired circuit is turned into design implementation in terms of logic gates.

• Specification– Text description– Truth table– Abstract description in

so-called Hardware Description Language (HDL)

A>BA

CB

B0

C=A>B

B1 A1 A0

• Output– logic function– schematic

synthesis

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Simple logic function – truth table

A B A>B

00 00 0

00 01 0

00 10 0

00 11 0

01 00 1

01 01 0

01 10 0

01 11 0

10 00 1

10 01 1

10 10 0

10 11 0

11 00 1

11 01 1

11 10 1

11 11 0

• Logic function = combinational circuit

• Let's consider comparison of two 2-bit numbers: C=A>B

• Inputs are 2-element binary vectors: A={A1, A0}; B={B1, B0}

• All combinations of inputs and outputs can be easy written down in form of Truth Table

A>B

AC

B

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General forms of boolean formula

A B A>B

00 00 0

00 01 0

00 10 0

00 11 0

01 00 1

01 01 0

01 10 0

01 11 0

10 00 1

10 01 1

10 10 0

10 11 0

11 00 1

11 01 1

11 10 1

11 11 0

• If a single 1 appears in sum the result is 1

• Each boolean function can be shown as a sum of so-called minterms mi

• C = ∑mi

A1*A0*B1*B0

A1*A0*B1*B0

minterms

A1+A0+B1+B0

• If a single 0 appears in product the result is 0

• Each boolean function can be shown as a product of maxterms Mi

• C = ∏Mi

A1+A0+B1+B0

maxterms

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Synthesis – the base approach (minterms)

A B A>B

00 00 0

00 01 0

00 10 0

00 11 0

01 00 1

01 01 0

01 10 0

01 11 0

10 00 1

10 01 1

10 10 0

10 11 0

11 00 1

11 01 1

11 10 1

11 11 0

• In general C = ∑mi

• Write formulas for minterms

• Combine pairs of minterms with the same but one coefficients and reduce as many as you can

• Is there a better method?

A1*A0*B1*B0

A1*A0*B1*B0A1*A0*B1*B0

A1*A0*B1*B0

A1*A0*B1*B0

A1*A0*B1*B0

A1*A0*B1*(B0 + B0) = A1*A0*B1}

A1*A0*B1*(B0 + B0) = A1*A0*B1}

A1*B1*(A0 + A0) = A1*B1

A1*A0*B0*(B1 + B1) = A1*A0*B0

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A B A>B

00 00 0

00 01 0

00 10 0

00 11 0

01 00 1

01 01 0

01 10 0

01 11 0

10 00 1

10 01 1

10 10 0

10 11 0

11 00 1

11 01 1

11 10 1

11 11 0

B1,B000 01 11 10

00 0 0 0 0

01 1 0 0 0

11 1 1 0 1

10 1 1 0 0

A1,A0

Grey code column and row headers

Karnaugh map – better method

<=>

What to do if the function output is multi-bit?

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B1,B000 01 11 10

00 0 0 0 0

01 1 0 0 0

11 1 1 0 1

10 1 1 0 0

Minimized logic function

A1,A0

Number of elements and group size is power of 2

• Let's group ones (or zeros)

• The bigger group the better

+ A1*A0*B0because A1*A0*B1*B0 + A1*A0*B1*B0 =

= A1*A0*B0*(B1 + B1) == A1*A0*B0

C = B1*A1 + A0*B1*B0

C =

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Schematic of the result circuit

B0

C=A>B

B1 A1 A0

C = B1*A1 + A0*B1*B0

+ A1*A0*B0

• Gates statics:– 2 NOTs (inverters)– 3 ANDs– 1 OR

• What to do if the function output is multi-bit?

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Final schematic may still be transformed for specific requirements e.g. NANDs only

B0

C=A>B

B1 A1 A0 B0

C=A>B

B1 A1 A0

=>

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Exercise 3 – logic synthesis

• Design (using Karnaugh tables) a two 2-bit comparator: C = A<=B

• Design (for lab) 1-bit adder which may be a part of multi-bit adder;

– it has 3 inputs: a, b, cin (where is cin is a carry from previous addition)

– and 2 outputs: s, cout (where s is the sum and cout is the output carry)

• Use the previous block to build multibit (e.g. 4-bit) adder

• Repeat the above exercises for subtractor

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More complicated design – ALU

• ALU – Arithmetic Logic Unit

• In simplest realisation it is combinational circuit

• Desired operation encoded as a number at K input

• Example operations: add, sub, lsh, lsr, and, or, xor, not

• How to describe so complicated circuit?

• Cin i Cout are carry bits

ALU

A[7:0]

B[7:0]

Cin

S[7:0]

Cout

K[7:0]

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Simple description of complicated circuit – HDL

• HDL – Hardware Description Language

• Two most important HDL languages: VHDL and Verilog HDL

• Verilog is similar to C, but only similar

• Special simulator is needed

• How to translate this to gates?

module ALU (input [7:0]A, [7:0]B, Cin, [7:0]K, output reg [7:0]S, Cout);

localparam c_add=0, c_sub=1, c_lsh=2, c_rsh=3, c_and=4, c_or=5, c_xor=6, c_not=7;

always @* case(K)

c_add: {Cout,S} = A+B+Cin;c_sub: {Cout,S} = A-B-Cin;c_lsh: {Cout,S} = {A,Cin};c_rsh: {S,Cout} = {Cin,A};c_and: S = A & B; Cout=0;c_or : S = A | B; Cout=0;c_xor: S = A ^ B; Cout=0;c_not: S = ~A; Cout=0;

endcaseendmodule Verilog HDL

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ALU synthesis result

• Translation from HDL to gates is called synthesis

• Another tool is needed – RTL Compiler

• It was easy to write a code but how to implement it?

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3. Transistors

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What is inside logical gate? Transistors.

• CMOS transistor– semiconductor element– two types: p-type & n-type– 4-terminals: gate (G), source

(S), drain (D) and bulk (B)

• In digital circuits– Bulk connected to ground

(NMOS) or power (PMOS), so it’s omitted in schematics

– Transistors works as switches

PMOS(p-type)

NMOS(n-type)

Typically connected to higher voltage (above ½ vdd e.g. vdd)

Typically connected to lower voltage (below ½ vdd e.g. gnd)

SG

D

S

G

B

B

PMOS – Positive MOSNMOS – Negative MOS

MOS – metal oxide semiconductor

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The simplest model of transistor – a switch

Gate

Gate

Source

Source

Drain(sink)

Drain(sink)

OFF

ON

• Gate voltage in relation to source controls transistor state, when

– |VG – VS| is high then trans. is ON

– |VG – VS| is low then trans. is OFF

faucet model

OFF

G=vdd

ON

G=gnd

ON

OFF NMOS

PMOS

vddS

G

D

S

G

gnd

vddS

G

D

S

G

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Static CMOS gates – NOT (inverter)

• Transistors are geometric objects with width and length

• Length is always minimal: L = 0.35 um (in AMS, lab.)

• Width of PMOS is typically twice larger then NMOS to equalize ON resistanceY = A

VDDWL

P

WL

N

A Y

1.60.35

0.80.35

=

=

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Static CMOS gates – NAND

VDD

 A

B

B

Y

1.60.35

1.60.35

1.60.35

1.60.35

• Multiplication (*)– PMOS trans. are parallel– NMOS trans. in series

• Output logic function is always negated

• NAND is simpler then AND• AND=NAND + NOT

• Transistors in series have to be larger to lower the resistance

Y = A*B

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Static CMOS gates – NOR

• Addition (+)– PMOS trans. in series– NMOS trans. parallel

• NOR is simpler then OR• OR=NOR + NOT

• Transistors in series have to be larger to lower the resistance and because they are PMOS, width is 4 times larger than in NMOS

Y = A+B

 

VDD

A

B

B

Y

3.20.35

3.20.35

0.80.35

0.80.35

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More complicated functions are also feasible

3-input NAND

Y=(A*B*C)

Y=(A+B+C)*D

• Logically NAND inputs are equivalent, but electrically they are not!

VDD

 A

B

B C

Y

c

VDD

A

B

D

Y

B

C

A

D

C

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De Morgan's laws in reduction of circuit area

xy

z xy

z x+y = x*y

x*y = x+y xy

z xy

z

• NAND is simpler then AND• NOR is simpler then OR• OR and NOR are larger (because of PMOSes)

then AND and NAND

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Backup

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Transistors are semiconductor elements

• MOS transistor– MOS – metal oxide semiconductor – two types: p-type & n-type– 4-terminals: gate (G), source (S),

drain (D) and bulk (B)– bulk connected to ground (NMOS)

or power (PMOS) in digital

gndvdd

PMOS(p-type)

NMOS(n-type)

SG

D

S

G

B

B