Fully TID-Hardened Gigabit Ethernet Transponder Based On A

Proprietary Library of SCL Cells

Presentation By: Jeb Binkley (jbinkley@adsantec.net)

Vladimir Katzman Ph.D. (vkatzman@adsantec.net)

MAPLD 9/01/09

Advanced Science and Novel Technology

A D S A N T E C

Introduction• Transponder requirements and specifications

• TID hardening approach

• Optimum circuit logic family selection

• Proprietary cell library development

• Test chip and its laboratory results

• Transponder block schematics, layouts, and simulation results

• Transponder test results

• Summary

A D S A N T E C A D S A N T E C

Gigabit Ethernet Transponder A D S A N T E C A D S A N T E C

SEL 3

SEL 2 10:1 MUX

CMU

SEL 1

2-Bit FIFO

NORT

CDR

SEL 3

1:10 DMUX

Loop Test 1

Err Res

D00-09 & C/10

Q00-09 & C/10 Loop

Test 2

Loop Test 3

Cref C/10-20 Bit

Order Bit

Order

CML OB CML IB

Dout Din C/10

off Transponder Specifications

• 10-1 MUX with CMU and 1-10 DMUX with CDR

• 1.25Gb/s CML serial interface

• 1.8V CMOS low-speed parallel interface

• Internal 2-bit FIFO block

• 3 loop-back test modes

• ≤ 250mW power consumption

• TID hardness up to 1.0Mrad

• Must utilize 90nm CMOS9SF process from IBM

TID Hardening Of FETs

Advanced Science and Novel Technology

A D S A N T E C

Design of TID-Tolerant FETs A D S A N T E C A D S A N T E C

• Field-effect transistors (FETs) are susceptible to the effects of TID (well known)

• An effective RHBD technique is the utilization of annular transistors (no-edge gate structures) in combination with protection guard rings around all n/n+ regions featuring different electrical potentials [1].

• Application of this technique requires the development of the corresponding transistor layout structures and extraction procedures in order to determine the correct parameters of the simulation models.

• No libraries of CMOS gates with annular transistors are currently available on the market today.

Annular FETs

Drain/Source

Source/Drain

Gate

Length

Width (Perimeter) Body

FET type Minimum channel

length (nm) Technological minimum

gate width (nm) Annular minimum

gate width (nm) LVTNFET 100 120 2600 DGNFET 240 360 3600

In Annular FETs:

1. Current density is limited by the number of contacts to the inner diffusion region.

2. Minimum gate width is limited by the smallest circle length and depends on the gate length.

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Logic Family Selection

Advanced Science and Novel Technology

A D S A N T E C

SCL vs. CMOS A D S A N T E C A D S A N T E C

• CMOS logic is a natural implementation of the Si-based CMOS technologies

• Single-ended architecture is utilized in most modern day IC products

• Down-scaling of gate lengths to 90nm and below makes it suitable for Gb/s circuit designs

• Short-channel devices suffer from increased sub-threshold currents and low breakdown voltages

• Single-ended circuitry includes switching noise and signal duty cycle distortion

• Significant increase of dynamic power consumption at higher speed

• SCL architecture is based on a differential current switch

• Overcomes switching noise and duty cycle distortion problems

• SCL circuits are less sensitive to sub-threshold currents

• DC current consumption that does not increase with signal frequency

• Limited transconductance of FETs minimizes the architectural advantage of SCL

• The driving capability of SCL logic gates is relatively low

Logic Family Selection A D S A N T E C A D S A N T E C

• SCL architecture selected

• CMOS power saving advantages negated due to the enlarged minimized sized transistor width allowed by the annular transistor technique (Slide 5)

• Common circuit structures simulated to select the optimum logic family

• Simple dividers, DFFs, and ring oscillators

Divide-by-2 CMOS Version SCL Version

Maximum Frequency

700MHz 720MHz

Power Consumption (@625MHz)

1.2V * 0.6mA = 0.72mW

1.6V * 0.5mA = 0.8mW

Gate Count 61 21

Cell Library Development

Advanced Science and Novel Technology

A D S A N T E C

SCL Library Design (Schematic) A D S A N T E C A D S A N T E C

• SCL cells with various tail current ratings that support operational frequencies from DC to over 10GHz

• Operate from a single power supply voltage of 1.6V±5%

• Includes bandgap reference stage and other referencing circuitry

• Examples of implemented standard gates include:

• Logic gates (AND, XOR, etc.)

• Buffers (current switches)

• Source followers

• Latches (RS-latch, D-latch)

• Mux 2-1

• SCL to CMOS

Reference Circuitry Buffer

SCL Library Design (Layout) A D S A N T E C A D S A N T E C

• SCL cell layouts follow ADSANTEC’s proven proprietary layout approach:

• Minimum distance between transistors in differential pairs & similar component orientation

• All resistors are constructed utilizing standard bars

• Each cell is placed inside a closed substrate contact ring to improve its radiation tolerance

• All cells can be placed next to each other in X direction with virtually no gap in between

• Vertical connections are in “M4” & “M5” will horizontal are in “M2” & “M3”

• Layers “M6”, “M1_2B”, and “M2_2B” are reserved for bulk reference plane, VCC, and VEE connections.

• All interconnections inside the cells are valid for 100000POH at 125C and ±3 sigma process variation.

Buffer Cell

Main Library Benefits A D S A N T E C A D S A N T E C

• Benefits of a gate-array design approach• No-gap cell placement & similar structure of all cells

minimizes area consumption• Transistor mismatch minimization• Resistor mismatch minimization• Symmetry optimization• Thermal environment optimization• Current density optimization • Parasitic optimization

• High simulation speed and accuracy• Reduces schematic and layout design cycle• Designs are created utilizing proven blocks

Test Chip

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A D S A N T E C

Test Chip Results

A D S A N T E C A D S A N T E C

TID (krad) 0 100 100+ 300 300+ 500 500+ 1000 1000+ 2000 A* Δ time (minutes) - 12 41 25 38 25 32 60 25 120

“v2p5” (mA) 58.5 61.0 59.8 62 60 63 60.7 62 61 62.3 59.0 “vdd” (mA) 10.0 10.2 10.1 10.5 10.2 10.6 10.2 10.3 10.2 10.3 10.1

LVDS I/O Max. Freq. (GHz) “a” 1.47 1.48 1.5 1.5 1.55 1.5 1.5 Osc. Max. Freq. (GHz) “a” 1.57 1.5 1.5 1.49 1.49 1.49 1.5

LVDS I/O Max. Freq. (GHz) “b” 1.7 1.68 1.61 1.6 1.63 1.62 1.65 Osc. Max. Freq. (GHz) “b” 1.62 1.69 1.7 1.71 1.64 1.63 1.64

*Annealed: 168 hours at 100°C

TID Testing Results

• TID testing was conducted at Kirtland Air Force Base, Albuquerque, NM with support from Micro-RDC and AFRL• All test structures exhibited no degradation in electrical behavior after radiation exposure• No latch up or extra current consumption was observed

Transponder Blocks

Advanced Science and Novel Technology

A D S A N T E C

Top Level Schematic A D S A N T E C A D S A N T E C

Main Blocks A D S A N T E C A D S A N T E C

• 10-1 MUX• Two 5-1 parallel-serial registers connected to a MUX 2-1

• Utilizes proprietary clocking scheme• Charge pump PLL based differential CMU with ring VCO

• 1-10 DMUX• One DMUX 1-2 followed by two 1-5 serial-parallel registers• Proprietary dual loop CDR with LOL detection

• 2-bit FIFO• Removes clock ambiguity between input and PLL clocks

Top Level Simulation

A D S A N T E C A D S A N T E C

Loop Back Test 3

MUX Output

DMUX Input

SerDes Output C/10 Signals Current Consumption = 105mA

Ring VCO

A D S A N T E C A D S A N T E C

Layout

Schematic Kvco Curves

Laboratory ResultsTest Results for the 10:1/1:10 SerDes at 1.25GHz:

Reference Clock

Divided-by-10 Clock

C/10 Jitter pk-pk = 25-30ps

• Excellent signal characteristics• Demonstrated full functionality • Passed TID testing up to 2Mrad

A D S A N T E C A D S A N T E C

Summary• A 1.25GHz 10-1 / 1-10 transponder was successfully designed,

fabricated, and tested.

• IBM9SF CMOS technology

• Chip size 2.4mm by 2.4mm

• Power: 200mW

• Designed using proprietary library of TID hardened SCL cells

• TID hardness provided by a combination of annular FET layouts and guard rings

• Suitable for gigabit Ethernet application

A D S A N T E C A D S A N T E C

Questions?• Special thank you to the support provided by:

• AFRL (David Alexander) and MRDC (Keith Avery)

• “SerDes, LVDS IOs, and Core Frequency Synthesis PLL for Radiation-Hardened-by-Design Structured ASICs”

• Sub-Contract Number: 07001-SC-002

• SBIR Contract Number: FA9453-06-C-0200

• NASA GSFC (Glen Rakow)

• “Radiation-Tolerant, Space Wire and Gigabit Ethernet Compatible Optical Transponder”

• SBIR Contract Number: NNX07CA73P

• [1] David R. Alexander, David G. Mavis, Charles P. Brothers, and Joseph R. Chavez, “Design Issues for Radiation Tolerant Microcircuits in Space”, 1996 IEEE Nuclear and Space Radiation Effects Conference Short Course, 1996.

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