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Fully depleted MAPS: Pegasus and MIMOSA 33 Maciej Kachel, Wojciech Duliński PICSEL group, IPHC...
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Transcript of Fully depleted MAPS: Pegasus and MIMOSA 33 Maciej Kachel, Wojciech Duliński PICSEL group, IPHC...
Fully depleted MAPS: Pegasus and Mimosa 33
Fully depleted MAPS: Pegasus and MIMOSA 33Maciej Kachel, Wojciech DuliskiPICSEL group, IPHC Strasbourg1
For low energy X-ray applicationsMotivationGoal (success oriented):Low energy X-rays (< 10 keV)Single photon counting (with > 106 ph / 100x100 m2) Good spatial resolution (few m)[email protected] requirements:Depletion depth ~ 50-100 mLow noise (sensitivity to few 100 e- signal)Fast frame rate >> kHzPixel pitch ~ 20 mIntermediate step ASIC:Counting > 103 ph/pixelsEnergy range 1 keV 10 keVNoise below 25 e-Pixel size 25 x 25 m2Chip size ~1 cm2How to get depletion??MAPS
[email protected] sensitive area only few um of depletion - limited in Xray appications, but work with indirect detection
3Detection with MAPS Standard low resistivity epi (few cm)High resistivity epi (k cm)
With the same electronics you gain the depletion zone depth
But this is not enough!!4DiodeProvided by A. [email protected] efficiency of Si5Si - 300 mSi - 10 mSi - 50 [email protected] choice Test structures (collecting diodes and amplifiers) were made in both technologies TOWER (0.18 um)ESPROS (0.15 um)
Quadruple well technologyP substrateUsed by CERNFully depleted 50 mPost processing includedN substrate (detector grade)Out of the box solution [email protected] 33 submissionESPROS technology
Study different biasing approches
- Bias the diode from bottom
- Bias from the top DC coupling
[email protected] the charge collection with different pixel pitchPrototype of a simple X-ray counterM33: Standard SF pixel
Isolated NMOS transistors (but used with std voltage)
Diode biased from the anode side with negative voltage
SF bias - self biased solution
[email protected]: Standard SF mesurements
Increasing the Vphanode improves the charge collectionHigh noise ~ 50 e- rms ?
Low gain because of the large capacitance at the input node ??Fe55 measurements with different biasing(Vback, Vphanode)where the extracted capacitance at the gate of input transistor ~ [email protected] pixelM33: Standard SF mesurements (I) depletion depthMimosa 33 was tested with Sr beta source
10Apart from that good charge collection -> most of the charge is collected by the single pixel It looks like there is only 15m of depleted detector (out of 50)Beta particle leave ~80 e- / m of detector
1200 e- -> 15um of depleted substrate [email protected] pixel10M33: bias the diode from the top
First stage of the pixel can be supplied from higher voltages (i.e. 3.2 V 5.0 V)~4V at the diodeWith vback=-3V (or even 0V) response from beta particles is similar to the previous [email protected] pixelM33: X-ray counter
SR90 beta sourceFe55 X-ray source
SR90 beta sourceFe55 X-ray sourceChip is responsive
Due to the low gain problem the chip was not tested extensivelyDeveloped as a proof of concept16 x 18 pixels 50 um pitchIn pixel:CSA, shaper, comparator , 4bit counter and 4bit DC [email protected]: problem & second submissionThe reason for the low gain/high noise was the wrong sensing element placed by the foundry
Corrected version of chip was resubmitted and is expected in November 2014.
Foreseen testsStudy the charge collection with different pixel pitch (25 um, 50um)Custom made sensing elements insertedPixel designs modified, with AC coupled diode
Use standard CMOS technology
Courtesy of T. HemperekBonn University
[email protected] CMOS (Tower)Various types of epi in submission25 x 25m2 pixels Matrix - 56x32 with 4 versions of pixelsTwo source followersTwo amplifiers
AmplifierInput diode AC coupled with amplifierBased on inverterNo bias [email protected] measurements results
Fe55 spectrum with different diode voltage (seed pixel)ENC ~25 e-Tests performed on the chips with a 18 m thick epitaxial [email protected] depletion depth estimationPegasus chip (in-pixel amplifier)171400 e- -> substrate with 18m [email protected] pixelPegasus 2Similar to Pegasus 1 (also 4 versions of pixels)Problems with high frame rate in first submission pixels optimized
Rolling shutter readout -> 150ns per row
Tests just started18
[email protected] 2Cluster shape19
[email protected] 2 preliminary measurements20
Source follower:Gain 17 uV/e- => Cin = 9.38 fFENC 17 e- (base) 28 e- (Fe peak)Amplifier:Gain 70 uV/e-ENC 16 e- (base) 30e- (Fe peak)[email protected] pixelSeed pixelConclusionsWith those new technologies MAPS looks promising for wide variety of low energy X-ray applications
Both approaches are promissingCharge collection TOWER full depletion of epi - most of the events in 1-2 pixelsSmall noise 100 eV resolution at 6 keVFrame rate to achieve the high frame rate goal -> 3D approach like professionals do
Study of the charge collection and depletion capabilities will be performedCharge collection with different pixel pitch (4, 25, 50)Response linearity with energySensitivity to 1 keV photonsDepletion uniformity Sr source, Edge TCT studiesNeutron irradiated [email protected] you for your attention23Motivation
Advantages :Smaller pixelsStandard CMOS technology ($)No bump bonding neededNoise lower than in hybrid det. Due to small capacitance at the inputDisadvantages:Low energy X-rays only ( < 20 keV )Radiation tolerance smaller than in hybrids
Monolithic sensorHybridsAdvantages :Different materials of detectorsThick detectors for higher energies availableRadiation hardness
Disadvantages:Pixel pitchHard to set the threshold lowCosts: Detectors, Bonding
24Maciej KachelMAPSStandard MAPSIntroduced at the end of the XXth century for digital cameras
Only NMOS transistors in pixels (PMOS would take part in charge collection)Charge collection mainly through diffusion (low efficiency, no depletion)Thin sensitive area limited in Xray applications, but work with indirect detectionUsed in various charge particle detection applications25Maciej KachelThin sensitive area only few um of depletion - limited in Xray appications, but work with indirect detection
25P- substrate
P - WELL
epitaxial layer ~20 m
N-WELL
n
n
P - WELL
n
n
collecting diode
NMOS
NMOS
RST
vdiode
VDDA
ROWselect
Columnoutput
P- substrate
N-WELL
p
p
PMOS
collecting diode
P - WELL
N-WELL
NMOS
p-well
n
n
N-WELL
p
p
deep pwell
n
n
PMOS
NMOS
+1.8V
+~1.5V
+1.8V
+1.8V
-5V -12V
+1.8V
READ
OUTPUT
VPHANODE
+5V
+4.5V
+5V
+5V
+5V
READ_3.2-5V
+5V
+5V
+5V
OUTPUT
+5V
BIAS
3.2V
3.2V
+5V
Vclamp
Clamp
READ
Rf
Collecting diode
Diode Bias
OUT
Vclamp
Cc
Collecting diode
Diode Bias
Rf
Vanadium foil (5 m thick)
55Fe source
P- substrate
P - WELL
epitaxial layer ~20 m
N-WELL
n
n
P - WELL
n
n
collecting diode
NMOS
NMOS
RST
vdiode
VDDA
ROWselect
Columnoutput