Front–End Tools for Dynamic Reconfiguration in FPGA Devices 2005
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Transcript of Front–End Tools for Dynamic Reconfiguration in FPGA Devices 2005
Front-End Tools for Dynamic Reconfiguration in FPGA devices
Kamil KedzierskiTechnical University of Catalonia, Spain
Kraków, 23.06.2005
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Outline
• Introduction
• Manual Partitioning Tool
• VHDL-Post Processing Tool
• Configuration Controller Generator
• Putting it all together
• Conclusions
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
• Different modes of reconfiguration:
– Global, static
– Partial, static
– Partial, Dynamic:
• Reconfigure some areas of the FPGA while the rest ofthe design is still running
• Resulting challenge:
– Sequentially download the configuration of the dynamic blocks while maintaining, until the switch to the new configuration, the operation of the static blocks
Project rationales and objectives
Dynamic modules Static
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Project organization: Consortium: www.reconf.org
• Geographical repartition over 6 European countries
• 7 partners: 2 Academics, 1 Semiconductor Provider, 3 Users
GREECEAtmel Hellaswww.atmel.com
BELGIUMDeltatecwww.deltatec.be
ITALYKayser Italiawww.kayser.it
FRANCE
Atmel NTOwww.atmel.com
MBDA Francewww.mbda.net
SPAIN
UPCwww-eel.upc.es/aha
CZECH REPUBLICUTIAwww.ideal-ist.cz
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Project organization
WP
1: P
roje
ct M
anag
emen
t
WP2: D_FPGA & Tools Specifications
• Specifications of the D_FPGA Characteristics• Specifications of the Design Environment
WP3: Methodology
• New Partitioning Methodology• Design Guidelines
WP4: Front-end Tools design
• Constraints Editor• Automatic Partitioning Tool• VHDL Post-Processing Tool• Configuration Controller Gen.
WP5: Back-end Tools design
• Modular Place & Route Tool• FPGA Re-configuration Tool
Evaluation: Overall methodology
• Mock up for evaluation• Medical Application
WP6: Evaluation:States Machine
• Mock up for evaluation• Control for Space Application
WP7: Evaluation:Complex algorithms;Real time
• Mock up for evaluation• Video Application
WP8: Evaluation:Data management;Test & debug
• Mock up for evaluation• Aeronautic Application
WP
9: Disse
min
ation
& Im
plem
entatio
n
• Web page: w
ww
.reconf.org• T
hird Party for F
ront End T
ools
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Standard HDLsynthesis
Standard HDLsimulation
Technicalspecifications
Chiparchitecture
Chip modelling
Standard HDLsimulation
Standard HDLsimulation
Temporalsystemplanner
Constraintsdefinition
VHDL post-processing
Configurationcontroller generator
Librarycreation
Modularplace & route
D_FPGAreconfiguration
tool
Front EndTechnology transparent
Back EndTechnology dependent
- Standard SW environment-HW / SW co-simulation
InstrumentedHDL files
Constraintsfile
Partialsimulations
Inputs from highlevel design tools:
- MatLab,- Celoxica...
Updatedconstraints file
SchedulerC files
HDL files(static & dynamic)
SchedulerHDL files
StandardHDL files
Bit streamfiles
KEY
Indication of the sequence between tasks (logical & temporal)
Link to the task that generated the outputs Tasks identical to the ones of the «classical design flow», using «standard» tools
Tasks specific to partial dynamic reconfiguration and requiring dedicated tools
Inputs / Outputs. Only the main ones are indicated for clarity pupose
The Design Flow
Manual Partitioning Tool
Partitioning
Configuration Controller Generator
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Outline
• Introduction
• Manual Partitioning Tool
• VHDL-Post Processing Tool
• Configuration Controller Generator
• Putting it all together
• Conclusions
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Manual Partitioning Tool - Features
• Reads VHDL source files
• Hierarchical graphical representation of internal structure (input & output code), direct import of VHDL dynamic modules possible
• Possibility for setting, editing and checking constraints for every dynamic module:
– Conditions for loading / unloading dynamic modules• Time based (Clock cycle), Frame based (periodic), Signal event based (asynchronous)
– Exclusive constraints between dynamic modules
– Interface between application and configuration controller (status)
– Bit stream organization in the storage memory
• Generation of the interfaces between dynamic and static parts
• Output contains source files for the dynamic modules, interfaces, static parts and DCF file
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Manual partitioning tool – User Interface
Input Output
Tree Browser
SignalList
SourceCode
Viewer
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Outline
• Introduction
• Manual Partitioning Tool
• VHDL-Post Processing Tool
• Configuration Controller Generator
• Putting it all together
• Conclusions
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
VHDL Post-Processing Tool - Features
• Permits to carry out a functional validation for the results of the partitioning process
– Verify if exclusive constraints are satisfied
– Identify the active dynamic modules at any given time
– Analyse the effect of unloaded dynamic modules on the whole design
• Dynamic simulation process based on the DCS (Dynamic Circuit Switch) techniques proposed by Lysaght et al
• Activation/Deactivation of dynamic modules emulated by means of isolation switches
• Generates a functional description of the configuration controller (Schedule Control Module - SCM) and the isolation switches
• Dynamic simulation fully compatible with static verification (same set of stimuli)
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
VHDL Post-Processing Tool, organisation of the simulation process
Static Module 1Static Module 1 Static Module 2Static Module 2
SCMSCM
Z (D_Module not present)
D_Module driver
X (D_Module being re-configured)
SCM control
Static node
Isolation switch
Dynamic Module 2Dynamic Module 2
Dynamic Module NDynamic Module N
Dynamic Module 1Dynamic Module 1
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
VHDL Post-Processing Tool, organisation of the simulation process
Static Module 1Static Module 1 Static Module 2Static Module 2
Dynamic Module 2Dynamic Module 2
Dynamic Module 1Dynamic Module 1
ON
OFF
REC
DM1
DM2
time
time
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
VHDL Post-Processing Tool, organisation of the simulation process
Static Module 1Static Module 1 Static Module 2Static Module 2
Dynamic Module 2Dynamic Module 2
Dynamic Module 1Dynamic Module 1
ON
OFF
REC
DM1
DM2
time
time
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
VHDL Post-Processing Tool, organisation of the simulation process
Static Module 1Static Module 1 Static Module 2Static Module 2
Dynamic Module 2Dynamic Module 2
Dynamic Module 1Dynamic Module 1
ON
OFF
REC
DM1
DM2
time
time
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Outline
• Introduction
• Manual Partitioning Tool
• VHDL-Post Processing Tool
• Configuration Controller Generator
• Putting it all together
• Conclusions
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Configuration Controller Generator (CCG), organization
• CCG is a collection of two tools. Therefore, the following parts of the functionality may be distinguished:
– VHDL-Post Processing Tool (Simulation Tool) generates:
• Bidirectional switch,
• Dynamic modules with added switches description
• Functional Configuration Controller
• Top-level file,
• Model simulation *.do file
– Configuration Controller Generator generates:
• Physical Configuration Controller (in both VHDL and C code)
• Reconf Interface, that is a collection of:– Event Detector– Sequential Scheduler– Physical Configuration Controller in VHDL code– Physical Interface
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Hardware Controller Verification process
Staticpart
Reconf Interface
IS
IS
IS
Dynamic_Module_1
Dynamic_Module_1
Dynamic_Module_1
TOP Entity
StimuliAI
• AI: Application Interface
• IS: Isolation switches
Reconfiguration Interface
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Reconf Interface detailed view
Event Detector
Switch control ports
Applicationsignals/ports
- event signals- clock signal- status signal
Reflects the conditions for loading or unloading the dynamic modules as specified in the DCF file relative to the design.
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Reconf Interface detailed view
Event Detector
SequentialScheduler
Applicationsignals/ports
- event signals- clock signal- status signal
Responsible for sequentially loading dynamic bit streams accordingly to the events detected by the event detector.
Switch control ports
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Reconf Interface detailed view
Event Detector
SequentialScheduler
PhysicalConfiguration
Controller
Switch control ports
Applicationsignals/ports
- event signals- clock signal- status signal
Responsible for sequentially requesting all the bit stream data of the bit stream associated to the bit stream Id requested by the Sequential Scheduler. It is also responsible
for reading the start and end pointers of the bit stream to load.
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Reconf Interface detailed view
Event Detector
SequentialScheduler
PhysicalConfiguration
Controller
PhysicalInterface
Switch control ports
Applicationsignals/ports
- event signals- clock signal- status signal
Reconf. port/
bit stream memory
Responsible for managing internal or external reconfiguration ports of the D_FPGA and internal/external bit stream memory.
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Reconf Interface detailed view
Event Detector
SequentialScheduler
PhysicalConfiguration
Controller
PhysicalInterface
Switch control ports
Applicationsignals/ports
- event signals- clock signal- status signal
Reconf. port/
bit stream memory
Device independent partDevice
dependent part
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Outline
• Introduction
• Manual Partitioning Tool
• VHDL-Post Processing Tool
• Configuration Controller Generator
• Putting it all together
• Conclusions
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Putting it all together: the Design Flow
P1
P3
P2
P4
P5
P6
static
d_module_1
d_module_2
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
P
static
d_module_1
d_module_2
cut
P1
P3
Putting it all together: the Design Flow
P2
P5
P4
P6
?
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
P
static
d_module_1
d_module_2
cut
P1
P3
P2
P5
P4
P6
S
SS
S
S
S
S
FCC switch control
cut control
eventsignals
Putting it all together: the Design Flow(functional simulation)
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Outline
• Introduction
• Manual Partitioning Tool
• VHDL-Post Processing Tool
• Configuration Controller Generator
• Putting it all together
• Conclusions
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
Conclusions
• Presented CAD environment allows the designer to proceed the dynamic reconfiguration in dynamically reconfigurable FPGA devices using currently available HDL tools
• The user is fully supported during the whole process: starting from input static VHDL files until a final VHDL description of a dynamic behaviour of a design
• Presented environment is a good candidate for the designer whenever the flexibility of tools and user convenience has to be high
FET for Dynamic Reconfiguration In FPGA
Kamil [email protected]
Kraków 2005
- All disclosure and / or reproduction rights reserved -
About the Author
• Currently working in High Performance Computing research group of the Computer Architecture Department at Universitat Politécnica de Catalunya, Barcelona (http://www.ac.upc.edu)
• Topics: high performance processor architectures, runtime support for parallel programming models, and performance tuning applications for supercomputing
• Last 5 years: more than 250 published papers in refereed international conferences, and 25 PhD thesis
• Come join us! contact: [email protected]