Front-End and ADC ASIC DesignFront End and ADC ASIC Design

Shaorui Li, Gianluigi de Geronimo*, Jack Fried, Wenbin Hou, NeenaShaorui Li, Gianluigi de Geronimo , Jack Fried, Wenbin Hou, Neena Nambia*, Emerson Vernon, Krithika Yethiraj, and Veljko Redeka

Instrumentation Division, Brookhaven National Lab

Outline• Introduction of cold front‐end (FE) and ADC ASICs for LAr TPCIntroduction of cold front end (FE) and ADC ASICs for LAr TPC• CMOS modeling and design for cold electronics• LAr FE ASIC: ‐ Optimizing input MOSFET under power constraint  ‐ Crosstalk of Adjacent Channels Performance of FE ASIC in MicroBooNE‐ Performance of FE ASIC in MicroBooNE

• LAr ADC ASIC: ‐ ASIC Feature and operation ‐ Current‐mode Domino architecture

• CMOS lifetime study for cold electronicsB i h t i ff t d lif ti‐ Basics on hot‐carrier effects and lifetime 

‐ CMOS lifetime in dc operation: analog front‐end ASICs‐ CMOS lifetime ac operation: logic circuits and FPGAs

2

p g• Further R&D for LAr FE and ADC ASICs

• Sense (anode) wires (up to ~ 10m long):

~14-31 kwires/kton

ASIC Specifications from LArTPC:

• up to 200 pF/wire• collecting (Y)• non-collecting

dE/dx of 1 MIP: 2.1MeV/cm

(U,V)• charge sensitivity

• range ~200 fC• ENC < 1,000 e-

• sample/buffer events• ADC 10-12-bit, 1-2 MS/s

• digital multiplexing• 128:4

• power constraint• ~ 20 mW /wire(FE+ADc+FPGA)

time •operation in LAr• > 30 yearsFirst proposed by C. Rubbia, 1977

3

voltage regulation (COTS)(< 100mV dropout)Cold Electronics

front‐end ASIC~ 5mW/ch.

FPGA (COTS)~ 8mW/ch.

ADC ASIC~ 5mW/ch.

overall 128:4sensing  o e a 8:multiplexingwires

8 x1 x

front‐end cold moduleserving 128 wires

Parallel work• CMOS lifetime studies

serving 128 wires~ 2.4 W 

Outline• Introduction of Cold Front‐End and ADC ASICs for LAr TPC• CMOS modeling and design for cold electronics• LAr FE ASIC: ‐ Noise Sources in Detector Amplifier and ENC CalculationNoise Sources in Detector Amplifier and ENC Calculation ‐ Optimizing input MOSFET under power constraint  ‐ Crosstalk of Adjacent Channels ‐ Performance of FE ASIC in MicroBooNE

• LAr ADC ASIC: ASIC Feature and operation‐ ASIC Feature and operation 

‐ Current‐mode Domino architecture • CMOS lifetime study for cold electronics‐ Basics on hot‐carrier effects and lifetime ‐ CMOS lifetime in dc operation: analog front‐end ASICsCMOS lif ti ti l i i it d FPGA

5

‐ CMOS lifetime ac operation: logic circuits and FPGAs• Further R&D for LAr FE and ADC ASICs

10CMOS018SIMULATED (foundry parameters)

LNRT

8

10CMOS018MEASURED

LNRT

ID vs VDS

CMOS static characteristics vs. T -- ID/VDS & ID/VGS

4

6

8 RT

I D [m

A]

4

6

8 RT

I D [m

A]

0

2

4

NMOS, L=0.18µm, W=10µm0

2

4

NMOS, L=0.18µm, W=10µm

100

101

CMOS018

I

gm

100

101

CMOS018

I

gm

0.0 0.3 0.6 0.9 1.2 1.5 1.8VDS [V]

0.0 0.3 0.6 0.9 1.2 1.5 1.80

VDS [V]

ID vs VGS

3

10-2

10-1

cmV/

dec

(ln(1

0)nV

T)

MEASURED

ID

LN RT

[mA]

, gm [m

S]

3

10-2

10-1

SIMULATED(foundry parameters)

LN RT

ID

[mA

], g m

[mS

]

cmV/

dec

(ln(1

0)nV

T)

0.0 0.3 0.6 0.9 1.2 1.5 1.810-5

10-4

10-3

~18m

V/de

c

~72mI D

NMOS, L=0.18µm, W=10µm

0.0 0.3 0.6 0.9 1.2 1.5 1.810-5

10-4

10-3I D

NMOS, L=0.18µm, W=10µm

~18m

V/de

c

~72m

0.0 0.3 0.6 0.9 1.2 1.5 1.8VGS [V]

0.0 0.3 0.6 0.9 1.2 1.5 1.8VGS [V]

Some differences in saturation voltage, sub-threshold slope, transconductance

6

120 MEASURED

CMOS static characteristics vs. T -- gm/ID

80

100NMOS PMOS T=77K L=360nm L=270nm L=180nm

gm/ID

40

60 NMOS PMOS T=300K L=360nm L=270nm

L=180nm

g m/I D

[V-1]

0

20

40 L 180nm

CMOS018

~ 30 300m at T Kg q

10-6 10-5 10-4 10-3 10-2 10-1 100 101 1020

Drain Current Density [mA/mm]

Transconductance/~116 77

m

D B

g qat T KI nk T

At 77-89K, charge carrier mobility in silicon increases, thermal fl t ti d ith kT/ lti i hi h i hi h /I

Transconductance//drain current

fluctuations decrease with kT/e, resulting in a higher gain, higher gm /I, higher speed and lower noise.

7

103

103T = 300K T = 77K

CMOS Noise Spectral Density vs. T

102

1/fNMOS

L=180nm, W=1mm (20µm x 50)VDS=400mV, T=300K

ty [n

V/

Hz]

102

1/f NMOS

L=180nm, W=1mm (20µm x 50)VDS=400mV, T=77K

ity [n

V/H

z]

101

NMOSID=3.2mA (IC=1)

PMOSID=0.7mA (IC=1)

fit curvespec

tral d

ensi

101

ID=3.2mA (IC=3)

PMOSID=0.7mA (IC=0.3)

fit curve spe

ctra

l den

si

1 2 3 4 5 6 7 810-1

100

1/fwhite

CMOS018Inpu

t noi

se

101 102 103 104 105 106 107 10810-1

100

1/fwhite

CMOS018Inpu

t noi

se• White noise at 77K is a factor of 2 lower than at 300K

101 102 103 104 105 106 107 108

Frequency [Hz]

101 102 103 104 105 106 107 108

Frequency [Hz]1.3nV/Hz1/2 0.65nV/Hz1/2

• PMOS• 1/f noise amplitude at 77K is a factor of 2 lower than at 300K

• NMOS• comparable 1/f noise amplitude at 300 K and 77K• Lorentzian packet at 77K

8

Outline• Introduction of Cold Front‐End and ADC ASICs for LAr TPC• CMOS modeling and design for cold electronics• LAr FE ASIC: ‐ Optimizing input MOSFET under power constraintOptimizing input MOSFET under power constraint  ‐ Crosstalk of Adjacent Channels ‐ Performance of FE ASIC in MicroBooNE

• LAr ADC ASIC: ‐ ASIC Feature and operation Current mode Domino architecture‐ Current‐mode Domino architecture 

• CMOS lifetime study for cold electronics‐ Basics on hot‐carrier effects and lifetime ‐ CMOS lifetime in dc operation: analog front‐end ASICs‐ CMOS lifetime ac operation: logic circuits and FPGAsF th R&D f LA FE d ADC ASIC

9

• Further R&D for LAr FE and ADC ASICs

digitalBlock Diagram

Analog Front‐End ASICAnalog Front‐End ASIC

common register

channel registergain &mode bypasspeaking time &

modemode &

couplingtest

BGR, common bias, temp. sensordigital

interface

5

mode

wireanalogoutputs

.7 mm

• 16 channels

dual-stage charge amplifier filter ac/dc

16 channels

p

6.0 mm• charge amplifier, high-order anti-aliasing filter• programmable gain: 4.7, 7.8, 14, 25 mV/fC

• band-gap referenced biasing• temperature sensor (~ 3mV/°C)• 136 registers with digital interface• 5 5 mW/channel (input MOSFET 3 9 mW)

(charge 55, 100, 180, 300 fC)programmable filter

(peaking time 0.5, 1, 2, 3 µs)• programmable collection/non-collection

5.5 mW/channel (input MOSFET 3.9 mW)• single MOSFET test structures• ~ 15,000 MOSFETs• designed for room and cryogenic operation• technology CMOS 0 18 µm 1 8 V

mode (baseline 200, 800 mV)• programmable dc/ac coupling (100µs)

technology CMOS 0.18 µm, 1.8 V

10

Charge Sensor-Transistor Capacitance Mismatch under power constraint

n d gse C CENC

22 4 Ve kT

For a very large low noise PMOS transistor W~10mm, 

1 2

g

p

ENC

4 nm

e kT Hzg

L~250nm, W/L~4x10^4,  Cgs~10pF.    Area in 180 nm process:  160µm x 50µm=8,000µm2, equivalent to ~ 103 small transistors. 

The transistor can not match a large (nanofarad) sensor capacitance and we are left with linear dependence of ENC on detector capacitance:

For low power, CMOS in weak inversion:       1 3gsopt gdC C

det1 2 n

p

e CENC

11

Layout of Input PMOS in LAr FE ASIC

ENC vs. Power in the Input Cascode

3500

4000

Total ENCWhit

PMOSL = 270 nm

2500

3000White Low-frequency

ons]

CDET=200pFPK=1sT = 87 K

1500

2000

rms

elec

tro

1000

1500

EN

C [r

10m 100m 1 3 6 10 1000

500

10m 100m 1 3.6 10 100Power [mW]

12

ENC in LArASIC vs. peaking time of the anti-aliasing filter at 300K and 90K

White series noisewhich is dominant at short peaking1600

1800

T=300K at short peaking times decreasesthe most with temperature.

1200

1400

90Km.s

.)

T=77K

CDET=220pF

temperature.

The remaining noise is600

800

1000 target at 90K

measured

(ele

ctro

ns r.

m

noise is dominated by 1/fnoise, which is independent of the200

400

600

simulated input MOSFET

simulated whole front-end

EN

C (

independent of the peaking time.

0 1 2 30

200 s u ated put OS

Peaking Time (µs)

13

Submersion in Liquid Nitrogen (77K)

1414

Crosstalk Study: Basic Feedback Preamplifier ConfigurationNote: feedback function per se does not affect ENC (feedback components may add noise)

ix1

Preamp input equivalent circuit

(See slide 20, 21)

0fR Gequivalent circuit

1 oCRGain‐Bandwidth:

DC Gain:

Input resistance:

Cin

0fC G f hR Inductance:

Rise time constant:

oin

h f m f

RC g C

1st pole:

=>

=>0f

12 inf

h f f

CRC C

A periodic response for

15

Crosstalk of Two Adjacent Channels in LAr TPC 

v (t) Cf

C

Vo,signal(t)

vin(t)

R

Sense wireAmp Filter

Qi(t)

Vin,crosstalk(t)

Cw

Cct(~CW/3‐6)

Rin

Cf

Cw

Vo,crosstalk(t)( W/ )

Amp Filter

Rin

Sense wire

crosstalk peakcrosstalk ratioi l k

For tp = 1 µs, Cw = 200pF, Rin = 50 Ω

Cct crosstalk ratio 30 F 0 225%

3~2

ct in

signal peakC R

t

30 pF 0.225%40 pF 0.3%50 pF 0.375%

16

2 pt 60 pF 0.45%Notice that crosstalk decrease with longer peaking time!

For t = 1 µs C = 200 pF C = 50 pF R = 50 Ω

FE Output Signal vs. Crosstalk x 100 3~ ct inC Rcrosstalk ratioFor tp = 1 µs, Cw = 200 pF, Cct = 50 pF, Rin = 50 Ω 2 pt

vs(t)

v (t) x 100vct(t) x 100

17Courtesy of Sergio Rescia

Calibration SchemeCalibration Scheme

M1 MP M2 M2xN2M1xN1

C2 C2xN2C1 C1xN1

MNto

shaper

frominput wire

dual-stage chargeamplifier

M4M3

dis en

dual-stage charge amplifier

N1 = 20 N2 = 3, 5, 9, 16

C ≈ 180 fF

cal. pulse

CINJ ≈ 180 fF Integrated injection capacitance (10 x 18 µm²)Measured with high-precision external capacitanceIntegrated pulse generators on ASICs

184 300183 77INJ

fF at KC

fF at K

Integrated pulse generators on ASICs Charge sensitivity calibration of entire TPC during assembly, cooling and operation

18

Noise Contribution from Noisy Dielectric of FR4 Board --Testing Results

• Dissipation Factor D remained independent ofindependent of frequency between 1kHz‐1MHz while submerged in liquid g qnitrogen.

ENC Contribution vs. Board Capacitance at LAr

O b d t it f i i t FE ASIC i b t 10~20 FOn‐board trace capacitance from sensing wire to FE ASIC is about 10~20 pF=> ENC contribution: 60~70 electrons

Bandgap Reference:

Signal Measurements: programmable gain, peak time and baselineSignal Measurements: programmable gain, peak time and baseline

K77atV164.1

K300atV185.1VBGR

variation ≈ 1.8 %

]

non-collecting mode

gain [mV/fC]

K77atVm3.259K300atmV0.867

VTMP

Temperature Sensor:

itude

[a.u

.] gain [mV/fC]25147.84 7

~ 2.86 mV / °K

Am

pl Peak time [µs] 0.5 1.02.0

4.7 Programmable gain, peaking time and

baseline2.0 3.0

collecting mode

Maximum charge55, 100, 180, 300 fC

0 10 20 30 40 50

Time [µs]21

FE ASICs in MicroBooNEMi B NE ld th b dMicroBooNE cold mother board with 12 analog FE ASICs (on top and bottom planes, a total of 192 channels)

50 cold mother boards (8,256 channels) are installed on MicroBooNE TPC

Courtesy of Hucheng Chen 22

23

24

25

Outline• Introduction of Cold Front‐End and ADC ASICs for LAr TPC• CMOS modeling and design for cold electronics• LAr FE ASIC: ‐ Optimizing input MOSFET under power constraintOptimizing input MOSFET under power constraint  ‐ Crosstalk of Adjacent Channels ‐ Performance of FE ASIC in MicroBooNE

• LAr ADC ASIC: ‐ ASIC Feature and operation Current mode Domino architecture‐ Current‐mode Domino architecture 

• CMOS lifetime study for cold electronics‐ Basics on hot‐carrier effects and lifetime ‐ CMOS lifetime in dc operation: analog front‐end ASICs‐ CMOS lifetime ac operation: logic circuits and FPGAsF th R&D f LA FE d ADC ASIC

26

• Further R&D for LAr FE and ADC ASICs

ADC ASIC Features

• Performance parameters :– Sampling rate up to 2 MS/s– Measured resolution 11.7‐bit

O8P/NADC1612 bits

12 bitsINP15

INP16

O16P/N– Low power ADC,  ~ 5 mW/ch– Input range 0.2 V to 1.6 V– Clockless operation, ideal for low noise 

operation

FIFO

ADC15/

operation– Small area favorable for multi‐channel 

system• Features

ADC112 bitsINP1

FIFO EMPTY

CLK  IN

– Low power mode with < 1us wake‐up– Adjustable offset– Multiple options  for internal control signals

BIAS

ASIC Simplified Block Diagram

0.28mm

27

2.4 mm

Single ADC Layout

ADC Operation & Functional Block

•Phases of OperationSampling & Reset: Input sampled and cells resetMSB Conversion: MSB bits output

4 Phase ADC ConversionLSB Conversion: LSB bits outputEncode: Thermometer code from MSB and LSB converted to binary

•Sample and Hold (S&H) converts input voltage to current•Blocks of ADCBlocks of ADC

LSB, MSB and Encoder•Multi‐phase pattern generator•Bias generator common•Encoder: Thermometer to Binary.•MSB: 6 bits →1MSB cell = 64* 1LSB•1LSB cell = 500nA; 1MSB 64 LSB ll 32 A•1MSB = 64 LSB cells = 32µA

ADC Functional Block Diagram

28

ADC Design Modules: S&H CircuitADC Design Modules: S&H Circuit

1) All it h 2 l d1) All switches 2 closed: • A2 charges C2 to VIN      • A1 transfers C1 (previously charged to VIN‐1) to R

2) A1 charges C1 to VIN      • A2 transfers C2//C1 (pre‐charges to VIN) to R

3) M1, M2 current copier multiplier4) Settling time of S&H 50 ns 

FIFO integrated on chip for data storage

29

Current‐Mode Domino (CMD) Peak‐Detect ADCDeveloped in 2007 for small‐angle neutron scattering measurements

Low‐noise front‐end with unity gas‐gain Single‐pad induction (small‐pixel effect) Full size: 196 x 196 pad array (108 n/s) Pad 25 mm², 5 pF, rate 5 kHz / pad

• 64 channels ‐mixed signal• low‐noise charge amp.• current‐mode peak detector ‐ 6‐bit ADC• 18‐bit timestamp110 l 1 5 W/ h l• 110 e‐ resol., 1.5 mW/channel

• sparse readout and FIFO• ASIC successfully produced in large numbers

300T = 300K1.6% on

150

200

250

4µs

2µs1µs

Peaking Time 500ns

NC

[rm

s el

ectro

ns]

neutron peak

0 1 2 3 4 5 6 7 8 9 10 1150

100

Dashed Lines: Theoretical Fitting

EN

External Input Capacitance [pF]

6.6 x 8.5 mm²

Image from Cd foil, 48x48 pad array

30

External Input Capacitance [pF]

• Coded aperture version for Nonproliferation• Large 1 m² version being developed for ANSTO*

*Australian Nuclear Science and Technology Organization

Two‐Step CMD ADC Architecture for LArPhase 1: selects n/63 macro‐currents Ii (32 µA/cell, 150 ns)

V

sampled current I v1

s1as1b v2

s2as2b

v34s63a

1

I1s1b c1

2

I2s2b c2 I63

64x500nA

Phase 2: on residual current, selects n/64 micro‐currents ii (500 nA/cell, 250 ns)

v1s1a

s1b c1v2s2a

s2b c2v64s64a

31

i1c1 i2

c2 i64500nA

31

LAr ADC Layout 

32Size ~ 4,500 x 6,100 µm²

Outline• Introduction of Cold Front‐End and ADC ASICs for LAr TPC• CMOS modeling and design for cold electronics• LAr FE ASIC: 

d‐ Optimizing input MOSFET under power constraint  ‐ Crosstalk of Adjacent Channels ‐ Performance of FE ASIC in MicroBooNEPerformance of FE ASIC in MicroBooNE

• LAr ADC ASIC: ‐ ASIC Feature and operation ‐ Current‐mode Domino architecture 

• CMOS lifetime study for cold electronicsBasics on hot carrier effects and lifetime‐ Basics on hot‐carrier effects and lifetime 

‐ CMOS lifetime in dc operation: analog front‐end ASICs‐ CMOS lifetime ac operation: logic circuits and FPGAs

33

• Most failure mechanisms (e.g. electromigration, stress migration, time‐dependent dielectric breakdown, and thermal cycling) are strongly temperature

IntroductionCMOS Lifetime at Cryogenic TemperaturesCMOS Lifetime at Cryogenic Temperatures

dependent dielectric breakdown, and thermal cycling) are strongly temperaturedependent [exp(‐const./kT)] and become negligible at cryogenic temperature.

•The only remaining mechanism that may affect the lifetime of CMOS devices atcryogenic temperature is the degradation (aging) due to channel hot carriercryogenic temperature is the degradation (aging) due to channel hot carriereffects (HCE).

• The degradation mainly concerns NMOS devices ‐ PMOS usually exhibits alif ti h l th NMOSlifetime much longer than NMOS.

• Lifetime due to HCE aging: A limit defined by a chosen level of monotonicdegradation in e.g., drain current, transconductance, threshold voltage. Thedevice “fails” if a chosen parameter gets out of the specified circuit designrange. This aging mechanism does not result in sudden device failure.

• The lifetime due to HCE at both the cryogenic temperature, as well as at roomy g ptemperature, is limited by a predictable and a very gradual degradation (aging)mechanism which can be controlled or avoided by device design and operatingconditions. In this study we have been following the basics established in the

34

literature, e.g., Hu et al. (1985), and the practices adopted more recently byChen&Cressler et al. (2006), as well as by industry.

34

Basics on Hot Carrier Effects (HCE) ‐1Basics on Hot Carrier Effects (HCE) ‐1

• Some hot electrons exceed the energy required to create an electron‐hole pair,                , resulting in impact ionization. Electrons proceed to the drain. The holes drift to the substrate. The substrate current,

(1)

1.3i eV

1i mq E

b dI C I e ( )• A very small fraction of hot electrons exceeds the energy required to create an interface state (e.g., an acceptor‐like trap), in the Si‐SiO2interface,                  , for electrons (~4.6eV for holes). This causes a change in the transistor characteristics (transconductance, threshold, intrinsic 

3.7it eV

1sub dsI C I e

gain). The time required to change any important parameter (the changes in different parameters are correlated) by a specified amount (e.g., gm by ‐10%) is defined as the device lifetime. It can be calculated as,

(2)it mq EWC e

q = electron chargeλ=electron mean free pathEm= electric field  Id = drain‐source current

dsatdsm VVE

2ds

C eI

Ids= drain‐source currentW= channel widthC1, C2 ‐ constants

• Isub is a monitor for all hot‐electron effects and it is the best predictor of device lifetime, because all observable hot l t ff t ( l t i l d ti l) d i b d i i f th i h l l t i fi ldelectron effects (electrical and optical) are driven by a common driving force – the maximum channel electric field 

Em , which occurs at the drain end of the channel.• From (1) and (2), the substrate current is connected to the lifetime (defined by any arbitrary but consistent criterion) by

1 1.3 ; 3.7 4.2i iteV eV

35

1

iti

ds

sub ds

I WI I

1.3 ; 3.7 4.2

2.9 3.2

i it

it

i

eV eV

Basics of Hot Carrier Effects ‐2 Basics of Hot Carrier Effects ‐2 

• Substrate current is a monitor of impact ionization and of  interface states creation

• “Degradation” – a decrease in Ids and gm and increase in Vth is due to interface state creation

• A lower temperature results in a slightly increased mean free path λ increasing the substrate current Isub . Degradation  of Vth , Ids and gm is independent of sub th ds m temperature if the product  λEm≈ λVds is kept constant.

Accelerated lifetime test at any temperature (well established by foundries):• Accelerated lifetime test at any temperature (well‐established by foundries):transistor is placed under a severe electric field stress (large VDS), to reduce thelifetime due to hot‐electron degradation to a practically observable range, by adrain source voltage considerably higher (~80%) than the nominal voltage

36

drain source voltage considerably higher ( 80%) than the nominal voltage.

Stress Test Flow Chart and Layout of test NMOS transistorsStress Test Flow Chart and Layout of test NMOS transistors

2µm

Test transistors, NMOS L=180nm, W=10µm (5 fingers x 2µm), designed to have negligible IR drop and power dissipation <15mW in stress tests to prevent p p ptemperature change due to self-heating.

Vds=3.2V,77K Vds=2.8V, 77KVds=3V 77K

100

Vds=3V,77K Vds=2.8V, RT Vds=3V,RT Vds=3.2V,RT

10atio

n [%

]

10

gm d

egra

da

37101 102 103 104 105 1061

Stress time [s]

Measurement Type I:    “Stress Plot”

Accelerated Lifetime Measurements (180 nm)Accelerated Lifetime Measurements (180 nm)

itdsI

1ln

102

103

Vds=2.8V

yp

1

ds asub ds

I WI I

1E7

1E9

1.8V

Lifetime ~ 3200 yrs at Vds=1.8V, 77K

1.7Vdsatdsm VVEqW

ln

101

10

Vds=2.8VVds=3.1V

Vds=3.0V

/W [s

*A/

m] 300K Slope ~3.10

10

1000

100000

W (s

*A/

m)

300K

77KASIC design: Vds<1.5V

100 Vds=3.0V

Vds=3.2V

Vds=3.2V

*Id

s/

77K Slope ~2.941E-3

0.1

10

*I D

S/W

3.2, 3.1, 3.0, 2.8 V Vds<1.8V

Vds 1.5V

• If the measured points at both 300K and 77K are close to the characteristic slope for the

10-2 10-1 10010-1

Isub/Id

0.1 0.2 0.3 0.4 0.5 0.61E-5

1/VDS(V-1)

f p p finterface state generation, , it confirms that the degradation follows basicrelations for interface state creation. Substrate current must be measured for this stress plot.

3it ia

• The lifetime prediction plot (right) can be derived from the stress plot (left), or fromdi f i h i h b

38

direct measurements of τ vs. Vds , without measuring the substrate current

Measurement Type II:  Substrate Current  Density Isub /W  vs 1/Vds10-4 NMOS L=180nm, W=10µm (5x2µm), Vgs=1V L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm

1E-8L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm

1E-81E-8

10-7

10-6

10-5

10Stressed lifetime=798s at Vds=3.2V, 77K

Stressed lifetime=8506s at Vds=3.2V, 300K

Lifetime ~ 5500 yrs at Vds=1.8V, 77K

L=360 nm;       ‐”‐ ; Ids/W=1.0µA/µmL=9 µmL=270 nmL=9 µm

)

1E-12

1E-11

1E-10

1E-9 L=360 nm;       ‐”‐ ; Ids/W=1.0µA/µmL=9 µmL=270 nmL=9 µm

)

1E-12

1E-11

1E-10

1E-9

1E-12

1E-11

1E-10

1E-9

10-11

10-10

10-9

10-8

Isub

/W [A

/m

]

300K 77K

3subI

Isub

/W (A

/ m)

1E-16

1E-15

1E-14

1E-13

Isub

/W (A

/ m)

1E-16

1E-15

1E-14

1E-13

1E-16

1E-15

1E-14

1E-13

0 1 210-14

10-13

10-12

10

ASIC design: Vds<1.5V

1E-20

1E-19

1E-18

1E-17

1E-20

1E-19

1E-18

1E-17

1E-20

1E-19

1E-18

1E-17

1/Vds [1/V]Vds=1.8V

• One order of magnitude in substrate current  Isub corresponds to three orders of magnitude in lifetime. At 77 K, Vds = 1.8 V projects a lifetime of 

1.5V    1.0V     0.5V   0 2 4 6

1E 20

1/Vds (1/V)1.5V    1.0V     0.5V   0 2 4 6

1E 200 2 4 6

1E 20

1/Vds (1/V)

ds ~5500 years. • Isub/W and 1/Vds distribution for all transistors in the analog front‐end ASIC for LAr TPC (TSMC 180nm, 1.8V node) shows that all transistors are well below 

39

nominal voltage of 1.8V and at low Isub; Reduced Vds < 1.5 V results in essentially making  HCE negligible and a very long extrapolated life time.

5

10-4

pre stress post stress rt

(Hz)

]

5

10-4

t(Hz)

]

pre stresspost stress

Noise Degradation: Less Degradation in PMOS Noise Degradation: Less Degradation in PMOS NMOS L=180nm, W=10µm (5x2µm) PMOS L=180nm, W=10µm (5x2µm)

10-7

10-6

10-5 6000 s -> 10% gm degradation

inpu

t noi

se [V

/sq

10-7

10-6

10-5

nput

noi

se [V

/sqr

t post stress12960 s -> 2% gm degradation

300 K 300 K

101 102 103 104 105 106 107 10810-9

10-8

Equi

vale

nt i

Frequency [Hz]101 102 103 104 105 106 10710-9

10-8

Equi

vale

nt in

Frequency [Hz]Frequency [Hz] Frequency [Hz]

10-5

10-4

10-3

[V/s

qrt(H

z)] pre stress

post stress 920 s -> 10% gm degradation

post stress3900 s -> 15% gm degradation 10-6

10-5

10-4

pre stress post stress

1500s stress -> 2% degradation of gm post stress

5000s stress -> 3.5% degradation of gm[V/s

qrt(H

z)]

10-8

10-7

10-6

alen

t Inp

ut n

oise

[ 3900 s 5% g deg adat o

10-8

10-7

10 6 5000s st ess 3 5% deg adat o o g

alen

t inp

ut n

osie

77 K 77 K

• PMOS: much less degradation than NMOS

101 102 103 104 105 106 107 10810-9

10

Equi

va

Frequency [Hz]101 102 103 104 105 106 10710-9

Equi

va

Frequency [Hz]

40

PMOS: much less degradation than NMOS• PMOS is used in the preamp input and, by design, it is the main noisecontributor in the front‐end ASIC.

CMOS in dc Operation (180nm, 130 nm and 65 nm)CMOS in dc Operation (180nm, 130 nm and 65 nm)• Reducing Vds at 77K by ~ 6% makes the lifetime an order of magnitude longer inll th t h l i → id ti l l 1/ V t ti i l V

L 65 nm 130 nm 180 nm∆Vds/Vds: ~5.3% ~5.7% ~5.5%

all three technologies → identical slope τ vs 1/ Vds at respective nominal Vds

(F lid 6)for τ2/τ1=10

130 nm 65 nm

(From slide 6)

41(Data for 130nm and 65nm, courtesy of G. Wu_SMU&FNAL) 41

Why is the dependence of Lifetime on Vds so strong?

Why is the dependence of Lifetime on Vds so strong?strong?strong?

The lifetime is given by,

21 1

it he it heC e eI W I W

Electrons in the MOS channel reach energies well above thermal both at  300K and at 77K . However the mean electron energy,                        , at the electric field 100he mq E meV

2ds dsI W I W

in the range Em ≥100kV/cm. At 77K it is slightly higher,Only a tiny fraction of “hot” electrons reaches the much higher energy                required to create an interface state. This makes the exponent in the relation for the lif ti l

he mq77 300 1.06he K he K

3.7it eV

lifetime very large,

Si h i f lif i f li h l diff l f V i

40 4it it

he mq E

E VSince                           ,  the ratio of lifetimes for two slightly different values of Vds is given by,

21ln 1it dsVV

2 11.06 10dsVfor

V

m dsE V

2 1he dsV 1 2dsV

Much Longer Lifetime with Longer DeviceMuch Longer Lifetime with Longer Device

• By increasing device length the 10%• By increasing device length, themeasured lifetime increased by 1‐2orders of magnitude

10%

65 nm

@ 77 K

10%

10%

180 nm

130 nm

43(Data for 130nm and 65nm, courtesy of G. Wu) 43

CMOS Lifetime in AC Operation: Logic Circuits and FPGAsCMOS Lifetime in AC Operation: Logic Circuits and FPGAs

• Long established (e.g. Quader&Hu et al.(1994), White&Bernstein (2006)] and adaptedb f d i id i h i f h d h f ff iby foundries: considering the ac stress as a series of short dc stresses, each for effectivestress time teff during the switching cycle 2tr , strung together.• The lifetime of digital circuits (ac operation) is extended by the inverse duty factor1/(f t ) compared to dc operation This factor can be quite large at ≤130nm1/(fck teff ) compared to dc operation. This factor can be quite large at ≤130nm.• Rough estimation of teff [Quader&Hu et al. (1994)]: 

teff/tr≈1/4,       tr = the gate voltage rise time for NMOS Quader&Hu et al. (1994)

• Inverse duty factor at                                                                                                       maximum switching frequency fck ≤1/2tr  :

1 8

f

• Note that the substrate current flows only during a small fraction of  rise/fall time while  Vds is high. 

ck efff t

More detailed estimation can be found in the design manuals of major foundries. 

A standard method for evaluating the digital circuit lifetime is to apply accelerated stress test on a Ring Oscillator (RO) and observe the RO frequency degradation under

44

stress test on a Ring Oscillator (RO) and observe the RO frequency degradation under severe stress. Degradation of drain current leads to increased rise (propagation) time and reduced frequency.

Th t th d l d t d f ll th t d d

FPGA Lifetime Study: Stress methodology

• The stress methodology we adopted follows the standard Accelerated Lifetime Strategy. The experiment is composed of two steps performed alternately: – Measurement Step: measure frequency of ring oscillator(RO) at Vccint=1.2V for 30s.A l t d St St l t d d ti f RO t– Accelerated Stress Step: accelerate degradation of RO at higher core voltage. Stress device (e.g. Vccint=1.8V) for 3600s.

• In each measurement step, frequency measured from 15s to 30s are averaged for reliable result.Th d d i i i i d fi d 3% d d i f h• The degradation criteria is defined as 3% degradation of the frequency which is widely adopted [J. Zhang and S. S. Chu, 2002].

45

Experiment Block Diagram and FPGA Floor Plan

Control LogicExperiment Block Diagram

Control Logic (locked down in the area with Logic‐Lock)

A f 30 RO Af h d i i d dArray of 30 ROs. After the device is stressed under one voltage, another array of ROs will be locked down for stress. 

FPGA Floor Plan

46

RO Frequency Measurement

• Frequency of RO is stable with less than 0 1% variation• Frequency of RO is stable with less than 0.1% variationfrom peak to peak

47

Freq enc of 30 RO Channels F Hi t f 30 RO Ch l

Statistical View of the Degradation of 30 RO Channels

Frequency of 30 RO Channels Frequency Histogram of 30 RO Channels.

• μ=0.88, σ=0.087• The mean of 30 RO Channels is used for each stress point to 

calculate the frequency degradation  

48

Lifetime Projection of FPGA

@400MHz

• Traditionally,  lifetime is projected by empirical equation                        .  The target operation frequency is 400MHz while the RO is stress under 1.7GHz. To include the effect of higher stress frequency,  frequency acceleration factor      is introduced which is defined as                   . The equation for lifetime projection is modified as:

F ll i th b ti lif ti f FPGA t 77K i j t d t b• Following the above equation,  lifetime of FPGA at 77K is projected to be                    years for 3% degradation criteria, giving a wide margin over the physical target (>20 years) .

49

Regulator at 77K‐Two Year Continuous Non‐stress TestRegulator at 77K Two Year Continuous Non stress Test

A 2‐year continuous non‐stress test of six regulators biased at different operating condition has b f d Th l f h l i bl h f ll f

50

been performed. The output voltage of the regulator is stable over the full range of two years. Voltage drops are due to power glitch (power supply or computer shut down), movement of experiment setup, ect.

Regulator Stress Test

Block diagram of TPS74201

51

Lifetime Risk Analysis and Amelioration Lifetime Risk Analysis and Amelioration 

• To alleviate the lifetime risk, custom ASIC should be designed for one or two ordersof magnitude longer lifetime than 30 years, by selection of Vdd and L, essentially toget out of the region of degradation measurable after 30 years.g g g y

• The lifetime issue for complex synthesizable logic circuits should be treatedseparately from the question of how good the transistor/circuit models for lowtemperature operation might be The separation of the two issues is easilytemperature operation might be. The separation of the two issues is easilyaccomplished by providing a large lifetime margin, so that the circuit and processmargins can be treated independently of aging.

• Note that rise/fall times are faster at 77K, even at reduced Vds, than at 300K, andthe ASIC data processing speed performance need not suffer due to conservativelarge lifetime margins.

• The positive lifetime results on the FPGA and voltage regulator suggest, for their use in LAr, the lifetime shouldn't represent a concern. The operation and programmability of FPGAs and voltage regulators has been subject of a separate 

52

study.

Further R&D on FE and ADC ASICs FE ASICFE ASIC

• Two design issues to be addressed in FE P2 submission: V i ti f bi t d t t d i ti‐ Variation of bias current due to unsupported‐wire motion, 1‐GOhm resistor is necessary on board to bring channels up‐ Imperfect pole‐zero cancellation in cold operationImperfect pole zero cancellation in cold operation

• Suppression of power supply noise from regulator in cold operation

ADC ASICADC ASIC 

• Stuck code (more severe in cold operation)

53