From Spin Torque Random Access Memory to Spintronic Memristor
Transcript of From Spin Torque Random Access Memory to Spintronic Memristor
X. Wang −−−− 2
Contents
Spin Torque Random Access Memory:dynamics characterization, device scale down challenges and opportunities
Spin Torque Memristor:concept, device and application examples
X. Wang −−−− 3
Spin Torque Random Access Memory (SPRAM) Working Principle
Select Transistor
Bottom electrode
MTJ
Top electrode
Reference layer
Tunneling insulating barrier
Free layer
Magnetic tunneling junction (MTJ)
. (1)
Integrate magnetic tunneling junction (MTJ) with CM OSReading through magneto-resistance principleWriting through spin torque excitation
X. Wang −−−− 4
SPRAM Switching Behavior
I
V0
RH
RL
+-
RAP
1
2
3
4
5
6
MTJ static picture
Magnetic field ( Oe)
Res
ista
nc e
(O
hm
)
Spin torque switching asymmetry for a field balanced MTJ stack
Reference: X. Wang, W. Zhu, D. Dimitrov, Phys. Rev. B, 79, 104408, 2009.
Ref: Y. Chen, X. Wang, H. Li, D. Dimitar, H. Liu, International Symposium on Quality Electronic Design, 2008.
MTJ coupled with CMOS
MTJ switching asymmetry
X. Wang −−−− 5
SPRAM System Dynamical Approach: Quantum-Micromagnetic-SPICE
( )( )BLSL)(
orSLBL)(
dt
dVC
dt
dVC
M
DDM
DBDB
GDGD
TDBGDM
→−=⋅→−=⋅
⋅=
−⋅=
+=+
VtRI
VVtRI
I
I
IIII
Dynamic CMOS circuit
CMOS I-V curve,equivalent capacitors,etc
Macroscopic magnetic(size, Ms, etc)
Dynamical approach
BL
SL
WL
CGD CDB
CGS
CSB
CGB
VDD
5
10
15
5
10
15
20
25
Dynamic Magnetization
MTJ electronic spin transport(band structure, tunneling)
Reference: X. Wang, W. Zhu, D. Dimitrov, Phys. Rev. B, 79, 104408, 2009.
Ref: X. Wang, Y. Chen, H. Li, D. Dimitar, H. Liu,
IEEE Tran. On Magn., 44(11), 2470, 2008
Quantum electronic spin transport
X. Wang −−−− 6
Challenge for SPRAM to Scale Down
As magnetic device scales down, with CMOS driving s tengthdecreasing, achieving fast nanosecond time scale magnetization switching and maintaining thermal sta bility at years time scale become a challenge.
Field driving: switching field scales up with 1/volume or 1/surface dimension
Spin torque driving: switching current density scales up with 1/volume or 1/surface dimension
1500 2000 2500 300070
80
90
100
110
120
130
140
150
MTJ Resistance (Ohm)C
MO
S d
rivin
g cu
rren
t (uA
)
22nm x 100nm CMOS22 nm x 45 nm MTJ, 17.4F2
22nm x 75nm CMOS22nm x 45nm MTJ, 13.2F2
22nm x 45nm CMOS22nm x 22nm MTJ, 9F2
X. Wang −−−− 7
Challenge for SPRAM to Scale Down
As device scales down, increased variability is another challenge.
Spin torque MRAM device to device variations reduce sensing and writing margins
Variation of single device different switching
X. Wang −−−− 8
Current Reduction Through Magnetization Dynamics
plane-outfactor demag: plane,-in factors demag:,
))((M
current switching critical2s
zyx
xzyz
DDD
DDDDV −−∝
ηα
)(M :mequilibriuin energy Stable 2s xy DDV −
Dz >> Dx, Dy, different scaling behavior of MTJ writing current magnitude and thermal stability energy
Road leads to same scaling of switching current and thermal stability energy
Geometric wise: thin film for TMR etc.Magnetization dynamics wise: Symmetric magnetization motion: Dz =Dy
X. Wang −−−− 9
Current Reduction Through Magnetization Dynamics
Constant p
olariza
tion dire
ction so
lution
Optimal time varying polarization direction solution
0 0.2 0.4 0.6 0.8 1 1.2 1.4 x 10-8-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time (sec)
Nor
mal
ized
mag
neti
zati
on M
z/M
s
RF frequency time varying polarization angle Composite material stack
Hard magnetic layer to keep thermal stability
Soft magnetic layer to decrease switching field/current magnitude
X. Wang −−−− 10
Increase insulating layer thickness only, RA increases 5 times, critical switching voltage only increases 2.5 times
Ref: X. Wang, W. Zhu, Y. Zheng, Z. Gao, H. Xi, INTERMAG 2009
MTJ with spin moment conservation layer between free layer and top cap layer
More opaque barrier, less magnetization precessing induced spin pumping, effective damping reduction
Current Reduction Through Electronic and Spin Transport Across Interface
Ref: Y. Zheng, W. Zhu, X. Wang, Z. Gao, D. Wang, D. Dimitrov et. al. submitted to Appli. Phys. Letters
-50
-30
-10
10
30
50
70
90
110
130
150
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
J(MA/cm^2)
MR
(%)
Single
Double
-1.0
-0.5
0.0
0.5
1.0
0.000001 0.0001 0.01 1
tp(s)
Jc(M
A/c
m^2
)
Double AP->P
Double P->AP
Dual tunneling barrier, critical switching current down to 0.6MA/cm2, quantum confinement effects ?
X. Wang −−−− 11
Variation Controlling at Device Level
Unique Device characters leads to new sensing scheme
destructive
non-destructive
Self-reference sensing
Ref. Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu and T. Zhang, Design, Automation & Test in Europe Conference and Exhibition, 2010.
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
-1000 -500 0 500 1000
MTJ
Re
sis
tan
ce
(ΩΩ ΩΩ
)
Sensing Current (µµµµA)
40ns pulse
DC extrapolation
RL
IR
RH
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Variation Controlling at System Level
Reduce switching current requirement by intentional ly move away from worst case scenario design
a smaller-than-worst-case transistor sizing approac h. For 256Mb SPRAM design at 45nm node, under a normalized write current threshold deviation of 2 0%, the overall memory die size can be reduced by more than 20% compared with the conventional worst- case transistor sizing design.
Ref: W. Xu, Y. Chen, X. Wang, and T. Zhang, 46th Design Automation Conference, 2009.
X. Wang −−−− 13
Surface anti-ferromagnetic coupled (AFC) magnetic layer with relatively low Curier temperature:At room temperature, the AFC coupling provides surface anisotropy to maintain thermal stability of the square magnetic element.During the writing process, the joule heating of spin torque current raises temperature of AFC surface magnetic layer above Curier temperature and the AFC induced surface anisotropy disappears. The element can be switched at low threshold current.
0
100
200
300
400
500
0 20 40 60 80 100 120 140
6 nsec
10 nsec
D (nm)
I (µA
)
0
100
200
300
400
500
0 20 40 60 80 100 120 140
6 nsec
10 nsec
D (nm)
I (µA
)
D (nm)
Cel
l siz
e (u
m2 )
1Gb
256Mb
64Mb
0.01
0.10
1.00
0 20 40 60 80 100 120 140
65nm, 6nsec
65nm, 10nsec
40nm, 6nsec
40nm, 10nsec
D (nm)
Cel
l siz
e (u
m2 )
1Gb1Gb
256Mb256Mb
64Mb64Mb
0.01
0.10
1.00
0 20 40 60 80 100 120 140
65nm, 6nsec
65nm, 10nsec
40nm, 6nsec
40nm, 10nsecRA = 12.5 Ωµm2
Write current decreases with decreasing memory element dimension D. Meanwhile, the MTJ resistance increases with decreasing memory element dimension. For a given technology node, an optimal memory cell size can be found due to the tradeoff between critical switching current and MTJ resistance
Required heating current
Heat Asssited Solutions
Ref: H. Xi, J. Sreicklin, H. Li, Y. Chen, X. Wang, and Y. Zheng, Z. Gao, M. Tang, IEEE Trans. Magn, 46,no. 3, 860, 2010
From nonlinear resistor point of view:
reversible branch: 11 to 10, 00 to 01
Irreversible branch: 00 to 10
demonstrated multi-bit MTJ devices
Ref: X. Lou, Z. Gao, D. Dimitrov, and M. Tang, Appli. Phys. Letters, 93, 242502, 2008
00000000
01010101
11111111
10101010
MTJ Memristor and Mutibit Data Storage and Logic
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From memristor point of view:
Switching from 00 to 10 and from 00 to 01 are all possible by adjusting pulse width
Different slope, switching depends upon integration of current, not current magnitude !
0 0.5 1 1.5 2 2.5 3 x 1080
200
400
600
800
1000
1200
1400
Inverse of pulse width (sec -1)
Sw
itchi
ng c
urre
nt (
uA)
switch00->01
switch00->10
more elongated shape and less surface area
MTJ Memristor and Mutibit Data Storage and Logic
Ref. X. Wang, Y. Chen, Design, Automation & Test in Europe Conference and Exhibition, 2010.
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Chua (1971) proposed memristor for
logic completeness of circuit element
Leon O. Chua, Memristor-the missing circuit element, IEEE Trans. Circuit Theory, vol. 18, no. 5, 1971
Memristor as Fourth Circuit Element
Resistor
Memristor
What makes memristordifferent from an ordinary constant resistor or even a current or voltage dependent nonlinear resistor: memristance is a function of charge, which depends upon the hysteretic behavior of the current (or voltage) profile.
q
Vcapacitor
∫= Idtq
∫= Vdtϕ
What makes memristor different from a capacitor or inductor is the ability to accumulate current or voltage information at constant voltage or current.
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Memristance in Resistive Memory Stack
1) J. M. Tour and T. He, Nature 453, 42, (2008).2) D. B. Strukov; G. S. Snider; D. R. Stewart and R. S. Williams, Nature, 453, 80, (2008)
low resistance state
high resistance state
1) Nano-scale two terminal device as two connecting resistors (doped region and undoped region)
2) Bias electric current drives the front of the doped region
measured
simulated
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Spintronic Memristor Through Spin Torque Induced Magnetization Motion
Spintronic memristor: resistance depends upon the integral effects of its current profile.
GMR/TMR device: resistance depends upon magnetization state
Spin Torque device: current electronic spin changes the magnetization state of the device. The magnetization state of the device depends upon the cumulative effects of electron spin
excitations.
X. Wang, Y. Chen. H. Xi, H. Li, D. Dimitrov: IEEE electronic device letters vol. 30, no. 3,
pp.294, 2009.
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Domain Wall Memristor and Temperature Sensor
interactions between macroscopic coherent magnetic structures and random fluctuations
X. Wang, Y. Chen, Y. Gu, H. Li: IEEE electronic device letters vol. 31, no. 1, pp.20, 2010.
Nano-scale feature size, low cost, and mature integration technology with the CMOS process.
Targeting the highly integrated on-chip thermal detection applications
X. Wang −−−− 20
Memristor for Power Management
The ability to accumulate current/voltage through constant current and/or voltage driving strength: power monitor device
Negative feedback: power control device
∫∫ == IdtVVIdtE
Ref. X. Wang, Y. Chen, Design, Automation & Test in Europe Conference and Exhibition, 2010.
X. Wang −−−− 21
Memristor for Data Security
Question: Administrator and user. Design a scheme to fight against following action: after reading the stored data information, the user tries to restore the device state to the same state as before reading, so that administrator could not find whether the data has been accessed.
Solution depends upon whether the user is given the limited or the same authority on device writing and reading compared to thatof the administrator. For the case of user with limited reading and/or writing authority, data informa tion security task can beachieved more easily. For limited writing authority case, user may not be able to restore the device to the state set by the administrator before. For reading limited case, the user may not know the state of the device set by the administrator.
A solution giving user and administrator the same authority on reading and writing:
1) Writing process: administrator sets high resistance state (0)fully saturated and low resistance state (1) partially saturated.
2) Reading process: two constant voltage pulses excite device afew times (order of 10). One pulse pushes domain wall toward high resistance end and the other pulse tries to push domain wall toward low resistance end.
3) The device reports two values for reading: 1) final state of the device close to high or low resistance state (High or Low) and 2) whether the device resistance has been significantly changed during reading (Yes or No).
0.8 1 1.2 1.4 1.6 1.8 2 2.20
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Second pulse magnitude
Fin
al d
omai
n w
all s
ettle
d po
sitio
n
Administrator reads the data using pulses with a particular second pulse driving strength.
Ref. X. Wang, Y. Chen, Design, Automation & Test in Europe Conference and Exhibition, 2010.
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Path to Future: Potentials
GMR with spin valve structure TMR with tunneling structure
New geometry structures
Physics process is clear and scaling behavior is well understood: controllable and tunable device
Easily integration on top of CMOS
New material
Y. V. Pershin and M. Di Ventra, Phys. Rev. B, 78, 113309, 2008
Spin blockade, half-metallic material