Frequency Synthesizer for Multi-Band Multi- Standard Base ......3G LTE WiMAX TDD FDD FDD FDD TDD TDD...

IHPIm Technologiepark 2515236 Frankfurt (Oder)

Germany

IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2008 - All rights reserved

Frequency Synthesizer for Multi-Band Multi-Standard Base Station Application

Sabbir A. Osmany, J. Christoph Scheytt


Outline

Introduction

Synthesizer architecture

Phase noise in PLLs

Design of subcircuits

Measurement results & comparison (VCO)

Conclusions


Introduction

Variety of wireless standards for different application scenariosCurrently system design ( HW/SW) is done separately for every standard

=> Limited hardware reuseFeasible standards and frequency bands to be served with one hardware

=> MxMobile ( Multi-Standard Mobile Platform)Need for One Common Synthesizer Module !


Introduction

Tuning range 700 MHz … 4 GHzS S B Noise -120 dBc/Hz @ 2 MHz

Harmonic spurs < - 20 dBcNon-harmonic spurs <-65 … -90 dB

Step size 5 MHz

… …

700 1000 1800 2500 3500 MHzGSM

UMTS

3G LTE

WiMAX

TDD

FDD

FDD FDD

TDDTDD

TDMA

TDMATDMA

Atleast 11 sub bands have to be served

And furthers Radio Frequency bands

in future?


Introduction

SiGe Technology

High-frequency performance: comparable to GaAs, better than CMOSLow-frequency phase noise: much better than CMOS, better than GaAsHigh-frequency phase noise: better than CMOS (@ same technology node),

inferior to GaAsCost: cheaper than GaAs, more expensive than CMOS in volume

Combines advantages SiGe HBTs with complexity of CMOSBiCMOS process allows for combining analog and digital functions(channel selection) on the same chip

SiGe BiCMOS Technology

SiGe BiCMOS technology perfectly suited



:Rf

VCO

20..28 GHz

f out

700..4400 MHz:M

control register

fREF

R=2..255

serial interface

8 5 3

N:1

M=3/4/5/6/8/10/12/16

VCO1LFCPPFD

fPFD

N=3 … 2048

311

VCO2

:2

Type –II, Single loop PLLVCO frequency ~ 20 - 28 GHz (Qind ~ f, Qvar ~ 1/f )5 bit digital tuning and fine analog tuningLow PFD/CP, loop filter noise gain



20..28 GHz

f out

700..4400 MHzmux

:2:2 :2:2 :2 625 – 875 MHz

:3

:5

:3

:5

:3

833 – 1167 MHz

1 – 1.4 GHz

1.25 – 1.75 GHz

1.67 – 2.33 GHz

2 – 2.8 GHz

2.5 – 3.5 GHz

3.33 – 4.67 GHz

band selection

VCO1

VCO2

High-frequency VCOs + high-speed dividersLow-noise wideband solution


Phase Noise in PLLs

Reference noise = > Low-pass filtered and amplified by NVCO noise => High-pass filteredCharge pump noise => Low-pass filteredLoop filter noise => Band-pass filtered

PFDφREF φoutVCOcharge LPFpump

noisy phase of crystal reference(free-running oscillator)

VCO with high phase noise(phase-locked to reference)

_ N


Phase Noise in PLLs

PLL phase noise spectrum andits components

Phase noise for different chargepump currents

Charge pump dominantes

Reference noise dominantes

VCO dominantes

Higher charge pump current reduces in-band phase noise,(charge pump noise PSD ~ , transfer function ~ )Higher current increases phase noise at very large offset

CPI 21 CPI


Design of subcircuit (VCO)

VCO2

VCO1

14

20..24 GHz

24..28 GHz

Analogtuning

Digitaltuning

Vbb

MIM capacitors

Vout

Output buffer incommon emitter

configuration

sw1 inv

sw2 inv

Vctrl

sw3 inv

sw4 inv

1 bit core selection, 4 bit digital tuning

Differential, Colpitts type oscillator

Usually for digital tuning, MOS switch is used to ON/OFF mim capacitor

degrade phase noise

Our approachuse varactor in digital manner


Design of subcircuit (VCO)

D=160µW=20µ

Silicon-substrate (p-type)

n-well

Gate (Poly-Si, n+)n+

signalVctrl

symmetry line

charge extraction (p+)

Accumulation mode varactors

Cmax / Cmin of varactor: ~ 3

Measured quality factor ~ 14

Fifth Al metal layer (thickness 3 µm)

Simulated Q ~ 20

VaractorInductor


Measurement results (VCO)Tuning curve

20

21

22

23

24

25

26

27

28

29

0 0.5 1 1.5 2 2.5 3 3.5

Vctrl [V]

Freq

[GHz

]

S_00000S_00001S_00010S_00011S_00100S_00101S_00110S_00111S_01000S_01001S_01010S_01011S_01100S_01101S_01110S_01111S_10000S_10001S_10010S_10011S_10100S_10101S_10110S_10111S_11000S_11001S_11010S_11011S_11100S_11101S_11110S 11111

VCO tuning curve

VCO spectrum

Measured tuning range:20.4 - 23.8GHz, 25.1 – 28.5GHz

VCC =5V, Ic= 4.5mA


Measurement results & comparison (VCO)

-112 dBc/Hz @ 1 MHz

-90

-100

-105

-110

-10 -100

-95

Frequency [GHz]

Phas

e N

oise

[dB

c/H

z]

6 dB / octave

This work

1 2

34

5

Measured phase noise at 1 MHz offsetPhase noise at 23 GHz operation frequency

Measured phase noise is at least 4 dB lower than all previously published Si-based integrated synthesizers above 12 GHz


Design of subcircuit (Programmable divider)

: R / R+1 P

S

fin fout

Commonly used programmable divider architecture

Divider value N = P*R+S

Not truely moduler

Program counter

Swallow counter


Design of subcircuit (Programmable divider)

1 „A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-m CMOS Technology“, Cicero S.Vaucher et. al., IEEE Journal of Solid-State Circuits, VOL. 35, NO. 7, JULY 2000

Div value 2n to 2n+1-1

Div value 2n‘min to 2n+1-1

11 bit, div value: 3 to 2048input frequency 10 GHz (simulation with parasitic extraction)


Design of subcircuit (PFD/CP)

Four switchable charge pump currents in parallel

Current can be controlled digitally from 250 µA to 3750 µA in steps of 250 µA

Bandwidth and noise can be optimised by varying the charge pump current

Each CP is based on standard topology using current mirror and cascaded current source

PFD is designed using two resettable D-flip-flops, nor gate in the feedback path

cp_2m

vee

vdd

ctrl

outup

down

cp_1m

vee

vdd

ctrl

outup

down

cp_0.5m

vee

vdd

ctrl

outup

down

cp_0.25m

vee

vdd

ctrl

outup

down

PFD Filter


Layout

VCOREF

SPIProg. Div

PFD/CP

Prescaler

Area: 4 x 1.4 mm2

High aspect ratio reduces substrate noise coupling significantly by distance

Vertical guard band between VCO and digital part

Chip layout


Conclusions

Synthesizer architecture for multi-band multi-standard base station application

32 band VCO measurement results

Using varactor in digital manner helps to achieve better phase noise

Multi-Modulus divider architecture

Presently complete synthesizer is in the fabrication process


References

M. Tiebout, et al., “A Fully Integrated 13GHz DS Fractional-N PLL in 0.13 µm CMOS,” in IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 47, 2004, pp. 386-387

1

H. Hashemi, et al., “A 24-GHz SiGe Phased-Array Receiver-LO Phase-Shifting Approach,”IEEE Tran. Micro. Theory Tech., vol. 53, pp. 614-626, Feb. 2005

2

3 O. Mazouffre, et al., “A 23-24 GHz Low Power Frequency Synthesizer in 0.25 µm SiGe,” in Proc. of the 13th European Gallium Arsenide and other Compound Semiconductors Application Symposium, Paris, France, Oct. 2005, pp. 533-536

F. Herzel, S. Glisic, and W. Winkler, “Integrated frequency Synthesizer in SiGe BiCMOSTechnology for 60 and 24 GHz Wireless Applications,” Electronics letters, vol. 43, pp. 154-156, Feb. 2007.

W. Winkler, et al. “A Fully Integrated BiCMOS PLL for 60GHz Wireless Applications,” in IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 48, 2005, pp. 406-407

4

5


THANK YOU !!

Frequency Synthesizer for Multi-Band Multi- Standard Base ......3G LTE WiMAX TDD FDD FDD FDD TDD TDD...

Documents

Transcript of Frequency Synthesizer for Multi-Band Multi- Standard Base ......3G LTE WiMAX TDD FDD FDD FDD TDD TDD...