Frequency Synthesis and Clock Generation for High Speed Systems - VE2013
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Transcript of Frequency Synthesis and Clock Generation for High Speed Systems - VE2013
Analog Design Conference 2013 Frequency Synthesis and Clock Generation Advanced Techniques of Higher Performance Signal Processing David Kress and Mike Curtin
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3
Today’s Agenda
Applications areas for clocks and frequency synthesis
Design and application of phase-locked loops (PLLs)
Design and application of direct digital synthesis (DDS)
Clock generation and distribution
Issues of clocking data converters
4
What is a clock and what are the common frequencies?
Unlike a data waveform, a clock signal is a square wave whose frequency is usually constant.
Common frequencies include: 1 pps (pulse per second) used by GPS 8 kHz (commonly used in wired communcations) and is commonly referred to
as a BITS clock 32.768 kHz is the common watch crystal oscillator 19.44 MHz is a common reference clock in synchronous optical (SONET)
networks, and is still used in OTU (Optical Transport Unit) networks that are replacing SONET
122.88 MHz is commonly used in wireless communications 125 and 156.25 MHz are common Ethernet reference clocks
5
Clock Sources
General oscillators Crystal oscillators Voltage-controlled oscillators (VCO)
Phase Locked Loops (PLLs) Analog PLLs Uses an analog multiplier as the phase detector Not in Wide Use
Digital PLLs Use a digital phase frequency detector (PFD), analog loop filter, voltage controlled oscillator (VCO) Simple architecture Very high performance and low noise
All-Digital PLLs Use a digital phase frequency detector (PFD), digital loop filter, NCO Increased flexibility for faster locking Excellent jitter cleaning Extremely flexible
Direct Digital Synthesis Extremely flexible frequency generation Very fast frequency sweeping and hopping Very popular in military and instrumentation applications
3.6
Basic Phase Locked Loop (PLL) Model
(B) STANDARD NEGATIVE FEEDBACK CONTROL SYSTEM MODEL
(A) PLL MODEL
ERROR DETECTOR LOOP FILTER VCO
FEEDBACK DIVIDER PHASE
DETECTOR CHARGE
PUMP FO = N FREF
7
Digital PLL Block Diagram
3.8
Phase/Frequency Detector (PFD) Driving a Charge Pump (CP)
D1 Q1
CLR1
CLR2D2 Q2
V+
V−
HI
HI
+IN
−IN
DELAY
UP
DOWN
CP OUT
I
I
U1
U2
U3
PFDCP
D1 Q1
CLR1
CLR2D2 Q2
V+
V−
HI
HI
+IN
−IN
DELAY
UP
DOWN
CP OUT
I
I
U1
U2
U3
PFDCP
(A) OUT OF FREQUENCY LOCK AND PHASE LOCK
(B) IN FREQUENCY LOCK, BUT SLIGHTLY OUT OF PHASE LOCK
0
+I
+I
0
(A) OUT OF FREQUENCY LOCK AND PHASE LOCK
(B) IN FREQUENCY LOCK, BUT SLIGHTLY OUT OF PHASE LOCK
0
+I
+I
0
UP
1
0
0
DOWN
0
1
0
CP OUT
+ I
−I
0
UP
1
0
0
DOWN
0
1
0
CP OUT
+ I
−I
0
(C) IN FREQUENCY LOCK AND PHASE LOCK
3.9
Adding an Input Reference Divider and a Prescaler to the Basic PLL
(A)
(B)
All-Digital PLL Detailed Block Diagram (AD9557 Shown)
10
SPI/I2CSERIAL PORT
EEPROM
REF MONITORINGAUTOMATICSWITCHING
÷N1 ÷N2
÷N3
÷2 ÷M0OUT0OUT0
OUT1OUT1
10-BITINTEGERDIVIDERS
MAX 1.25GHz
÷M1
×2
×2
LF
PFD/CP
RF DIVIDER 1÷3 TO ÷11
XO OR XTAL XO FREQUENCIES10MHz TO 180MHz
XTAL: 10MHz TO 50MHz
RF DIVIDER 2÷3 TO ÷11
FOUT = 360kHz TO 1.25GHz
INTEGER DIVIDER
OUTPUT PLL (APLL)
FRAC1/MOD1
17-BITINTEGER
24b/24bRESOLUTION DIGITAL PLL (DPLL)
÷2
REGISTERSPACE
2kH
zTO
1.25
GH
z
R DIVIDER (20-BIT)
SYNC RESET PINCONTROL M0 M1 M2 M3 IRQ
SPI/I2C
DIGITALLOOP
FILTER
TUNINGWORD
CLAMP ANDHISTORY
FREERUNTW
PLL2STATUS
LF CAP
PFD/CP LF3.34GHz
TO4.05GHz
DP
FD
30-BIT
NC
O
ROMANDFSM
MULTI-FUNCTION I/O PINS(CONTROL AND STATUS
READ BACK)
SYSTEMCLOCK
MULTIPLIER
÷2
AD9557
REFAREFA
REFBREFB
0 91 9
7 -13
5
All-Digital PLL Core
Digital PLL
3.11
Integer-N Compared to Fractional-N Synthesizer
REF DIVIDER
R PFD FILTER VCO
N COUNTER
FREF F1
FOUT
10MHz
R =50
0.2MHz
N = 4501
900.2MHz
REF DIVIDER
R PFD FILTER VCO
"N" COUNTER
FREF F1
FOUT
10MHz
R =10
1MHz
900.2MHz
N =900.2
"N" = NINTEGER + NFRACTION NMODULUS = 900 +
NFRACTION
5
FOUT = FREF×(N/R)
(A) INTEGER N
(B) FRACTIONAL N
3.12
Key PLL Specifications
RF Input Frequency (Minimum/Maximum) Phase Noise and Phase Jitter Reference Spurs Frequency Lock Time Output Frequency Error Phase Lock Time Output Phase Error Loop Bandwidth and Phase Margin
13
Common Uses for PLLs
Frequency translation
Jitter Cleanup
Redundant clocking
Holdover
Clock Distribution
/2REFA19.44MHz
/R1
PhaseFreqDet
(PFD)
10 kHz< FPFD < 50MHz
Charge Pump
Loop Filter (External)
VCO
/4 or 5/B
156.25MHz
Feedback Divider (N Divider)
/P/2 /R2
Reference Monitor and control Logic
REFB
REF FLAG
VCOdiv
14
Frequency Translation Example:
19.44 MHz (SONET) to 156.25 MHz (10 Gb/s Ethernet): R divider=162, B=15625, VCO divider = 3, P divider = 4 Phase detector frequency: 120 kHz VCO frequency: 1875 MHz
15
Jitter Clean-up
Clean signal from main clock board
Backplane has lots of noise sources Clock received by line
card is contaminated
Clock received from back plane is used to establish phase and frequency of the output
Signal purity of the output is dependent upon the Local oscillator (Crystal, TCXO, or OCXO) used HOW?
Digital PLL w/ a Programmable Digital loop Filter capable of <1 Hz BW
Switchover and Holdover
Holdover:
Holdover is the ability to provide output signals even when the reference input disappears. Holdover can be initiated either as directed by controller/processor elements in a system, or via a provided monitoring function which will automatically switch into holdover mode when the reference input goes quiet.
Switchover:
Switchover provides additional security beyond the holdover function. If one of the references fails, the clock device will use one of the alternate references instead. An important aspect of all the switchover functions provided in ADI clock devices is that no runt pulses and no extra long pulses result from this change. Downstream PLLs will not lose lock as a result, of or during, switchover - even when no predefined relationship exists between the phases of the various reference input signals. Switchover can be initiated either as directed by controller/processor elements in a system, or via a provided monitoring function which will automatically implement switchover when the active reference input goes quiet.
Switchover, Synchronization, and Holdover
NOTE output is synchronized to primary reference But what happens when the
primary reference disappears?
The PLL will maintain the output clock in holdover until another reference input is available. The output phase may or may not slew (depending on the application) so that either the input-output phase is the maintained or there is no output clock phase slewing.
AD9548
3.18
TOOLS – Design, Simulation, Evaluation
Full Range of Evaluation Boards for DDS, Clock Generation and Distribution, PLLs Available. Full suite of Windows-Compatible Software Available http://www.analog.com/en/evaluation-boards-kits/resources/index.html
http://www.analog.com/en/rf-tools/topic.html
http://ez.analog.com/welcome
3.20
PLL Design and Simulation Software
VERSION 3.5
www.analog.com/adisimpll
Forums in
22
Get fast answers to new questions
Search existing content for immediate answers
http://ez.analog.com/community/dds http://ez.analog.com/community/clock_and_timing http://ez.analog.com/community/rf
Clocking Applications for Phase-locked Loops (PLLs)
24
Clocking Application – Wireless Transceiver Card
ADC
TRX Clock Distribution IC
ADC
ADC
ADC
DDC or ASIC
DAC
DUC or FPGA
DAC
User’s Reference
Clock
Clock to A-D Converters
Clock to D-A Converters
Clock to Digital Chips
Critical Clock Functions on Transceiver Card: • clean-up jitter on user’s input reference • up-convert user reference frequency to highest frequency needed, usually driven by DAC clock requirements • generate multiple frequencies for RX & TX • provide low jitter clocks for converters • generate mix of LVPECL, LVDS, CMOS clocks • adjust phase or delay between clock channels • offer isolation between clock channels
TRX Cards
25
Digital Cross Point
Clock Generation/ Distribution
Power Sequencing
Line Card
Switch Card
XCVR CDR
SERDES
Backplane Switch & EQ
Digital Engine
Optical Transceiver
TIA
LDD
PIN
Laser
Limiting AMP
Signal Conditioner
Clocking Application – Line Card
Switch Card
Line Card
Backplane
New ADI clock products such as the AD9557 and AD9548 are tailored for network applications. Specific AD9548 example on next page
SyncE / IEEE1588 Hybrid (with Hooks for Pure IEEE1588)
Backplane
Line Card
AD9557 AD9547
TCXO / OCXO Recovered clocks
from Line cards
BITS GPS
Timing Card
XO AD9553/7 (Optional)
Tx
Rx
CPU / FPGA / DSP IEEE1588
Protocol / Algorithm
SPI / I 2C
MAC/PHY
SyncE Clock Recovering +
IEEE1588 Time Stamp
Time Stamps
Frequency Synchronization
1 PPS
Timing Card 2 Line Card n
Time of Day Offset Adjustment
1 PPS
Time of Day
Clock/Frequency Control
AD9548
Using DDS For Clock Generation
28
Generating Clocks using DDS
LimiterReconstruction
Filter
Fsysclock(fc) DAC out Filter out
Clock out
Ideal TimeDomain
Response
IdealFrequency
DomainResponse
"Real World"FrequencyResponse
t
0
1 1 3 5 7Odd harmonic series
1 3 5 7
t t
f ff
ffffc
fc 2fc
2fc
DDS
The DDS chip can synchronize to a user’s reference. An on-chip clock multiplier can generate the fast clock needed to clock the NCO/DAC. A frequency tuning word may be written to set the output clock rate. External filtering removes unwanted images. A squaring function then converts sine wave to square wave.
3.29
A Flexible DDS System
f c
SE RI AL OR BYTE
LO AD REGISTER
n n
FREQUENCY CONTROL
PH A SE REGISTER
LPF
D A C
PA R A L L EL DE L TA PH A SE
REGISTER M CLOCK
n n
PHASE ACCUMULATOR
n
PH AS E TR UN CA TI ON 12-19 BITS
AMP LIT UDE TR UN CA TI ON
2 n = f o
M • f c
N-BITS
n = 24 - 48 BITS
PHASE-TO AMPLITUDE CONVERTER
M = TUNING WORD
SYSTEM CLOCK
(10-14)
6-bit phase wheel 0
1 2 3 4
63
0 2 4
31 29 …
…
5-bit amplitude resolution
f o
vector data raw DDS-DAC output filtered output compared output
3.30
Signal Flow Through the DDS Architecture
REFERENCECLOCK
PHASEACCUMULATOR
(n-BITS)
PHASE-TO-AMPLITUDECONVERTER DAC
M
TUNING WORD SPECIFIESOUTPUT FREQUENCY AS AFRACTION OF REFERENCECLOCK FREQUENCY
IN DIGITAL DOMAIN ANALOG
NDDS CIRCUITRY (NCO)
TOFILTER
2n=foM • fc2n=fo
M • fc
fc
M = JUMP SIZE
3.31
AD9858 1GSPS DDS with Phase Detector and Multiplier
3.32
DDS Single Loop Upconversion Using the AD9858
DDS 1GHz DAC
10 32 LPF DIVIDER
1/2/4
PHASE/ FREQUENCY DETECTOR
150MHz
CHARGE PUMP 0.5mA-2mA
0.5mA STEPS
LOOP FILTER ~
DIVIDER K
DC - 400MHz
VCO
f = K× fREF
DDS/DAC CLOCK
FREQUENCY TUNING WORD
PART OF AD9858:
fREF DC - 150MHz
DDS vs. PLL
Comparing: Advantage The rest of the story Freq. Resolution DDS Fractional N PLLs shrink the gap, Programmable Modulus
improves DDS precision
Freq. Agility DDS Fast hopping PLLs shrink the gap
Phase Resolution & Agility
DDS Digital PLLs can provide some level of phase control.
Amplitude Resolution & Agility
DDS
Power Consumption PLL Gap shrinks with geometry; interleaved cores
Output Frequency Range
PLL
Price PLL* Gap shrinks with geometry; in no small part this is due to the breadth of adoption of PLL technology,
Broad Spectral Purity PLL Ancillary circuitry PLL Freq. Up-conversion PLL Super Nyquist operation and hybrids
33
Hybrid configurations
DDS RefCLK PLL Upconverting PLL
DDS RefCLK PLL RefCLK multipying PLL
PLL DDS
RefCLK DDS in feedback path
PLL
DDS RefCLK DDS as a DCO
34
Clocking Data Converters
36
Clocking Data Converters
Absolute accuracy needed for reproduction CD sound output would be off-tune
Clock jitter leads to distortion
Effective Aperture Delay Time Measured with Respect to ADC Input
SAM PL ING CL OC K
ANALOG INPUT SI NE WA VE
ZERO CROSSING
+FS
-FS
0 V
+ t e – t e
t e
' '
'
38
Jitter – common noise source introduced at SHA in A-D Converter
Clock jitter is the sample to sample variation in the encode clock (both the external jitter as well as the internal jitter).
Fullscale SNR is jitter-limited by:
See AN-501 and AN-756
SHA = Sample & Hold Amplifier
=
=
jitterrms
rmsjitter ftN
SSNRπ2
1log20log20
39
45.0
50.0
55.0
60.0
65.0
70.0
75.0
80.0
85.0
90.0
100 1000
50 fs
100 fs
200 fs
400 fs
800 fs
Fullscale Analog Input (sinewave)
84dB
78dB
AIN = 200 MHz
Each line shows constant RMS clock jitter in femtoseconds (fs)
72dB
66dB
60dB
300MHz
400MHz
500MHz
SNR of ADC @ 200 MHz AIN varies with clock jitter
Sig
nal t
o N
oise
Rat
io (S
NR
) in
dB
ADC Analog Input
Sampling Clock
SNR
Digital Output
As analog signal increases, clock jitter limits SNR
=
jitterjit ft
SNRπ2
1log20
40
Clocking AD9434 A/D Converter (12 Bits at 500MSPS)
41
Clocking AD9434 A/D Converter (12 Bits at 500MSPS)
42
Clocking AD9434 A/D Converter (12 Bits at 500MSPS)
2.43
Additive RMS Jitter of Logic Gates/Drivers
FPGA (driver gates only) 33-50 ps**
74LS00 4.94 ps *
74HCT00 2.20 ps *
74ACT00 0.99 ps *
MC100EL16 PECL 0.7 ps **
AD951x family 0.22 ps **
NBSG16, Reduced Swing ECL (0.4V) 0.2 ps **
ADCLK9xx, ECL Clock Driver Family <0.1 ps**
* Calculated values based on degradation in ADC SNR
** Manufacturers' specification
By Architecture & Performance N
on-P
LL
PLL
Ext
VC
O
PLL
Int V
CO
Wideband RMS jitter
ADCLK944
ADCLK905 ADCLK907 ADCLK925
ADCLK946 ADCLK948 ADCLK950 ADCLK954
ADCLK914
ADCLK846 ADCLK854
AD9512 AD9514 AD9515
AD9513
AD9508
AD9510 AD9511
AD9516-5
AD9520-5
AD9522-5
AD9516-0:4 AD9517-0:4 AD9518-0:4
AD9520-0:4 AD9522-0:4
AD9523 AD9524
AD9525
50 fs 150 fs 100 fs 200 fs 250 fs 300 fs
Additive Jitter
Absolute Jitter
AD9523-1
6 8 10 12
6
6 8 10
12 12
8
14
14
12
12 10
5
5
6 12 4
9
3 3 2
2 2
1 1
8
Indicates # of outputs
Front end loop of AD9523/4 Uses external Oscillator
Absolute jitter includes oscillator performance and reference quality
Additive jitter excludes oscillator performance and reference quality
ADF4351
ADF4360
ADF4002, ADF4106 Stand-Alone PLL
+ Ext VCXO
1 ps
45
Voltage-controlled Oscillators
Provide simplicity and versatility
Simple RC-adjustable oscillators for undemanding applications
Higher frequencies require specialized design
46
Voltage-controlled Oscillators ADF5508
3.47
LOOP FILTER
VCXO
System Clock Distribution Examples
ADC FIFO
122.88 MHz 122.88 MHz
LVPECL CMOS
DELAY = 4.3ns
HIGH SPEED MEASUREMENT SUBSYSTEM
REFCLK
491.52 MHz LVPECL
30.72 MHz
DAC
DAC FPGA LVDS
CMOS
CMOS
QUADRATURE TRANSMIT SOURCE
61.44 MHz
61.44 MHz
PHASE = 90°
DELAY = 10ns 122.88 MHz
LVPECL 491.52 MHz
CLEAN_REFCLK 30.72 MHz
CALIBRATION 15.36 MHz
Clock ICs simplify board design by integrating phase control, delay adjust, frequency dividers, and logic translation
PHASE = 0°
TOYOCOM 491.52 MHz
AD9513/AD9514/AD9515 easy to design in. Require only a +3.3V supply. All functionality selected by tying input pins to VS, GND, VREF, or NC
48
AD9516 Family 1.5 -3.0 GHz, 8/5-Channel Clock Distribution ICs
Clock Outputs 1.2 GHz LVPECL 800 MHz LVDS 250 MHz CMOS
PLL Core 250 MHz REFIN 1.6 GHz PLL Jitter Clean-up
Programmable Dividers Any integer 1 to 32 Phase offset control Each divider independent
Programmable Delay Adjust Fullscale from 1ns to 10ns 32 delay steps
64-LFCSP typically replaces
Five(5) discrete ICs
AD9510 Shown Below, Broadband RMS Jitter <1ps
3.49
AD9512 1.2GHz Clock Distribution IC
Delay 1-10ns
1:5 Fanout Buffer
Divide by 1-32 LVDS OR
CMOS
LVDS OR CMOS
225 fs rms
225 fs rms
350 fs rms
1-3 ps rms
A
rms jitter added to signal at A
225 fs rms
Divide by 1-32
Divide by 1-32
Divide by 1-32
Divide by 1-32 LVPECL Buffer
LVPECL Buffer
LVPECL Buffer
TOTAL JITTER = J12 + J2
2 + J32 +...+JN
2
50
ADI’s Complete Clock Portfolio
Digital and All-Digital PLLs Used for frequency multiplication/translation Redundant Clocking and Holdover
Synthesizers Used for clock generation
Clock Distribution Used for sending the identical clock to multiple chips Also used for logic level translation (i.e., LVPECL to LVDS) May include frequency dividers (/2, /4, etc.) May include skew adjustment
Voltage-controlled oscillators
51
What we covered
As system complexity and performance demands increase, frequency synthesis devices have had to keep pace with greater performance and versatility
Design and application of phase-locked loops (PLLs)
Design and application of direct digital synthesis (DDS)
Software tools greatly simplify design and set-up of complex frequency synthesis devices
Clocks for data converters need to have low jitter to keep distortion at a minimum
Specialized clock generation and distribution allows precise frequency tuning and phase control
Visit the DDS, PLL and CLK simulators in the demonstration room
ADIsimCLK, ADIsimPLL and ADIsimDDS can quickly configure the complex registers and settings on frequency synthesis devices to provide optimum performance
Image of demo/board
52
VERSION 3.5
Design Conference Schedule
53
Advanced Techniques of Higher Performance Signal Processing
Industry Reference Designs & Systems Applications
8:00 – 9:00 Registration
9:00-10:15 System Partitioning & Design
Signal Chain Designer: A new way to design online
High Speed Data Connectivity: More than Hardware
Process Control System
10:15-10:45 Break and Exhibit
10:45-12:00 Data Conversion: Hard Problems Made Easy
Amplify, Level Shift & Drive Precision Systems
Rapid Prototyping with Xilinx Solutions
Instrumentation: Liquid & Gas Sensing
12:00-1:30 Lunch and Exhibit
1:30-2:45 Frequency Synthesis and Clock Generation for High-Speed Systems
Sensors for Low level Signal Acquisition
Modeling with MATLAB® and Simulink®
Instrumentation: Test & Measurement Methods and Solutions
2:45-3:15 Break and Exhibit
3:15-4:30 High Speed & RF Design Considerations
Data & Power Isolation
Integrated Software Defined Radio
Motor Control
4:30-5:00 Exhibit and iPad drawing