Freescale presentation template

Freescale Semiconductor Confidential Proprietary. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor , Inc.

All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004 Freescale Semiconductor Confidential Proprietary. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor , Inc.

All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004

The S12XE…

Jooyang Park

Freescale Korea AutoLab

April 2012

16 Bit Automotive Microcontrollers



S12 Automotive Evolution

These represent Freescale Semiconductor's current proposed product development plans, and are subject to change

Ap

pli

ca

tio

n P

erf

orm

an

ce

/ In

teg

rati

on

S12Q

32K

Lowest Cost

8-16MHz

48,52,80pin

ROM Available

64K

96K

128K

S12C

32K

Low Cost

16-25MHz

48,52,80pin

ROM Available

64K

96K

128K

32K

64K

128K S12P Ultra Low Cost

LIN/CAN

32Mhz

48,64,80 pin

64K

128K

256K S12XS Reduced peripherals from S12XE

40MHz no XGATE, no MPU

64, 80, 112pin

64K

128K

256K S12XD

40MHz

XGATE

80,112,144 pin

512K

S12XB Reduced peripherals

from S12XD 80,112pin

64K

128K

S12HZ Stepper Motor,

LCD Support

25MHz

80,112 pin

(ROM 32K-256K

512K

256K

S12XH Stepper Motor,

LCD Support

40MHz XGATE

112,144 pin

512K

384K

256K

128K

S12XF FlexRay, XGATE, MPU,

ECC

50MHz

64,112pin

1M

768K

512K

384K

S12XE

XGATE, MPU, EEEPROM

50MHz

80,112,144,208pin

256K

128K

S12ZG

512K

384K

S12G Cost Reduced 16-bit MCU

16-240K Flash

Onboard EEPROM

25MHz

20 TSSOP - 100LQFP

256K

128K

384K

256K

S12XE Next Gen

Cost Reduction

Linear CPU

XGATE, MPU, EEPROM

60MHz

64,80,112 pin

S12(X)HY

32K

Stepper Motor, LCD Drive

32MHz

64,100 pin

64K

48K

192K

2008 2009 2010 2011

128K

96K

64K

16K

32K

48K

240K

Relay-driven Window Lift

LIN Slave Device

System in Package Solutions Single Die

With embedded VREG,

LIN or CAN Phy, 12V I/Os

Application Specific

Drivers

32-64pin QFP, QFN?

128K

256K

Available

Planned

Proposed

In Design

96K

2012

DC/ BLDC Motor


All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004 3

S12XE Family

This document contains forward-looking statements based on current expectations, forecast and assumptions of Freescale that involves risk and uncertainties. Forward looking statements are subject to risk and uncertainties associated with Freescale business that could cause actual results to vary materially from those stated or implied by such forward-looking statements.

Device Flash ROM RAM EE XGATE MPU EBI CAN

SCI

(LIN) SPI IIC ECT TIM PIT PWM ATD

Max

Speed

(MHz) Package

9S12XEP100 1Mb 64 4 1 1 y 5 8 3 2 16b8ch 16b8ch 8ch 8b8c 32 50 112 LQFP 144QFP 208MBGA

9S12XEP768 768 48 4 1 1 y 5 8 3 2 16b8ch 16b8ch 8ch 8b8c 32 50 112 LQFP 144QFP 208MBGA

9S12XEQ512 512 32 4 1 1 y 4 6 3 2 16b8ch - 8ch 8b8c 24 50 80 QFP 112 LQFP 144QFP

9S12XEQ384 384 24 4 1 1 y 4 4 3 1 16b8ch - 4ch 8b8c 24 50 80QFP 112LQFP 144LQFP

9S12XET256 256 16 4 1 1 y 3 4 3 1 16b8ch - 4ch 8b8c 24 50 80QFP 112LQFP 144LQFP

9S12XEG128 128 12 2 1 1 y 2 2 2 1 16b8ch - 2ch 8b8c 16 50 80QFP 112LQFP

8 LIN/SCI

3 SPI

2 IIC

GPIO

FMPLL

5 MSCAN

ATD 12b 32ch

Timer 16b 8ch

ECT 16b 8ch

8ch Periodic

Interrupt Timer

PWM 8b 8ch

80/112/144QFP

208 MBGA

4KB EEPROM

MPU CRG

DBG INT

1MB Flash

64KB RAM

S12XCPU

External Bus Interface

Introducing the S12XE Family:

S12X CISC core @ 50MHz

XGATE RISC core @ 100MHz

Enables higher system integrity at the ECU

level (MPU, ECC, Supervisor Mode)

Improved EMI/EMC

Better resolution/faster ATD

Additional Periodic Interrupt Timer PIT

Enhanced XGATE now with interruptability



4

XGATE Concept

CPU Running

application code

CPU Running

application code

S12

S12X

Interrupt

request

CPU Stalls

Application code

to service IRQ

Interrupt

complete

CPU Running

application code

XGATE

stopped

CPU Running

application code

XGATE completely

handles the IRQ

CPU Running

application code

XGATE

stopped



What is XGATE?

XGATE is a co-processor

• 16bit RISC engine

• Instruction set optimised for data manipulation

• Runs at up to 2x CPU bus speed

• Executes interrupt code only

• Can directly access all peripheral registers.

• Can directly access some of the RAM, some of the Flash

• XGATE is Interrupt driven



XGATE application

Virtual Peripheral

DMA(Direct Memory Access)

Interrupt Handler

Gateway

Simple algorithm implementation

Safety

…. Add your idea!!!



DEMO9S12XEP100 Board including USB-BDM

Power LED

Power

Cable

J502:

Power

Switch

P&E BDM Port S12XEP100

112Pin

SoftTec

USB BDM

IF



DEMO9S12XEP100 Board Peripherals

Power LED

Port A

LEDs

PA[3..0]

Port B

Switches Port P

Buttons

Photocell

ADC 01

CAN0 SCI0

ADC 00

Variable R

Sensor input (ADC)

for line detect

Sensor output (IO)

for light radiation

Communication

(SCI,IIC,CAN)

for monitoring

Driving

(PWM/Timer)

for car

speed

Steering

(PWM/Timer)

for car

direction



Slide 9

CCR

PC

SP

IY

IX

AccD

AccA AccB

CCR (N,V,C,Z)

PC

R7

R6

R5

R4

R3

R2

R1 = Variable Base

R0=0

Flash

CPU EEPROM

RAM

XGATE

Peripherals t

p

0 1 2 3

p

S12XEP100 Architecture for sharing memory



Local Map Paging Scheme

$0000

$1000

$4000

$8000

$C000

64k Local Space

16k unpaged

P-Flash

16k paged

P-Flash

16k unpaged

P-Flash

8k unpaged

RAM

4k paged RAM

1k unpaged EEE 1k paged EEE

2k Registers

$B000

$0800

$FFFF

4k RPAGE 4k RPAGE

16k PPAGE

8MByte Global Space

$000000

$100000

$140000

$7FFFFF

$3FFFFF

1k EPAGE

16k PPAGE

~3MB

Reserved for P-Flash

1MB P-Flash

~1M

Reserved for RAM

64k RAM

252k Reserved for

EEE system

& D-Flash

4k EEE

2k Registers

Extern ~3MB



XGATE Memory Map

Flash

Block 3

RAM

$8000

$FFFF

XGATE

Region

Shared

Data Region

$0000 2K Register

$07FF $00_07FF

$0F_8000

$0F_FFFF

$0800

$78_0800

$78_7FFF

64K total XGATE Address Space 8MByte Global Address Space

4MByte Flash

Accessible via

PPAGE

Fixed pages $7F_FFFF

$00_0000

$10_0000

~1M

RAM rsv’d

8k RAM 24k RAM

252k

EEPROM rsv’d

1k EEPROM 3k EEPROM

2k Register

$14_0000

$00_0800

Depending on

Pin out

Extern ~3MB $40_0000

$7F_4000



BUS CLOCK

OSC CLOCK

CRG

CORE CLOCK = 2 x BUSCLK

S12XE Clock Connections



Interrupt Controller Overview

Each interrupt source has a dedicated control register • Indicates priority level

• Directs interrupt to either CPU or XGATE

• Out of reset configures all interrupts to level 1 and directs them to the

CPU

Provides movable vector table • Allows vectors to be placed in any 256 byte page

Provides 7 interrupt Levels + 1 for disabled



Interrupt Controller Example

X

X X

0

X X

3

0 X

0

X X

0

X X

0

X X

X

X X

0 3 7 3 2 1 0

Resume 3

7 interrupts 3

2 higher than pending 1

RTI

0

2 3 4

1

5 6 7

Pro

ce

ss

ing

Le

ve

l

RTI RTI

* IPL[2:0] is stored on the stack with the new high byte of the CCR

IPL*



Event allocation P

eri

ph

era

l

Mo

du

les

Service

Requests Interrupt

Requests Inte

rru

pt

Pri

ori

ty D

eco

der

XGATE

Module

XG

AT

E R

eq

uest

Pri

ori

ty D

eco

der

CPU

Interrupt

ILVL2 ILVL1 ILVL0

RQST = 0

RQST = 1

RQST

SIF (n)



Standardized interface between peripheral modules and I/O pads for all ports except A,B,E,K. Port control function within standard peripheral modules has been removed

Standard Port features:

User Defined "electrical"

characteristics on a pin by pin basis:

– reduced drive

– wired-or mode

– pull-ups /downs* (* Here certain precautions are taken such as if the CAN is

enabled pull-up is allowed but pull-down is blocked)

-> High Flexibility

• Port Registers Relocatable on Mem

Map -> High Flexibility

PIM

Tim

er

Po

rtT

PT0

PT1 PT2 PT3 PT4

PT5 PT6 PT7

IOC0

IOC1 IOC2 IOC3 IOC4

IOC5 IOC6 IOC7

PW

M

Po

rtP

PP0

PP1 PP2 PP3 PP4

PP5 PP6 PP7

PW0

PW1 PW2 PW3 PW4

PW5 PW6 PW7

SCI0

Po

rtS

PS0

PS1 PS2 PS3 PS4

PS5 PS6 PS7

RxD

TxD RxD TxD

SDI/MISO

SDO/MOSI SCK

SS

SCI1

SPI

Inte

rrup

t

Lo

gic

Po

rtH

PH0 PH1 PH2

PH3 PH4 PH5

PH6 PH7

Inter.L.

Po

rtJ

PJ0 PJ1 PJ6

PJ7 IIC

CAN4

SDA

SDL RxCAN

TxCAN

Po

rtM

PM0 PM1 PM2

PM3 PM4 PM5

PM6 PM7

RxCAN

TxCAN RxCAN TxCAN RxCAN

TxCAN RxCAN TxCAN

CAN3

CAN2

BDLC

CAN0

CAN1

RxB TxB

Port Integration Module PIM



Sensor output (IO) for light radiation

7............………..............................................0

7..........……………..................................................0

DDRB - Port B Data Direction Register

PORTB - Port B Data Register

7.......………………....................................................0

7..…………………........................................................0

RST: U…….…………………………………………………..….U

Read/write

PORTA - Port A Data Register

DDRA - Port A Data Direction Register

Address Offset $0002

$0000

RST: 0..................………..........................................0

RST: U…….…………………………………………………..….U

Read/write

Read/write Read/write

DDRx 1 = PIN IS OUTPUT 0 = PINIS INPUT


$0001

// Port A0 output HIGH

DDRA = 0x01;

PORTA = 0x01;

// Port B0,1,2,3

// output HIGH

// Port B4,5,6

// output LOW

// Port B7 input

DDRB = 0x7F;

PORTB = 0x0F;



Sensor input (ADC) for line detect

Noise filtering

White ground Black ground

ADC0

ADC1

8ch.

8ch.

Total

16 ch.



• 8 /10/12 bit resolution

• Conv. time: 3 µs per ch (10Bit)

• continuous / single scan

(SCAN = 1 or 0)

• single ch./ multich. (MULT)

• External Trigger Control

• 16ch in ADC

• Auto comparioson

MC9S12XE 8/10/12bit A/D converter



SCAN=0 , S8C~S1C 0000, Initial Ch0, MULT = 1



SCAN=0 , S8C~S1C 0000, Initial Ch0, MULT = 0

AN0

AN0

AN0

AN0

AN0

AN0

AN0

AN1

AN1

AN1

AN1

AN1

AN1

AN1

AN2

AN2

AN2

AN2

AN2

AN2

AN2

AN3

AN3

AN3

AN3

AN3

AN3

AN3

AN5

AN6

AN7

S8C… 0100, MULT = 1

S8C… 0100, MULT = 0

AN5

AN5

AN5

S8C… 0001, MULT = 0/1



Driving and Steering with Timer or PWM

Timer output compare

• Periodic timer/counter

• PWM generation

Timer input capture

• Motor speed or position detection – Encoder

• Pulse count or Pulse period calculation

Mot

or

turning

Encoder

MCU

Timer




MC33887 - 5A

• Easy H-bridge motor control

M

High

High

Forward High

Reverse

Low

GPIO

PWM




PWM duty/period control

• Driving for speed – H-bridge circuit

• Steering for direction – Servo motor

Duty : 0.7ms 2.3ms

Period : 10ms



Output Compare Function

Compare/Capture Unit 16-Bit Free-Running Counter

16-Bit Compare

16-Bit Output Compare Register (programmed by software)

Pin Control Logic

Interrupt Request to CPU

OCxF Status Flag is set

upon compare match

OCxI

Optional Local Interrupt Mask (Enabled through software)

• UP TO 8 separate Output Compare Functions • Each Output Compare Function has its own Vector and Controls

• Provides a mechanism to output a signal at a specific time

Set Pin Clear Pin Toggle Pin Inhibit Pin

Action taken upon match of compare register with counter

TCNT

TOCx

Pin OCx



IC/OC Select

IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0

TIOS - TIMER INPUT CAPTURE/OUTPUT COMPARE SELECT REGISTER

IOSx = 1 SELECT OC FUNCTION = 0 SELECT IC FUNCTION

RST: 0 0 0 0 0 0 0 0

$0000 B6 B5 B4 B3 B7 B2 B1 B0

TIMER ENABLE 1 - CLOCKS COUNTER ENABLE 0 - CLOCKS COUNTER DISABLE

TSCR1 - TIMER SYSTEM CONTROL REGISTER 1

RST: 0……………………………………………………………………………0

$0006 TEN TSWAI TSFRZ TFFCA Reserved

TSWAI - TIMER STOP IN WAIT 0 = NORMAL OPERATION 1 = DISABLE TIMER IN WAIT MODE

TSBCK - TIMER STOP IN DEBUG MODE 0 = DO NOT STOP 1 = DISABLE TIMER IN DEBUG MODE

TFFCA - TIMER FAST FLAG CLEAR ENABLE 0 = TIMER FLAG CLEARING NORMALLY 1 = A READ FOR IC, A WRITE OF OC REGISTER CAUSES CORRESPONDING CHANNEL FLAG TO CLEAR



Timer, Prescaler and Counter

1. TCNT

2. TFLG2

Timer Overflow Flag Write a ‘1’ to clear

16 BIT FREE RUNNING /MODULO COUNTER

PRESCALER SELECTION

1 - TIMER OVERFLOW INTERRUPT ENABLE 0 - TIMER OVERFLOW INTERRUPT DISABLE

TOF 0 0 0 0 0 0 0

B7......................................................................B0

B15............................................................................................................................…B0

DIVIDE BY

1 2 4 8 16 32 64 128

REGISTERS:

0 0 0 0 1 1 1 1

0 1 0 1 0 1 0 1

0 0 1 1 0 0 1 1

PR2 PR1 PR0

* RESERVED

RST: 0 0 0 0 0 0 0 0

RST: 0........................................................................................................................0

$000F

$000D

Address Offset $0004, $0005

3. TSCR2

RST: 0 0 0 0 0 0 0 0

1 - TIMER RESET BY OC7 MATCH 0 - COUNTER IS FREE RUNING

TCRE - ALLOWS FOR PULSE WIDTH MODULATION FUNCTION.

B7....................................................................................B0

TOI 0 0 0 TCRE PR2 PR1 PR0



Output Compare

1. TC7 – TC0

COMPARE/CAPTURE FLAGS Write ‘1’ to Clear Interrupt Flag Ex) TFLG1 = 0x02; //C1F clear DO NOT USE BIT MANIPULATION INSTRUCTIONS (SINCE RM/W OPERATION)

COMPARE/ CAPTURE MASK 0 = Interrupt Request Masked 1 = Interrupt Request Enabled

OMX OLX Action on OCx

0 0 1 1

0 1 0 1

No Action OCx Toggle OCx Drive OCx LO Drive OCx HI

OUTPUT MODE AND OUTPUT LEVEL (O7–OC0)

REGISTERS:

OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 4. TCTL1

B6 B5 B4 B3 B7 B2 B1 B0

RST: 0 0 0 0 0 0 0 0

$0008

C7F C6F C5F C4F C3F C2F C1F C0F 2. TFLG1

B6 B5 B4 B3 B7 B2 B1 B0

RST: 0 0 0 0 0 0 0 0

$000E

C7I C6I C5I C4I C3I C2I C1I C0I 3. TIE

RST: 0 0 0 0 0 0 0 0

$000C B6 B5 B4 B3 B7 B2 B1 B0

OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 5. TCTL2

RST: 0 0 0 0 0 0 0 0

$0009 B6 B5 B4 B3 B7 B2 B1 B0

Address Offset $0010 - $0011 - - $001E - $001F

16 BIT CAPTURE COMPARE REGISTER (TC7)

16 BIT CAPTURE COMPARE REGISTER (TC0)

- -



Input Capture Function

Compare/Capture Unit 16-bit Free Running Counter

16-bit Input Capture Latch

Status Flag is set upon capture

Interrupt Request to CPU

Edge Edge Select & Detect

Pin ICx

ICxF

ICxI

• Up to 8 separate Input Capture function, IC7 - IC0 • Each Input Capture Function has its own Vector and Controls

Rising Edges Falling Edges Any Edge Inhibit

Optional Local Interrupt Mask (Enabled through software)

• Provides a mechanism to capture the time at which an external event occurs TCNT

TICx

Delay Counte

r

0 0 0 0 0 0 DLY1 DLY0

Bit 7 6 5 4 3 2 1 0

DLYCT - Delay Counter Control Register

DLY[1:0] - Delay Counter Values 00 = Disabled 01 = 256 M Clocks 10 = 512 M Clocks 11 = 1024 M Clocks


Note: Delay Counter produces a Pulse at preset clock count if the level of the input signal is the opposite of the level before the transition.

16-bit Holding Register



Input Capture Application

Period Calculation

#1 # 2

1. Input capture

Rising edge detection

(#2 time - #1 time) / TCNT speed

Fixed time

2. Event count during fixed time

Falling edge count

Fixed time / count

Duty Calculation

#1 # 3

1. Input capture

Any edge detection

(#2 time - #1 time) / TCNT speed

2. Gated time accumulation

Rising edge detection

High pulse status check periodically

Counted number x period

# 2



Pin Logic Delay

Counter

COMPARATOR

CAP./COM. Register Pulse Accumulator

16-Bit Free-running Main Timer

Hold Register Hold Register

Prescaler Mclock

CH1

16-Bit Modulo Down-Counter Prescaler

0

• 16-bit main timer with 7-bit Prescaler • 8 IC/OC channels, 4 IC channels buffered • 16-Bit modulus Down-Counter with 4-bit prescaler for:

•periodic interrupt time base •control IC/PA register latch

• 4 8-Bit or 2 16-bit pulse accumulators with 4 8-bit buffer registers • independent Interrupt sources: 8 IC/OC, Timer OF, 4 PA, MC

• 4 inputs with selectable Delay Counters to filter out spurious signals

ContrlBits

Reset

load Register

Mclock

MC9S12 Enhanced Capture Timer



Pulse Accumulator

USEFUL FOR: 1. EVENT COUNTING

2. GATED TIME ACCUMULATION

DESCRIPTION: IF PULSE ACCUMULATION IS Enabled, THEN STAR12

RESPONDS TO EDGES ON PAI BY INCREMENTING THE

8 OR 16-BIT PULSE Accumulator COUNTER.

EVENT COUNTING MODE:

INPUT EDGES ON PAI INCREMENT THE 8/16-BIT COUNTER

GATED TIME ACCUMULATION MODE:

THE 8/16-BIT COUNTER IS INCREMENTED BY AN E/64

CLOCK IF Enabled BY THE LAST EDGE ON PAI

IF THE SPECIFIED EDGE OCCURS, THEN:

1. THE PULSE Accumulator FLAG BIT IS SET

IN ADDITION, THE FOLLOWING MAY OCCUR: 1. THE COUNTER MAY BE INCREMENTED

2. THE PULSE Accumulator OVERFLOW BIT MAY SET

3. AN INTERRUPT IS GENERATED TO CPU, IF Enabled.



ECT Block and Application Example

SENSOR 1

SENSOR 2

SENSOR 3

SENSOR 4

SIGNAL CONDITIONING LOGIC




LF WHEEL RF WHEEL LR WHEEL RR WHEEL



SPARK PLUG SPARK PLUG FUEL INJECTOR FUEL INJECTOR





PWM Module

- 8 INDEPENDENT PWM CHANNELS WITH PROGRAMMABLE PERIOD AND

DUTYCYCLE.

- 8-BIT 8-CHANNELS OR 16-BIT 4-CHANNELS.

- DEDICATED COUNTER FOR EACH CHANNEL.

- FLEXIBLE CLOCK GENERATION ( A, B, SA AND SB )

THAT COVERS WIDE RANGE OF FREQUENCIES.

- PERIOD AND DUTY CYCLE ARE DOUBLE BUFFERED.

- ALLOWS FOR IMMEDIATE PWM UPDATE.

- POLARITY IS SOFTWARE SELECTABLE.

- PROGRAMMABLE CENTER OR LEFT-ALIGNED PWM OUTPUT.

- EMERGENCY SHUT DOWN



PWM Clock Select

1. Clock A (Ch 0, Ch 1, Ch 4, Ch 5)

2. Clock SA (scaled A; Ch 0, Ch 1, Ch 4, Ch 5)

3. Clock B (Ch 2, Ch 3, Ch 6, Ch 7)

4. Clock SB (scaled B; Ch 2, Ch 3, Ch 6, Ch 7)

Four clock sources:

Bus Clock

Divide by Prescaler Taps:

2 4 8 16 32 64 128

PRESCALE

PWMPRCLK @ $_03 Clock SA

Clock SB

Clock A

Further Division of the clock:

2 4 6 8 ... 512

Clock B

Further Division of the clock:

2 4 6 8 ... 512

PWMSCLA @ $_08

PWMSCLB @ $_09

SCALE



16-Bit Resolution

Two 8-bit channels of the PWM module can be concatenated to a 16-Bit PWM channel

Period/Duty Compare

PWMCNT6 PWMCNT7

PWM7

Clock Source 7

CONxx PWMEx PPOLx PCLKx CAEx PWMx OUTPUT

CON67 PWME7 PPOL7 PCLK7 CAE7 PWM7






PWM Initialization Steps

1. Disable PWM

PWME

2. Select clock (prescaler and scale) for the PWM

PWMPRCLK, PWMSCLA, PWMSCLB, PWMCLK

3. Select polarity

PWMPOL

4. Select center or left aligned mode

PWMCAE

5. Program duty cycle and period

PWMDTYx, PWMPERx

6. Enable used PWM channels

PWME



New &

Improved

Making it simpler, less expensive, and easier to use!

Host System

Target

System

BDM Pod / P&E Cable

Revolutionary MC9S12X Development Tools

BKGD

unused unused

GND

Vdd

RESET

You should disconnect the BDM from Target after target power off!!

Softec in S12XE board



• Low cost serial real-time emulation and debug

• Single step, Run, or Trace the application code

• On-chip hardware for multiple breakpoints

• Replaces expensive emulator or bus analyzer

• Works at full operating voltage and frequency

range

• Non-intrusive - no cumbersome emulator cables

• Fast in-circuit FLASH programming

BDM on MC9S12X:

Revolutionary Development Tools



CodeWarrior Development Studio for Freescale HCS12(X) Microcontrollers



Project Creation

Processor

Expert for

auto code

generation

Select XGATE

NO

Processor

Expert usage



Project Creation (cont.)

Compile

Compile &

Debugging

SofTec for board



Programming 1 – Bean Selection

BitIO

double click

TimerInt

Generation



Programming 2 – Bean Inspector Input

PB0 select

Enter “500ms”

Click!



Programming 3 – Code generation

Code generation

and Compile

1

2 Macro function

“NegVal” enable

Events.c Generation

3 4



Programming 4 – Code Input

Drag & Drop

1

Compile and

Debugger open

2



Debugger

Bus clock

RUN

Reset



Debugging TIP

Data Format Selectable by Variable

Use Automatic mode!!!

Blinking!



Programming 5 – Additional function : ADC

Bean select

at Converter

“ADC”

1

Generation

2

Channel select :

PAD02 3

Conversion time

Enter “10us” 4

Code generation

and Compile

7

A/D resolution

Select : 8bit

5

6

Macro function enable

“MeasureChan”, “GetChanValue”



Programming 6 – Utilize the Help code

Mouse right

button click!

Typical

Usage click!

Utilize the

example

code!



Programming 7 – Code input at main( )



Programming 8 – Code input at Events.c



Real Time debugger & Modification

Variable

Blinking

Speed !

Change

resistor

value !



Auto Code Generation by Processor Expert

1. Click on the

“Processor Expert“

TAB.

2. Select the “Generate

Code” option.

3. Select the

“Freeze Generated

Code” option in order

not to use the code

generation any more.



What is the FreeMASTER?

Real Time Monitor

Control Panel

Demonstration Platform

Test Panel

FOR YOUR

EMBEDDED

APPLICATION

• BDM/ICE Multilink Tool

• RS-232 Protocol **

• JTAG

** Requires user code

FreeMASTER Interface

Load

Freescale Processors

Supported by

FreeMASTER:

• 56F800/E DSCs

• HCS08

• HCS12

• Coldfire

• PowerPC Protocol Definition

CodeWarrior .abs / .map file

from project software code

Target Board / Hardware



FreeMASTER Setting 1 – Communication

“FreeMASTER” download from <www.freescale.com>

1

Project

Options



FreeMASTER Setting 2 – Target connection

Select

“Binary ELF with …..”

Choose the target file

( xxx.abs ) in project

folder (…/bin)



FreeMASTER Setting 3 – Variables selection

1

Project

Variables

Choose the

global variable

which you want

from list

2

3 4

5



FreeMASTER Variables Monitoring

Click mouse right

button and select

“Watch Properties”

1

2

3

4

5



FreeMASTER Scope

Click mouse

right button

and select

“Create Scope”

Click mouse right

button at Scope

and select

“Scope Properties”

1 2

3

4



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