itic

PR

Current mode

High linearity

Low-power

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ing

& 2011 Elsevier Ltd. All rights reserved.

growthnicatinded igratedgies [1r featucks, wingly.

realize the RF building blocks in the transmitter and receiver with

beennver-nver-hichtage-

provide the overall power conversion gain of 15.5 dB, which has

Contents lists available at ScienceDirect

.e

Microelectron

Microelectronics Journal 42 (2011) 766771specication of the current-mode transmitter is presented andwch1227164@sina.com (C. Wang).the advantages of a high linearity and a low power consumptionunder a supply voltage of 1.2 V, at the same time, its die size isonly 0.9 mm1.1 mm including testing pads.

The contents of this paper are as follows. In Section 2, the

0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved.

doi:10.1016/j.mejo.2011.01.009

n Corresponding author. Tel.: +86 13875902717.

E-mail addresses: wanqiuzhen@yahoo.com.cn (Q. Wan),2.4 GHz CMOS voltage mode transmitter and receiver front-endhave been published, such as [25]. However, it is difcult to

to-current (VI) conversion and reduce the nonlinearity contribu-tion. The proposed direct-conversion transmitter front-end couldAs for voltage mode circuits, the impedance of internal nodesis large so that the information is mostly carried by the time-varying voltage signal. This makes the voltage mode circuitsgradually face the problem of insufcient voltage headroom inthe case of low-voltage circuit designs. The papers regarding a

current mode approach in 0.18 mm CMOS technology hasproposed. For the high linearity performance, the direct-cosion transmitter is integrated with the current mode up-cosion mixer as well as the transimpedance driver amplier, wcould eliminate an unnecessary current-to-voltage (IV), volvoltage, the smaller the voltage headroom is left for designingcircuits. Low voltage headroom would deteriorate the perfor-mance of the RF building blocks and counteract the advantagesprovided by the advanced CMOS technologies if no specialtechniques are utilized.

direct-conversion transmitter operating with a low supply voltageand a low power. Therefore, current-mode circuits have a greatpotential in the design of the RF integrated circuits and thesystems in advanced nanometer CMOS technologies [69].

In this paper, a novel 2.4 GHz transmitter front-end using1. Introduction

Over the last decade, the rapidfrequency (RF) and wireless commuto considerable effort being expeperformance and low cost RF intewith the advanced CMOS technoloCMOS process provides the smalleperformance for the RF building blois required to be reduced accordin the eld of radio-on applications has ledn the design of highcircuits and systems]. The more advancedre size and the higherhile the supply voltageThe lower the supply

lower voltage and lower power consumption. Different circuittopologies and design techniques therefore need to be explored toovercome this problem. Unlike voltage mode circuits, currentmode circuits have low impedance at the internal nodes and thesignal information is carried by the time-varying current signal.Thus, the voltage signal at each node can be small, resulting inhigher linearity and lower power performance. It is well knownthat in the design of the RF building blocks, high linearity and lowpower dissipation are the key performance parameters. Thus, acurrent mode technique can be used to improve the linearity of aA low-voltage low-power CMOS transmapproach for 2.4 GHz wireless commun

Qiuzhen Wan n, Chunhua Wang

School of Computer and Communication, Hunan University, Changsha 410082, Hunan,

a r t i c l e i n f o

Article history:

Received 6 August 2010

Received in revised form

25 January 2011

Accepted 27 January 2011Available online 17 February 2011

Keywords:

CMOS

Up-conversion mixer

Driver amplier

a b s t r a c t

This paper presents a low

2.4 GHz wireless commu

technology. The direct up

input driver stage, which

current. The driver ampli

stage capacitive cross-cou

linearity. The measured r

power conversion gain, ou

(OIP3) of 13.8 dBm, while

1.2 V. The chip area includ

journal homepage: wwwter front-end using current modeations

China

ltage low-power transmitter front-end using current mode approach for

tion applications, which is fabricated in a chartered 0.18 mm CMOSversion is implemented with a current mode mixer employing a novel

signicantly improve the linearity and consume a small amount of DC

tilizes a transimpedance amplier as the rst stage and employs an inter-

g technique, which enhances the power conversion gain as well as high

ts show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of

t P1 dB of 3 dBm, and the output-referred third-order intercept pointwing only 6 mA from the transmitter front-end under a supply voltage of

the testing pads is only 0.9 mm1.1 mm.

lsevier.com/locate/mejo

ics Journal

the traditional transmitter architecture is discussed. Section 3presents the circuit design and implementation of each block indetail. The experimental results are described in Section 4 toverify the performances of the proposed current-mode transmit-ter front-end. Finally, the conclusions of this work are givenin Section 5.

2. Transmitter architecture

In the typical direct-conversion transmitter, a baseband digitalsignal is converted to an analog signal by a digital-to-analog

3. Circuit descriptions

3.1. Current-mode up-conversion mixer

3.1.1. Input current-squaring circuit and its class AB topology

The linearity of the conventional Gilbert-cell mixer is not goodmainly because of the VI converter nonlinearity, which becomesmore serious especially at lower bias current [12]. Because thecurrent mirror amplier is highly linear regardless of the biascurrent, where much better linearity is expected. The gain ofthe current mirror amplier can be easily set through appropriatescaling factor between the current mirror transistors. Therefore,we replaced VI converter by the current mirror amplier basedon the current-squaring circuit, which is modied from [13], asshown in Fig. 2(a). The transistors M1AM4A are biased tooperate in saturation region. Supposing that the threshold vol-tages of M1AM4A are Vth, the relation between VGS,M1A, io and iIF

DAC PA

Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771 767VGALPF

LOconverter (DAC), ltered and amplied by a low pass lter (LPF)and a variable gain amplier (VGA). This analog baseband signalis then up-converted to a RF signal by an up-conversion mixerand amplied by an on-chip driver amplier. Meanwhile a poweramplier (PA), after the driver amplier can deliver high outputpower, is used to satisfy the special system requirement. In thistraditional architecture, the up-conversion mixer and driveramplier are essential building blocks that generate a high powerconversion gain with good linearity. In general, these voltagemode transmitter front-end circuits require three seriesconnected transistors stacked between the supply rails, whichmake them unsuitable for low voltage operation. Moreover, thetraditional mixer designs convert IF input voltage to current andthen mixing to RF output voltage, and the driver amplierconverts the mixer output voltage into current and then backinto voltage for amplication. Thus, there appear several unne-cessary VI and IV conversions in the up-conversion mixer andthe driver amplier, which can cause nonlinearity and powerdissipation in the direct-conversion transmitter front-end [10,11].

With the motivation of low-voltage, low-power to fulll thedemand of new technology trends, Fig. 1 shows the block diagramof the proposed transmitter front-end architecture using currentmode approach for 2.4 GHz wireless communication applications.Here, the direct-conversion transmitter front-end is based on thecurrent mirror structure, which enables the VI converters to beeliminated in the baseband analog circuits and up-conversionmixer. Then, the amplication is performed by the transimpe-dence driver amplier to reduce the number of VI conversionthat result in the nonlinearity. By using this structure, the VIconversion of the up-conversion mixer input can be eliminated,and the current output of the mixer is directly connected to thetransimpedance driver amplier input. Besides, because thetraditional transmitter system need wide range of gain control,usually the driver amplier also implements gain control to serveas a RF variable gain amplier. This paper focuses on the low-voltage low-power design rather than gain control, hence, no gaincontrol is implemented in this version of the driver amplier, andthe gain control will be implemented in the next version. Thedetailed operational principles of the current mode up-conversionmixer and the transimpedence driver amplier are described inthe following part.

Current-mode Up-conversion mixer

Transimpedance driver amplifier Fig. 1. The proposed transmitter front-end architecture.can be expressed as

VGS,M1A vcc

2 iIFkw=lvcc2Vth

1

io N IBiIF2 iIF

2

16IB

!2

IB 1

8kw

lvcc2Vth2 3

where w/l is the channel width to the channel length ratio of theMOS devices, km0Cox is the mobility m0 times the oxide capaci-tance per unit area Cox. The current i1 is copied by the currentmirror amplier formed by M1A and M3A, and the aspect ratio ofM3A is N times that of M1A. From (2), the current-squaringfunction is realized. The transistor M4A acts as a current bufferand keeps the VDS of M3A the same as VDS of M1A to prevent fromthe channel length modulation. Also, there is freedom to choosethe aspect ratio and bias of M1AM4A. Therefore, by choosing aproper aspect ratio and bias of M1AM4A, the performance of thisstructure can be improved without inserting any additionalcircuit.

In general, the drain current IDS of a common-source MOStransistor can be expressed as

IDS IDS:dcgmvgsgum2!

v2gsguum3!

v3gsUUU 4

where gnm represents the nth order derivative of transconduc-tance gm with respect to small signal gate-to-source voltage vgs.The unwanted harmonic components inherently affected by thequadratic characteristic of MOS transistors, lead to leakages of

iIF

M3A

M4A

io

M1A

M2A

i1

VCC

VCC

IF+

M1

M2

M5 M7

M8M6

M3

M4

IF-

Fig. 2. (a) The proposed current-squaring circuit and (b) its cross-coupled class AB

topology.

input signals at the outputs, which usually counteract linearity ofthe current mirror amplier. It is well known that the linearity ofa CMOS RF building block can be improved by minimization guumof the circuits transconductance [14,15]. One way to minimizeguum of the current-squaring circuit is using the cross-coupledclass AB topology, which is shown in Fig. 2(b). The circuit has theadvantage that the current owing through M1 and M3 contri-butes to the output current, thanks to current mirrors MlM5 andM3M7. This arrangement makes the circuit less sensitive tolinearity degradation due to common-mode signals, since eachoutput depends on both inputs.

3.1.2. Mixer circuit

The circuit diagram of the proposed CMOS current-modeup-conversion mixer is shown in Fig. 3. The input current-squaring circuit as the input stage, which consists of M1M8. Asseen in Fig. 3, the current output of the current-squaring circuit is

improve linearity. On-chip capacitors (C1C8) are applied to bethe DC-blocking capacitors to isolate the input or output portfrom the dc source. The circuit is biased by means of currentmirrors (not shown in Fig. 3). Vb1 and Vb2 are the bias voltageswith the maximum DC supply voltage at 1.2 V.

Besides, R3 and R4 are the adequate resistors to enhancethe driving capability of the mixer output stage [16]. Due to theparasitic capacitors at the drains of M9M12, the impedance atthese nodes is reduced. Since the resistors (R3 and R4) make thehigh gain difcult to achieve, the peaking inductors (L3 and L4)are resonated at 2.4 GHz with parasitic capacitances whichprevent the signal loss into the silicon substrate to get the highestachievable gain. The peaking inductors (L3 and L4) have also aneffect, which can keep the current signal between the transimpe-dance input stage and the mixer output stage.

3.2. Transimpedance driver amplier

With the key point of high gain, low power consumption andhigh linearity, the solution proposed in this paper is the two stageclass AB transimpedance driver amplier. As can be seen in Fig. 4,the rst stage of the driver amplier is a transimpedance structurewhile the second stage is the conventional cascode topology.By using the transimpedance amplier, the IV conversion of themixer output can be eliminated, and the current output of the

M

C

C

Vb2R1 R2Vb1

OUT-

M14 M16

M20M18

M21

M22

M23

M24

L6 L5

C9

C11 C12

C13 C14OUT+Vb3 Vb3

VCC

Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771768IF+

IF-

M1

M2

M5M7

M8

M6

M3

M4 C1

C2capacitive coupled to the mixer core (M9M12), whose functionis to transfer the received incoming signal from current to currentthat serves as the biased current of the mixer core. This circuit hasseparate bias voltages for the current-squaring circuit and themixer core, allowing independent optimization for the perfor-mance in the two stages. The headroom requirements are alsorelaxed in this circuit because the tail current source in the mixercore does not govern the linearity, and hence can have muchsmaller gate-overdrive. The gain of current-squaring circuit isonly determined by the ratio of device sizes and the linearity ishardly affected by the voltage headroom.

In this design, the mixer core (M9M12) acts as switches tomodulate the output current signals provided by the current-squaring circuit, which are double balanced topology with theadvantage of rejecting the strong LO signal and the even-orderdistortion products. They switch the amplied IF current at a rateequal to the local oscillators frequency to realize the function ofmixer. The switching action generates an up-converted signal,which is same as that the IF current is multiplied by a squarewave. The bias voltage at the gate of the transistor M9M12 areset near to the threshold voltage Vth under dened the mixer coreof biasing current and output loading impedance in order toprovide a fast switching response. It is undesirable to set the biasvoltage higher or lower than the Vth. If the bias voltage is lowerthan the Vth, then the turn-on time will increase. If the gate biasvoltage is higher than Vth, the four switching transistors willalways be on, this will increase the power consumption. Thedegeneration inductors (L1 and L2) are used in the mixer to

VCCFig. 3. The proposed CMOS currenLO-

LO+9

M10M11

M12

L1 L2

L3

3

4

R3

L4

R4

RF+

RF-

C5

C6

C7

C8 VCC

M13 M15

M17 M19IN+ IN-C10

R5 R6

Fig. 4. The proposed transimpedance driver amplier.t-mode up-conversion mixer.

output spectrum of the proposed transmitter front-end at max-imum gain condition is plotted in Fig. 8. In this measurement, aninput IF signal at 10 MHz of which the signal level is 30 dBm andthe LO signal at 2.39 GHz are applied. The measured LO suppres-sion is more than 35 dB and all other unwanted harmonics are30 dB below the desired upper sideband (USB) signal, except forthe lower sideband signal, which is equal to the wanted uppersideband signal. However, this signal can be removed if I/Q(in-phase and quadrature) signals are applied.

Fig. 9 shows the measured power conversion gain of thetransmitter versus LO power. The overall power conversion gainis 15.5 dB at 2.4 GHz when the input LO power is 0 dBm. In the

M9M12 w/l51/0.18 mm C5, C6 4.5 pF R3, R4 305 OM13M16 w/l40/0.18 mm C7, C8 2.5 pF R5, R6 5.2 kO

Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771 769mixer is directly connected to the transimpedance amplier input.This reduces the voltage swing, as well as a redundant currentvoltagecurrent conversion. Thus signicant advantage is obtainedbecause it provides high dynamic range, as well as low powerconsumption. To relax the design constrains, the transimpedancestage consists of a CMOS inverter with the self-biasing by afeedback resistor [17]. Indeed, by stacking both NMOS and PMOStransistors, the overall equivalent transconductance of the inputstage is increased from gm to gm+gmp without additional powerdissipations for the same biasing current. Furthermore, this con-guration holds on the transistors in saturation region under aminimum supply voltage, without design tradeoff.

The second stage amplier, which employs the conventionalcascode topology, is designed for further signal amplication. Thecascode structure is a good choice for better isolation between therst and second stage amplier, also the reduction of the Miller effectonto the rst stage amplier. Another benet is that the RF gaincontrol can be more easily implemented at this cascode amplierwithout impairing the third order distortion cancellation of the driveramplier [4]. Essentially, the differential cascade structure can notonly reduce the second harmonics, but also increase the maximumoutput power with the additional power consumption.

At the same time, the inter-stage capacitive cross-couplingtechnique across the two stage driver amplier has been used.An obvious advantage of the capacitive cross-coupling is that it isinherently suitable for fully differential operation [18]. The capa-citive cross-coupling technique has been used for gain enhance-ment and inter-stage matching in this paper. The capacitive cross-coupling pair (C9 and C10) acts as two buffer ampliers, whichoffer a feedback loop to each NMOS of the differential cascadestructure to boost up the conversion gain in the high frequency. Itcompensates the high frequency gain decay of NMOS and furtherimproves the linearity of the driver amplier.

The two LC tank circuits, established by parallel connection ofon-chip spiral inductors (L5 and L6) and on-chip capacitors (C11and C12), and resonating at the operation frequency, are used toimprove the available power gain without requiring extra DCvoltage headroom. On-chip capacitors (C13 and C14) are appliedto be the DC-blocking capacitors to isolate the output port fromthe dc source. Vb3 is the bias voltage by means of current mirrorat 1.2 V DC supply voltage (not shown in Fig. 4). The sourcefollowers are used as the output driver stage for maximizing theoutput power and provide the required output impedance todrive the 50 O input port of the network analyzer.

M17M20 w/l90/0.18 mm C9, C10 0.4 pF L1L4 1.43 nHM21M24 w/l120/0.18 mm C11, C12 0.62 pF L5, L6 5.3 nHTable 1Summary of instance parameters.

Inst. Para. Inst. Para. Inst. Para.

M1M4 w/l1/0.18 mm C1, C2 10 pF C13, C14 5.6 pFM5M8 w/l320/0.18 mm C3, C4 3.6 pF R1, R2 307 OMost instances about the design parameters of the transmitterfront-end are summarized in Table 1.

4. Measurement results

The proposed transmitter front-end is fabricated in a chartered0.18 mm single-poly six-metal CMOS technology. A photomicro-graph of the fabricated transmitter front-end is shown in Fig. 5. Thedie size of the test chip is 0.9 mm1.1 mm including testing pads.The testing board has been built by directly bonding the die on atwo-layer FR4 substrate. Fig. 6 shows the experimental setup,which is used to measure the implemented current mode trans-mitter. C15 and C16 are the off-chip ltering capacitors to lowerthe noise induced by the supply voltage. In the measurementprocesses, the input IF signal and LO signal are converted from asingle-ended output of the signal generators to a differential signalby using external passive baluns, another external passive balun isused to combine the differential output signal to single-endedsignal at the RF output. A single-ended RF output signal is directlyconnected to a spectrum analyzer or a network analyzer both ofwhich have 50O to measure the output power spectrum and theoutput return loss (S22) of the transmitter front-end.

From the supply voltage of 1.2 V, the power consumption of thetransmitter front-end is 7.2 mW (not included the source followersdissipation of the driver amplier). The gain and power loss causedby the off-chip baluns and bonding wires have been de-embeddedfrom the measurement. Fig. 7 illustrates the measured result of theS22 (RF) return loss, which is below 13 dB from 1.8 to 2.8 GHz,indicating a good RF output matching condition. The measured

Fig. 5. Photomicrograph of the fabricated transmitter front-end.two-tone measurement, the two-tone signals injected into thetransmitter are at 10 and 10.1 MHz, while the input power level isswept from 30 to 2 dBm. The relationship between the inputand output power levels for the fundamental tones and third-order inter-modulation (IM3) products at maximum gain condi-tion are plotted in Fig. 10. The measurement result shows that theoutput P1 dB compression point and OIP3 of the transmitterfront-end approximately equal to 3 and 13.8 dBm, respectively.From the measurement results, the maximum output power ofthe transmitter front-end equal approximately to 4.5 dBm. Thepower amplier, if it is necessary, can be integrated to deliverhigher output power to satisfy the special system requirement.

CC

Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771770VCC V

C15 C16The measurement results meet the post-layout simulationresults quite good. Most of the values are 71 dB deviationcompared with the simulation results. The overall measuredperformance of the 2.4 GHz current-mode transmitter front-end

LOsource

Lbondwire

IFsource

Fig. 6. Block diagram of the tran

1 2 3-20

-5

-10

-15

0

40RF Frequency (GHz)

RF

Ret

urn

Loss

(dB)

Fig. 7. Measured output return loss (S22) of the transmitter front-end.

Fig. 8. Measured output spectrum of the transmitter front-end at 30 dBminput.Network

Lbondwireis summarized in Table 2, where comparisons with other publishedworks are also provided. From Table 2, the proposed current modetransmitter front-end can achieve a good linearity and a highconversion gain with low LO power, while at the same time, meetsthe requirement of low-voltage and low-power applications.

Matchnetwork Spectrum

alalyzer

alalyzer

smitter front-end test setup.

-6 0 3 6

16

14Co

nver

sion

Gai

n (dB

)

LO Power (dBm)

10

12

8

Conversion gain (USB)

-3

Fig. 9. Measured power conversion gain versus LO power with RF2.4 GHz.

RF

Out

put P

ower

(dBm

)

IF Input Power (dBm)-34 -24 -14 -4 4

15

0

-30

-15

-45

-60

IM3 (USB) USB

Fig. 10. Measured OIP3 of the proposed transmitter front-end (LO power: 0 dBm).

5. Conclusion

This paper has proposed the analysis and measurement of a

15.5 dB of overall power conversion gain, output P1 dB of 3 dBm,

References

[1] B. Razavi, CMOS technology characterization for analog and RF design, IEEEJournal of Solid-State Circuits 34 (1999) 268276.

[2] Y.S. Eo, H.J. Yu, S.S. Song, Y.J. Ko, J.Y. Kim, A fully integrated 2.4 GHz low IFCMOS transceiver for 802.15.4 ZigBee applications, in: IEEE Asian Solid-StateCircuits Conference, 2007, pp. 164167.

[3] H. Sjoland, A. Karimi-Sanjaani, A.A.A. Abidi, Merged CMOS LNA and mixer fora WCDMA receiver, IEEE Journal of Solid-State Circuits 38 (2003) 10451050.

[4] X.M. Yang, A. Davierwalla, D. Mann, K.G. Gard, A 90 nm CMOS directconversion transmitter for WCDMA, in: IEEE Radio Frequency IntegratedCircuits Symposium, 2007, pp. 1720.

[5] W. Kluge, F. Poegel, H. Roller, M. Lange, T. Ferchland, L. Dathe, A fullyintegrated 2.4-GHz IEEE 802.15.4-compliant transceiver for ZigBeeTM appli-cations, IEEE Journal of Solid-State Circuits 41 (2006) 27672775.

[6] W.C. Cheng, C.F. Chan, K.P. Pun, C.S. Choy, A low voltage current mode CMOSintegrated receiver front-end for GPS system, Analog Integrated Circuits andSignal Processing 63 (2010) 2331.

[7] F.R. Shahroury, C.Y. Wu, The design of low LO-power 60-GHz CMOS quad-rature-balanced self-switching current-mode mixer, IEEE Microwave andWireless Components Letters 18 (2008) 692694.

[8] I. Nam, K. Choi, J. Lee, H.K. Cha, B.I. Seo, K. Kwon, A 2.4-GHz low-power low-IFreceiver and direct-conversion transmitter in 0.18 mm CMOS for IEEE802.15.4 WPAN applications, IEEE Transactions on Microwave Theory andTechniques 55 (2007) 682689.

[9] G. Chandra, A. Kamath, P. Easwaran, A current mode 2.4 GHz direct conver-

Table 2Performance summary of the proposed transmitter front-end.

Parameters [10] [11] This work

Technology 0.18 mm CMOS 0.18 mm CMOS 0.18 mm CMOSLO power 3 dBm 2 dBm 0 dBmOutput return loss 23 dB 14 dB o-13 dBPower conversion gain 11.5 dB 16 dB 15.5 dB

Output P1 dB 3 dBm 2 dBm 3 dBmOIP3 12 dBm 13.8 dBm

LO suppression 24 dB 30 dB 35 dB

Supply voltage 1.8 V 1.25 V 1.2 V

Die size 0.96 (mm2) 0.8 (mm2)a 0.99 (mm2)

a It does not included the off-chip size.

Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771 771and the output-referred third-order intercept point (OIP3) of13.8 dBm. The excellent results have shown that the proposedcurrent-mode transmitter front-end is suitable for the applicationsof low-voltage low-power RF and wireless communication systems.

Future research will be conducted to design a complete2.4 GHz CMOS current mode single-sideband transmitter usingthe proposed I/Q signals arrangement and integrating it with anon-chip current mode analog baseband circuits.

Acknowledgement

The authors would like to thank the National Nature ScienceFoundation of China for nancially supporting this research underno. 60776021.signicantly improves the linearity performance. Two stage tran-simpedance driver amplier shares the inter-stage capacitive cross-coupling technique, which provides high enough gain as well ashigh linearity to drive 50O output loading. The measurementresults show that the transmitter front-end only consumes7.2 mW under a low supply voltage of 1.2 V, the circuit provides2005, pp. 50395042.[10] L.V. Hoang, N.T. Kien, S.K. Han, S.G. Lee, S.B. Hyun, Low power high linearity

transmitter front-end for 900 MHz Zigbee applications, in: IEEE InternationalSymposium on Circuits and Systems, 2006, pp. 16231626.

[11] T.K. Nguyen, A low-power, wide-range variable gain CMOS RF transmitter for900 MHz wireless communications, Analog Integrated Circuits and SignalProcessing 63 (2010) 177183.

[12] W. Qiuzhen, W. Chunhua, A 0.18 mm CMOS high-performance up-conversionmixer for 2.4-GHz transmitter application, Journal of RF-Engineering andTelecommunications 64 (2010) 1418.

[13] K. Bult, H. Wallinga, A class of analog CMOS circuits based on the square-lawcharacteristic of an MOS transistor in saturation, IEEE Journal of Solid-StateCircuits 22 (1987) 357365.

[14] T.W. Kim, B. Kim, K. Lee, Highly linear receiver front-end adopting MOSFETtransconductance linearization by multiple gated transistors, IEEE Journal ofSolid-State Circuits 39 (2004) 223229.

[15] L. Young-Wook, N. Ilku, K. Hong-Teuk, L. Kwyro, A highly linear widebandup-conversion differential CMOS micromixer using IMD3 cancellation for adigital TV tuner IC, IEEE Microwave and Wireless Components Letters 19(2009) 8991.

[16] C. Baoyong, S. Bingxue, W. Zhihua, A low voltage CMOS RF front-end for IEEE802.11b WLAN transceiver, Analog Integrated Circuits and Signal Processing48 (2006) 6777.

[17] Q. Huang, P. Orsatti, F. Piazza, GSM transceiver front-end circuits in 0.25 mmCMOS, IEEE Journal of Solid-State Circuits 34 (1999) 292303.

[18] F. Xiaohua, Z. Heng, E. Sanchez-Sinencio, A noise reduction and linearityimprovement technique for a differential cascode LNA, IEEE Journal of Solid-State Circuits 43 (2008) 588599.of cross-coupled class AB topology as the input stage, which sion receiver, in: IEEE International Symposium on Circuits and Systems,2.4 GHz CMOS direct-conversion transmitter front-end, which isfabricated in a chartered 0.18 mm CMOS technology. The currentmode up-conversion mixer uses the input current-squaring circuit

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4GHz wireless communicationsIntroductionTransmitter architectureCircuit descriptionsCurrent-mode up-conversion mixerInput current-squaring circuit and its class AB topologyMixer circuit

Transimpedance driver amplifier

Measurement resultsConclusionAcknowledgementReferences