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FRAIGs: Functionally Reduced

And-Inverter Graphs

Adapted from the paper “FRAIGs: A Unifying Representation for Logic Synthesis and Verification”, by Mishchenko,

Chatterjee, Jiang, Brayton, UCB Technical Report 2005

By

Ashesh Rastogi

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Outline

• Background on AIGs

• FRAIGs

• Applications of FRAIGs

• Experimental Results

• Conclusions

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Background• AND-INVERTER Graphs (AIGs)

– Boolean Network composed on 2-input AND gates and Inverters

– Representations:

NAND OR

a

bab

a b a b

ba

a + b ba

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Background• Properties of AIGs

– Function fn(x) of AIG node n – logic cone rooted at node n with base as PI

– Nodes of AIG – Number of AND gates

– Levels of AIG – Number of AND gates on the longest path from PI to PO

– Number of nodes Number of literals in factored form

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Background• Properties of AIGs

– Not Canonical

– Note: These AIGs are FRAIGs

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Background• AIG Construction

– Given a SOP

– Convert it into factored form

– Convert all 2-input OR gates into 2-input AND gates using DeMorgan Rule

bcddcaacd)c,b,F(a,

bc)cd(aacd)c,b,F(a,

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Background• AIG Construction

– Given a circuit– Perform recursive construction for each PO– At each step add new AND gate and

• Perform Structural Hashing (Strashing)• One-Level Strashing: Check for AND gate with

same fan-ins by looking at hash table• No Strashing: Don’t check – leads to redundant

nodes

– If a PI node: Create an AIG variable – Else construct AIG node for factored form

node

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Background• AIG with redundant nodes

• Has 11 Nodes and 5 Levels

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FRAIGs• Properties of FRAIGs

– For any two nodes n1, n2• and

– “Semi-Canonical”: No two functions have same PIs but still have different structures

– Possess same properties of AIGs

(x)fn(x)fn 21 (x)fn(x)fn 21

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FRAIGs• FRAIG Construction

– Perform one-level strashing– Perform functional equivalent test

• Do random simulation for each node by calling SAT solver

• Store results in a look-up table • Check new node functionally equivalent to old

node

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Applications of FRAIGs

• Traditional Logic Synthesis– Helps create compact circuits– Uniform representation of DAGs and algebraic

factored forms

• “Lossless” Logic Synthesis– Collect all logic representations obtained over

several optimization steps

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Applications of FRAIGs

• Technology Mapping– More structural mapping choices (Lossless

Synthesis)– Improved mapping quality

• Formal Verification– Improved Combinational Equivalence

Checking (CEC)– Ensures transformation at each step of

synthesis is functionally correct

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Experiment Results

• fraig -n: No strashing• fraig -r: One-level strashing• fraig: One-level strashing with functional reduction

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Experiment Results

• fraig -f: SAT solver feedback not used• fraig -s: No functional equivalence check

for sparse functions

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Experiment Results

• With and without structural choices

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Experiment Results

• Runtimes in MVSIS environment and on 2.4GHz Xeon CPU

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Conclusions• FRAIGs help in unifying all steps of logic

synthesis– Optimized functional representation– Enhanced technology mapping with help of lossless

synthesis– Transparent CEC: Guarantees all transformations

correct

• More robust than BDDs

• FRAIG is available for use in ABC Package

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QUESTIONS ?