Microelectronics Journal, 28 (1997) 1

FPGAs Achieve Superior Speed and Density with Antifuse Advancements Al Giraf Manlager of PLD Applications, Cypress Semiconductor

FPGAs basen on low-resistance, low-capacitance “ant$se” programmable elements ofleer very high-speed

performance with small, cost-eJectivc die sizes for high-volume pvoduction applications. FPGA vendors continue to invest in this technology to push further into the pevfovmance an,d density/cost realm pveviously dominated by conventional mask pvoyvammed ASICs. Thcsc high-pcr$ovmancc, high-density antifiise based products will ji.&cv distance themselves in speed, cost, and ease-of-use from slowcv, move costly RAM-based FPGAs.

Cypress introduces Ultra38000 family of FPGAs Cypress has recently introduced its new Ultra38000 family of FPGAs. This family pushes further the speed ;and density of low-resistance, low-capacitance antifuse-based FPGAs to new levels. This family includes devices ranging in density up to 20,000 gates of logic measured by comparable applications capacity to equivalent density gate arrays. Table 1 shows the members of the Ultra38000 family. An improved antifuse element in the Ultra38000 family increases speed by further reducing the already low capacitance of the antifuse element in Cypress’s pASIC380 FPGA family. This lower capacitance, combined with the already low resistance of the antifuse element, reduces further the RC time constant of the programmable

Cypress Semiconductors Ultra33XOO7 die

element, resulting in a 25’% increase in speed compared to the industry’s previously fastest FPGAs, the pASIC380 family. The Ultra38000 family utilizes three-layer metalization for interconnect with metal-to-metal

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7C38003 7C38005 7C38007 7C38009 7C380012 7C380016 7C380020 7C338003 7C338005 7C338007 7C338009 7C3380012 7C3380016 7C3380020

Usable 3,000 5,000 7,000 9,000 12,000 16,000 20,000 gates

Logic 192 320 480 672 896 1152 1440 cells

II/O cells 1 120 1 156 1 192 I 228 I 264 1 304 / 340 1

Table 1. Cypress Ultra3XOOO FPGAs

antifuse elements (Figure 1). This technology allows, for the first time, the programmable antifuse elements to be constructed on top of the underlying logic circuits. This approach has allowed a dramatic reduction in die size which translates to lower costs. The Ultra38000 logic cell offers the high performance of a coarse-grained cell in terms of an input count (29 inputs) that lets wide functions be

cell - i.e., the cell permits up to five “fragments,” for simple functions (Figure 2). Such fragmentation emulates a sea-of-gates architecture, greatly simplifying logic synthesis and improving logic packing density. The new Ultra38000 family is fully PC1 compliant and offers 3.3V versions suitable for use in portable systems. In addition, full JTAG compatibility is offered for incorporation in TTAG-based system

completed in a &ngle cell, and it offers the I J

test and diagnostics. maximum utilization associated with a fine-grained

Metal 3 Vertical T&s /n/s Vialink

wzngsten Plug Vii

Substrate 0.6% CMOS Metal 2 Logic Cell Widng

Figure 1, Three layer metalization for interconnect with metal-to-metal ant&e element.

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Microelectronics Journal, Vol. 28, No. I

Figure 2. Ultra 38000 logic cell permits up to 5 “fragments” for simple functions.

Trends in development tools

Rise of Synthesis for FPGAs The future of FPGA design tools will be characterized by implementation of design descriptions at a hig:her level of abstraction. These design descriptions will better match the system conceptualization process. Tools will offer high-quality synthesis from high-level HDL-based design descriptions and will allow implementation ofproven subsystem design descriptions in libraries which can be reused to accelerate the design process and enhance designer productivity. To improve synthesis, many FPGA manufacturers have been developing “synthesis friendly” FPGA architectures. Too often these “fine grained” architectures have mimicked older gate array architectures by implementing architectures based on simple “2 input NAND” based elements, and therefore perpetuated older logic synthesis and mapping algorithms;. However, use of such fine grained architectures for FPGAs has never been successful because they require a very large

number of programmable elements per configured logic function and, therefore, make less efficient use of silicon when compared to industry leading “large grained” devices. Further, these fine grained FPGAs do not support wide input functions well, requiring slower configurations of many more levels of logic as compared to larger grained devices with a wider available input field to the basic logic cell. What is needed is a combination of new, regular architectures with new companion architecture-specific synthesis algorithms which can deliver high-quality synthesis and high device utilization without compromising the silicon efficiency of the device. To achieve improvements in both architecture and synthesis methodology, it is essential for FPGA manufacturers to be involved in the development of synthesis algorithms for their architectures. Some FPGA and CPLD manufacturers have abandoned the essential effort of synthesis methodology development for their architectures, choosing to be supported only by third-party design tool companies which must develop support for all vendors. These FPGA

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vendors will ultimately be doomed to poorer comparative synthesis efficiency and lower system-level logic efficiency because the third party developer is likely to be neither knowledgeable enough of the capabilities of a specific architecture (having all manufacturers architectures to support), nor motivated to achieve superior synthesis and fitting for any one company’s architecture.

adoption of standards and incorporation of FPGA synthesis and mapping tools in larger scope design environments will not free the FPGA vendor from the pressure to continue to improve software methodology for architecture specific synthesis and mapping for its devices. This pressure will further increase as these tools will need to be more seamlessly integrated into those popular CAE design environments already in use at customer design facilities.

The Importance of Design Environment Compatibility As system designers have endorsed an integrated CAD approach to electronic system design, the range of activities that must be accomplished within the CAE environment has increased. With the arrival of the CAE “framework” all design activities can be managed within the same CAE environment. These activities include system specification, documentation, revision management, component selection and specification, project management, design capture at all levels of abstraction, design verification and documentation, and design verification at subsystem level and for the entire system. This integrated approach to system development will dictate that the specialized synthesis and place-and route-tools required to efficiently implement portions of a system in FPGAs must be available within all of the popular CAE environments. The need to provide sophisticated, architecture-specific synthesis and fitting technology for multiple vendors’ FPGAs in these CAE frameworks is forcing a greater degree of interdependence and cooperation between FPGA vendors and CAE tool vendors. It will stimulate greater cooperation in the development of emerging standards for design description and interchange such as VHDL for HDL design entry and LPM (Library of Parameterized Modules) for schematic design capture and communication between design environments. Future standards efforts such as VITAL (VHDL Initiative Toward ASIC Libraries) will standardize the format for simulation models to allow one set of models for each vendor’s FPGA to be used by all simulation tools which support the standard. This wider

Cypress is the only FPGA vendor to have developed its own VHDL synthesis. The powerful Warp software, in combination with the high-performance, synthesis-friendly architecture of the Ultra38000 family of FPGAs, offers users the best combination of speed, device utilization, and cost available.

Conclusion Improvements in antifuse technology continue to advance FPGAs to levels of performance, density and cost effectiveness which were previously the realm of conventional ASICs. This penetration of the traditional ASIC realm will open new opportunities for designers to utilize the convenience and flexibility of FPGAs in high-volume, low-cost applications. This added flexibility will make system manufacturers more responsive to market changes and competitor tactics, while streamlining the product development process by giving designers greater freedom to try more design options while simultaneously shortening the design iteration cycle. The power of FPGAs to transform and accelerate the product development process will now be available to designers in the most competitive, cost sensitive markets where this power can be applied to full benefit.

Acknowledgement This article is published with tlzc pcmissiorl of Cypress Semiconductor, 3901North First Street, San Jose, CA 95134-1599. Tclflax: [1](408)943 2600/2796. URL: www.cypress.cont

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