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Transcript of FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University...
![Page 1: FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.](https://reader030.fdocuments.in/reader030/viewer/2022032605/56649e725503460f94b713e6/html5/thumbnails/1.jpg)
FPGA Switch Block Design
Dr. Philip BriskDepartment of Computer Science and Engineering
University of California, Riverside
CS 223
![Page 2: FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.](https://reader030.fdocuments.in/reader030/viewer/2022032605/56649e725503460f94b713e6/html5/thumbnails/2.jpg)
FPGA Architecture (Recap)
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Routing Instance and an S Block
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Flexibility of Interconnection Structures for Field-
Programmable Gate Arrays
J. Rose and S. Brown,IEEE Journal of Solid-State Circuits 25(3): 277-282,
Mar. 1991
![Page 5: FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.](https://reader030.fdocuments.in/reader030/viewer/2022032605/56649e725503460f94b713e6/html5/thumbnails/5.jpg)
Key Questions
• What is the effect of C Block flexibility on routing completion rate?
• What is the effect of S Block flexibility on routing completion rate?
• How do S and C Block flexibilities interact?
• What is the effect of S and C Block flexibilities on the number of tracks per channel to achieve 100% routability?
![Page 6: FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.](https://reader030.fdocuments.in/reader030/viewer/2022032605/56649e725503460f94b713e6/html5/thumbnails/6.jpg)
Switch Block Flexibility• Total number of possible connections offered
to each incoming wire
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Switch Block Routability
• Cannot route from A to B
• Can route from A to B– Assymmetric about
horizontal and vertical axes
Fs = 2Fs = 2
![Page 8: FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.](https://reader030.fdocuments.in/reader030/viewer/2022032605/56649e725503460f94b713e6/html5/thumbnails/8.jpg)
Example Connection Block
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Routability Study (One Benchmark)
W = 14
• Increasing FS improves routability, but FC must be high to achieve 100% routability
• Routing completion rate approaches 100% when FC > ½W
• Routing completion rate is low for low values of FC
![Page 10: FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.](https://reader030.fdocuments.in/reader030/viewer/2022032605/56649e725503460f94b713e6/html5/thumbnails/10.jpg)
Routability Study (One Benchmark)
W = 14
• If FC is high enough, then low values of FS can achieve 100% routability
• The number of different paths between the initial physical pin and the terminating C Block of a two-pin wire is given by:
where N is the number of S Blocks on the global path
• For lower values of FC, increasing FS improves routability up to a point
![Page 11: FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.](https://reader030.fdocuments.in/reader030/viewer/2022032605/56649e725503460f94b713e6/html5/thumbnails/11.jpg)
S Block vs. C Block FlexibilityAv
g. F
C/W
for 1
00%
routi
ng c
ompl
etion • A more flexible
S Block can compensate for a less flexible C Block
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Track Count Requirement for BNREto Achieve 100% Routability
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Conclusion
• C Blocks should have high flexibility to achieve high-percentage routing completion
• S Blocks require limited flexibility
• With low flexibility, only a few extra tracks more than the minimum can achieve 100% routability
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Universal Switch Modules for FPGA Design
Y-W. Chang et al.,ACM Transactions on Design Automation for Electronic Systems 1(1): 80-101, Jan. 1996
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Overview
• A Switch Block with larger routing capacity has better area-performance in FPGA routing– Increased connectivity of routing components– Equivalence of LUT/CLB inputs permits pin
permutations, which yields highly optimal routing– Most nets are short
• 60% of nets route through at most 2 Switch Blocks• 90% of nets route through at most 5 Switch Blocks
• Tradeoff between routing capacity and area
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Universal Switch Module DefinitionRouting Resource Vector (RRV):N = (n1, n2, n3, n4, n5, n6), 0 < ni < W
Example: N = (1, 0, 1, 1, 0, 0) is routable on the following:
n1
n4 n3
• A Switch Block of size W is universal if the following inequalities are sufficient to determine of an RRV is routable:
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Examples
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Universal Sub-modules
• A sub-module of a Universal switch is also universal (but for a smaller W)
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Theoretical Results
• A universal S Block can be constructed with at least 6W switches
• Any S Block constructed with less than 6W switches cannot be universal
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Non-universal S Blocks
Disjoint Switch Block (Xilinx XC4000 series)
Antisymmetric Switch Block (Rose and Brown, 1991)
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Channel Width Required for 100% Routing Capacity (One Benchmark)
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Conclusion
• Universal S Blocks offer better routability than disjoint and antisymmetric S Blocks
• Algorithm presented to generate S Blocks that are universal (not discussed)
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Architectures and Algorithms for Field-Programmable Gate Arrays
with Embedded Memory
S. Wilton,Ph.D. Thesis, University of Toronto, 1997
(Section 6.1.2)
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S Blocks
Disjoint Universal Wilton
Start with Universal S Block, and rotate the diagonal connections by one track
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FPGA Routing Structures: A Novel Switch Block and Depopulated
Interconnect Matrix Architectures
M. I. Masud,M.S. Thesis, University of British Columbia, 1998
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Routing with a Disjoint S Block
• Routing fabric partitioned into domains• Cannot cross domains (using routing only)
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Routing with a Wilton S Block
• Eliminates domain choice problem• Many more routing choices are available
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Implementation Details
WiltonDisjoint
WiltonDisjoint
Area Overhead
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Imran S Block
• Routability of Wilton S Block• Implementation efficiency of Disjoint S Block
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Imran S Block(1) Tracks that terminate at the S Block
• Wilton topology
(2) Tracks that pass through the S Block• Disjoint topology
![Page 31: FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.](https://reader030.fdocuments.in/reader030/viewer/2022032605/56649e725503460f94b713e6/html5/thumbnails/31.jpg)
Area Results
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Delay Results
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Channel Width Results
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Conclusion
• Imran Switch Block– Routability of Wilton Switch Block– Area-efficiency of Disjoint Switch Block