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FPGA Implementation of a PWM for a Three-Phase Dc-Ac Multilevel Active-Clamped Converter

Abstract- With the aim to implement a suitable controller for a three-phase dc-ac multilevel active-clamped converter to enable its use in practice, and as a first step towards a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the structure and features of a FPGA implementation of an appropriate pulsewidth modulation (PWM) strategy. The selected PWM strategy guarantees dc-link capacitor voltage balance in every switching cycle and covers both the undermodulation and overmodulation regions. A flexible implementation is conceived, allowing the variation of important operating parameters such as the modulation index and switching frequency through a simple user interface. The key aspects to achieve an efficient and robust FPGA implementation are discussed. Experimental results in a four-level converter prototype controlled with an Altera Cyclone III device under different operating conditions match fairly well the expected results obtained through simulation, thus verifying the accurate performance of the FPGA-based modulator.

I. INTRODUCTION

Power electronics converter technology evolves towards multilevel topologies with higher number of switching devices, higher switching frequencies to obtain higher power density and better dynamic performance, and increased control complexity. One of such topologies is the recently proposed multilevel active-clamped (MAC) topology [1], shown in Fig. 1(a) for a four-level case, which is built upon a single controlled switching semiconductor device with an antiparallel diode. The functional model of the converter leg is the same as for a diode-clamped converter: a single-pole four-throw switch that connects the output leg terminal to one of the four input leg terminals through the application of the corresponding switching state. Compared to a multilevel diode-clamped converter, which presents a lower controlled switch count, the active-clamped topology advantages are [1]:

lower conduction loss, better distribution of switching losses, device blocking voltage always equal to one dc-link capacitor voltage, and increased fault-tolerance capacity. Motor drives, and in particular the traction inverter of electric vehicles, is one of the applications where the MAC topology could bring benefits. For this purpose, three legs can be connected to a common dc-link to obtain the four-level three-phase active-clamped converter of Fig. 1(b). However, in order to take full advantage in practice of the topology benefits, a robust and efficient controller has to be developed at a reasonable cost and with reduced complexity. This is the final goal of the present study.

Power converter control has been progressively migrating from the analog to the digital domain [2]. With the improvement of digital control devices and control techniques, in many applications, the inherent drawbacks of digital control (i.e., finite resolution leading to a reduced accuracy and the need of sampling and processing time leading to delays) have been compensated by the advantages: increased control complexity, flexibility, repeatability, reliability, versatility, and expandability.

Typical power converter digital controllers are based on microprocessors (µP), digital signal processors (DSP), field-programmable gate-arrays (FPGA), or a combination of them.

µPs and DSPs contain a central processing unit (CPU, fixed hardware) in charge of sequentially processing a set of instructions. They are therefore known to be software programmable. Microcontrollers and digital signal controllers embed the µP or DSP core, memory, and input/output peripherals (including PWM units) in the same chip. The programming can be performed with high-level algorithmic languages familiar to most designers.

Vdc C

C

+

–

+

–

vC2

vC1

+

–

C +

–vC3

ic

RL LL

Three MAC Legs

i4

i3

i2

i1

o3

o2

o1

c

ib

RL LL b

ia

RL LL a

1

2

3

4

+

–

vab

(a) (b) Fig. 1. MAC converter [1]. (a) Four-level leg topology. (b) Four-level three-phase dc-ac converter.

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FPGAs [3] basically contain an array of logic elements or cells (each cell containing look-up tables and registers), whose interconnections are decided by the contents of a random access memory (RAM). The FPGA design, typically using hardware description languages, decides the final circuit structure to achieve a desired functionality and it is therefore said to be hardware programmable. Besides a large number of configurable input/output blocks, FPGAs also typically contain additional optimized RAM blocks and multipliers to increase the performance of the device. Logic, adders, subtractors, comparators, multipliers, and special functions are easy to implement in these typical FPGAs. Special functions are implemented using look-up tables in RAM blocks. However, RAM size increases exponentially with the resolution of the input variables. Multipliers and dividers by powers of two are immediate. Nevertheless, general dividers are more complex. The hardware programmability of FPGAs allows both the concurrent or parallel processing of data and pipelining, which may dramatically reduce the required processing time and increase the number of computations per switching cycle, compared to µPs and DSPs. Additionally, in cases where the implementation of the desired control benefits from the use of a CPU, this can be embedded within the FPGA through the programming of the corresponding circuit. FPGAs have been employed in the control of a number of different topologies and applications [4]-[40], but specially for the control of multilevel converters [17]-[40] and the implementation of PWMs ([4]-[9], [18], [20]-[37], [40]), predictive controls ([10], [38], [39]), and fault-tolerant controls [14].

Due to wide device availability and familiarity with software programming, µP and DSP were the preferred designer’s choice in the first digital control implementations. As control requirements became more stringent from the point of view of processing time and number of PWM outputs, many designers opted for a combination of a µP or DSP with a FPGA ([13], [17], [35]). The sequential processor is in charge of the high level control tasks, while the FPGA typically implements the PWM strategy and subsequent switch control signal generation. One critical reason to combine two devices is that current microcontrollers do not contain enough PWM units to control multilevel converters. This is not the case of FPGAs, which contain a large number of possible output pins that can be controlled precisely to generate the switch control signals.

Due to the FPGA inherent advantages and expected future improvements, the authors foresee a progressive trend towards a full closed-loop converter control implementation within a single FPGA. In addition to performance improvements, this also saves costs and avoids the cumbersome synchronization and communication between the µP or DSP and the FPGA. Therefore, a full FPGA-based implementation of a three-phase dc-ac MAC converter controller is concluded to be the best choice. The authors final goal is to implement a closed-loop controller with relevant voltages and currents sampled as close as possible to

the beginning of the switching cycle where these values are applied. As a first step, in this paper, the controller is implemented in open-loop with the same philosophy: updating the PWM variables as close as possible to the beginning of the switching cycle. The description of the remaining closed-loop control implementation will be presented in a complementary future publication.

The paper is organized as follows. Section II reviews the PWM strategy and presents a suitable algorithm from which the FPGA implementation can be discussed. Section III explains the implementation structure and relevant design details to obtain an efficient and robust controller. In Section IV, simulation and experimental results are compared to verify the good performance of the designed modulator under different operating conditions. Finally, Section V presents the conclusions.

II. PWM STRATEGY

The PWM presented in [41] and extended to the overmodulation region in [42] is selected to operate the converter in Fig. 1(b). This PWM, originally defined applying the virtual-vector concept, guarantees the dc-link capacitor voltage balance in every switching cycle and all operating conditions, as long as the phase currents are approximately constant over the switching cycle and their addition is equal to zero. This allows minimizing the size of the dc-link capacitors, leading to a high converter power density. The PWM assumes that the switching frequency (fs = 1/ts, where ts is the switching or sampling period) is much larger than the fundamental frequency. This PWM allows modulation index values m [0, 1.1027], where m = vab,1,pk/Vdc and vab,1,pk is the peak value of the fundamental component of the line-to-line converter voltage. Therefore, it covers both the undermodulation (UM) and overmodulation (OM) ranges up to six-step operation. The overmodulation region is further divided into two subregions (OMI and OMII) with different type of applied reference vector trajectories [42].

This PWM can be defined with the following algorithm. First of all, from the desired reference vector normalized length and angle (m* and *, respectively), the values of the applied length and first-sextant equivalent angle (m, 1) are determined as

m*maxI = 3·ln(3)/

m*maxII = (2/)·sqrt(3)

(1)

sexta = 1+floor(*/(/3)) sextb = mod(sexta+4, 6) sextc = mod(sexta+2, 6) *

1 = mod(*, /3)

(2)

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if (m* > hbc·m*

maxII){ m* = hbc·m*

maxII

}end

mode = 01 m = m* 1 = *

1 if (hbc < m* hbc·m*

maxI){ mode = 00; lim = (/6)·(1–(m*–hbc)/(hbc·m*

maxI–hbc)) km1 = hbc/sin(lim+/3) km2 = 1/sin(*

1+/3) if (lim < *

1 /3–lim){ m = hbc·km2 }else{ m = km1 }end }elseif (hbc·m*

maxI < m* hbc·m*maxII){

mode = 10 lim=/6·(m*–hbc·m*

maxI)/(hbc·m*maxII–hbc·m*

maxI) km1 = hbc·2/sqrt(3) km2 = 1/sin(*

1+/3) if (*

1 < lim){ m = km1 1 = 0 }elseif (*

1 /3–lim){ m = km1 1 = /3 }else{ m = hbc·km2 }end }end,

(3)

where hbc 1 is an special parameter that regulates the capacitor voltage balance control margin in the overmodulation region [42].

Next, the value of auxiliary variables tα, tβ, t, and t are computed as

.21

6cos,2

6cos,2

1tst

1tαstα

tt

ttt

ktkmt

ktkmt

(4)

These auxiliary variables will be used to define the final dwell times of connection to the dc-link terminals t1, t2, t3, and t4, with reference to Fig. 2. But previously, they need to be modified so that final dwell times fall into a specified value range, as will be commented later: .,,,,,,, 2m1mmmm ttttfttttt (5)

Finally, the leg x {a, b, c} dwell times of connection of the leg output terminal to each input terminal are determined with the simple assignments indicated in Table I.

TABLE I LEG DWELL-TIMES COMPUTATION

sextx Leg x dwell times 1 t1 = 0 t2 = tm2 t3 = tm2 t4 = tβm 2 t1 = tm t2 = tm1 t3 = tm1 t4 = tαm 3 t1 = tβm t2 = tm2 t3 = tm2 t4 = 0 4 t1 = tβm t2 = tm2 t3 = tm2 t4 = 0 5 t1 = tαm t2 = tm1 t3 = tm1 t4 = tm 6 t1 = 0 t2 = tm2 t3 = tm2 t4 = tβm

i4

i3

i2

i1

t4 t4

t3 t3

t2 t2 2·t1

sn11 tbh

sp11 tbh

tbh

tbh

sp12 tbh tbh

sp13 td td

sn21 tbh

sn22 td

tbh

sp21 tbh tbh

sp22 td td

td

sn31 tbh

sn32

tbh

tbh

sn33

tbhsp31

td

tbh

td

tbh

Leg

out

put t

erm

inal

co

nnec

tion

n·ts (n+1)·ts

t

Fig. 2. Distribution of the leg output terminal connections over a switching cycle and corresponding switch control signals (high level: switch on; low level: switch off).

Fig. 3 illustrates the resulting leg duty-ratio pattern (di = 2·ti/ts) over a line cycle for four different values of m*. The other two legs have the same duty-ratio pattern but phase shifted 120˚.

The distribution of the leg output terminal connections over a switching cycle and the generation of the twelve switch control signals is performed according to Fig. 2, where tbh = tb/2 is half of the blanking time required between the turn-off of a set of devices and the turn-on of others to produce a change of the leg switching state; and td is a delay time used whenever several switch control signals change concurrently, so that switching losses of a transition between switching states concentrate on one specific switch (the one that turns on first or the one that turns off last, depending on the current polarity).

In this paper, the correction in (5) is made so that final dwell times verify

t2 , t3 [2·tb, ts/2] t1 , t4 {0 , [2·tb, ts/2 4·tb]}.

(6)

It is forced that t2, t3 ≥ 2·tb to avoid direct transitions of the leg output terminal connection between nonadjacent input terminals. It is further requested that t1, t4 ≥ 2·tb whenever they are not zero, to avoid narrow gate pulses.

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nly0 60 120 180 240 300 360

0

0.2

0.4

0.6

0.8

1

* [degrees]

d1

d2 = d3

d4

(a)

0 60 120 180 240 300 3600

0.2

0.4

0.6

0.8

1

* [degrees]

d1

d2 = d3

d4

(b)

0 60 120 180 240 300 3600

0.2

0.4

0.6

0.8

1

* [degrees]

d1

d2 = d3

d4

(c)

0 60 120 180 240 300 3600

0.2

0.4

0.6

0.8

1

* [degrees]

d1

d2 = d3

d4

(d)

Fig. 3. Leg ‘a’ duty-ratio pattern over a line cycle (hbc =0.98). (a) m* = 0.25. (b) m* = 0.75. (c) m* = 1.0. (d) m* = 1.05.

III. PWM IMPLEMENTATION

The previous PWM strategy is implemented into an Altera Cyclone III EP3C16F484C6 FPGA device with a 50 MHz oscillator, mounted on a DE0 development and education board from Terasic. The device architecture structure and functionality has been fully described in very-high-speed integrated-circuit hardware description language (VHDL). The simulation has been performed with ModelSim software from Mentor Graphics. The synthesis has been performed with Quartus II software from Altera. Simulation results have been compared to the results obtained from Matlab-Simulink simulations. The main PWM parameters are set to be user-configurable through ten slide switches (SdS) to introduce the

parameter code and value, and one pushbutton switch (PBS) to validate the data while the converter is in the off state. Table II lists these parameters, their value range and resolution, from which it can be easily derived a 158 Hz to 625 kHz range of possible switching frequencies. This allows thoroughly testing the implemented modulator performance under a wide range of operating conditions and power hardware prototypes. Two additional PBS are used to turn-on/off the converter and to reset the system.

A. Basic Design Aspects Variable values are represented in fixed-point format to

reduce hardware needs. Identification of symmetries, value offset, and value scaling are applied whenever possible to minimize the number of bits required to obtain a specified resolution.

All operations in the algorithm of Section II are easy to implement, except for divisions and transcendental functions. Expression (1) contains simple constants that can be precalculated. Expression (2) highlights the sixty-degree symmetry of the algorithm. The divisions and trigonometric functions in (3) require a detailed analysis to obtain the simplest implementation. Fig. 4 deploys the pattern for km2, ktα, and ktβ, from which 30-degree symmetries, proper offset values, and proper scaling values can be identified.

A basic time unit equal to td is defined. A clock signal with period td is generated to control most of the FPGA processing. All time variables are expressed as an integer number of this basic unit or power-of-two multiples of this unit. 16-bit counters are necessary to count td units over a whole switching cycle.

A basic angle unit (au) is defined so that each switching cycle corresponds to an integer number of au for every combination of fo, td, tb, and ts parameter values. This reduces to one simple addition modulus a sextant the calculation of the next switching cycle angle.

TABLE II CONFIGURABLE PWM PARAMETERS

Parameter name

Description Range Resolution

fo Fundamental ac frequency [5, 200] Hz 5 Hz m* Modulation index [0.01, 1.10] 0.01

hbc Hexagonal boundary compression factor

[0.7,1.0] 0.01

td Delay time [20, 100] ns 20 ns tb Blanking time [4, 62]·td 2·td ts Switching period [20, 1020]·tb 4·tb

0 10 20 30 40 50 600

0.2

0.4

0.6

0.8

1

1.2

*1 or 1 [degrees]

km2

ktα

ktβ

Fig. 4. Parameters km2, ktα, and ktβ as a function of *

1 or 1.

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On the other hand, to maximize the resolution for a given number of bits, one sextant of a line cycle must correspond to a number of au slightly lower than a power of two. It is finally set that one sextant contains 1,875,000 au. Thus, all angles lower than 60 degrees can be represented with 21 bits.

B. Controller Structure and Module Description The designed controller structure, applying concurrent

processing as much as possible, is depicted in Fig. 5. It is composed of a set of blocks or modules, classified as auxiliary (A1-A6) and main (M1-M11) modules. The applied variable value offset and scaling to optimize the implementation is not explicitly shown in the diagram.

From the 50 MHz system clock signal clk50M, having a period tck = 20 ns, module A1 generates the clock signal clktd, with period td, used in most of the relevant processes. Module A2 applies simple logic to generate a synchronous system reset signal rst from the state of the corresponding PBS. Module A3 samples at low frequency the value of the signals generated by the other two PBS and A4 generates a pulse of length td in the output signal whenever a rising edge occurs in the corresponding input signal. Finally, modules A5 and A6 are in charge of generating the required signals to show in three seven-segment displays the code and stored value (more significant hexadecimal digit (MSD) and less significant hexadecimal digit (LSD)) of a given system parameter, determined by the position of the slide switches.

Module M1 updates the registered value of a given system parameter, defined by the 10 SdS, whenever the data

validation PBS is pressed. The values are expressed and stored in the units indicated within brackets in the block output signals. Parameter limits and coherence are checked. Before proceeding to store a new value, it is first verified that

fo[5 Hz]·ts[4tb]·tb[2td]·td[tck] 50,000 (7)to guarantee a minimum of 25 switching cycles per line cycle. It is also verified that m* hbc·m*

maxII. On the other hand, two additional parameters are calculated as

ts[8td]= ts[4tb]·tb[2td] ∆*[au]= 9·fo[5 Hz]·ts[4tb]·tb[2td]·td[tck],

(8)

where ∆* is the increment of * corresponding to one switching cycle.

Module M2 updates the value of *1 according to ∆* as

close as possible to the end of the switching cycle, and generates a set of signals (cntts_0..cntts_4) to control the timing of the PWM variable value updates, as indicated in Fig. 6.

Modules M3 and M4 are read-only memories (ROM) plus a little logic that determine the operating mode (UM, OMI, or OMII), the characteristic angle lim in the OM (crossover or holding angle), and parameters km1 and km2 defining the applied instantaneous modulation index in the OM. M3 outputs are constant for constant m* and hbc, while the M4 output changes every switching cycle. M3 requires a capacity of 512 x 32 bits and it is implemented with two 9 Kb memory blocks. M4 requires a capacity of 4,096 x 9 bits and is implemented with four 9 Kb memory blocks.

clk50M

Clktd Generator

Reset Generator

[PBS] rst rst

clktd

25 Hz Pushbutton Sampling

rdata_val ronoff

Edge Detector & Synchronization

edata_val

eonoff

Parameter Update

On-Off State Machine

[PBS] onoff [PBS] data_val

td [tck]tb [2td] = tbh [td] ts [4tb]

fo [5 Hz] hbc [0.01] m* [0.01]

Selector

system_state

*[au]

ts[8td]

[SdS] data Param_code

Param_MSD

0x to 7s

0x to 7s 0x to 7s

code_7s

MSD_7s

LSD_7s

mode

lim

km1

Logic + ROM Operating mode, lim, km1

*1 Update

& Timing Control

*1

sexta sextb sextc cntts_2 cntts_3 cntts_4

ROM km2

Selector

1

m

m·ts

ROM kt/100

ROM kt/100

t [td]

t [td]

Leg Switch-

Control-Signal Generator

sanij

Logic

t [td] Modification

tm

tm2

tm

tm

tm1

Param_LSD

10

k m2

sapij

6

6

sbnij

sbpij

6

6

scnij

scpij

6

6

Leg Switch-Control-Signal

Generator

Leg Switch-Control-Signal

Generator

t [td]

A2

A3 A4

A1

M3

M2

A6

A6

A6

M1

M4

A5

M5

M7

M6

M8

M9

M10

M10

M10

M11

Fig. 5. FPGA-controller global structure.

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nlycntts_0

cntts_1

cntts_2

cntts_3

cntts_4

clktd

8·ts1 cntts 0 1 2 3 4 3+tbh

*

End of t4 or t3;

ti update

t4_0 update

*1

update ROM

addresses update

4+tbh 3+2·tbh

End of ts

Start of t4 or t3

tbh tbh

4+2·tbh

t1_0 update

Fig. 6. Timing of events before the beginning of a new switching cycle.

Based on the values of mode and lim, M5 selects the proper values of m and 1 among the three possible. After this, and with the aid of multipliers and ROM modules M6 and M7, the value of tα and tβ, expressed in td units with 15 bits, are obtained. Through simple algebraic operations M8 computes t and t. Then, M9 modifies this set of time values so as to verify (6). The criteria followed to perform this modification are to maintain, whenever possible, the produced switching-cycle-averaged leg output-terminal voltage vo1, and to reduce the number of switching transitions. A robust modification requires a detailed analysis of the multiple possible cases and generates two possible modified values of t: tm1 for sextants 2 and 5 in Table I, and tm2 for the rest. M6 requires a capacity of 8,192 x 12 bits and is implemented with twelve 9 Kb memory blocks. Considering offsets and symmetries (see Fig. 4), M7 requires a capacity of 4,096 x 9 bits and is implemented with four 9 Kb memory blocks.

From the above information, M10 is in charge of generating the 12 switch control signals for one leg. Fig. 7 presents the internal block diagram of M10. Module M10A is in charge of updating and storing the t1, t2, t3, and t4 values for the next switching cycle (refer to Fig. 2) at the time defined in Fig. 6, and according to Table I. Two more bits are generated, t1_0 and t4_0, which indicate whether t1 and t4 are equal to zero, respectively. These values are updated as indicated in Fig. 6. All this information is fed to M10B, which contains a state machine in charge of determining the leg switching state, presented in Fig. 8. The name of the 27 states in Fig. 8 is defined with reference to the switching state of connection of the leg output terminal to the jth input terminal ssj. The state is further identified by the output values of the 10 independent switch control signals sn11-(sp11=sp12)-sp13-sn21-sn22-sp21-sp22-(sn31=sn32)-sn33-sp31 (in red) and two additional bits (black) to differentiate states with the same switch control signal values. It is interesting to note that the transition from one switching cycle to the next must be handled properly in accordance to the t4_0 value of the old and new switching cycles (there are four different transitions). The module output switching_state defined by the 10 red bits is then fed to M10C, which generates the 12 switch control signals and masks the values of some switch control signals during the global system turn-on and turn-off transitions, to avoid a possible switch overvoltage during these transients [43].

ti Memory

snij

spij

system_state

sextantcntts_2cntts_3cntts_4

tm

tbh

tmtm1

tm2tm

clktd

t1 t2 t3 t4

t1_0 t4_0

Switching-State Distribution

State Machine switching_state

Switch Control Signal

Masking

M10A M10B

M10C

Fig. 7. Leg switch-control-signal generator module structure.

The global on-off state of the system is controlled by the state machine of M11, presented in Fig. 9. The red bits in each state define the system_state output of M11. They represent, from left to right and with reference to Fig. 1(a), the masking bit for the switches in pole 3 (this bit is also the td counter enable in M10B), the masking bit for pole 2, the masking bit for pole 1, and the counter cntts enable in M2. In the transition from OFF to ON states, first pole 1 is enabled, then pole 2 is enabled, and finally pole 3 is enabled. This sequence of events is reversed in the transition from ON to OFF.

C. Consumed FPGA Resources An special effort has been made in the design to save

FPGA resources. Table III indicates the resources used to synthesize the previous controller, as reported by Quartus II software. These resources represent roughly around 20% of the total FPGA resources, leaving enough space to implement a full closed-loop converter controller, including the closed-loop control of the dc-link capacitor voltages and three-phase currents. A reduced number of resources will be necessary if a fixed value of Table II parameters is assumed, which is typically the case in practical applications.

IV. SIMULATION AND EXPERIMENTAL RESULTS

The previous FPGA-based control has been tested with a three-phase dc-ac converter configuration feeding a three-phase series R-L load, as shown in Fig. 1(b). The converter prototype with the DE0 board on top, containing the Altera Cyclone III EP3C16F484C6 FPGA, is presented in Fig. 10.

Fig. 11 presents the experimental switch control signals and output voltage of one leg, which follows the pattern described in Fig. 2. Note that the analog vo1 voltage waveform is delayed with reference to the digital switch control signals due to gate driver and measurement delays. Since the converter is non-ideal and it is operating in open-loop, there is some unbalance among the capacitor voltages that could be easily corrected with the introduction of a closed-loop control [44].

Figs. 12 and 13 present simulation and experimental results at different modulation indexes, covering the UM and OM ranges. Matlab-Simulink is used to perform the simulations. The obtained experimental results fairly match those from simulation, verifying the accurate performance of the programmed controller.

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ss2 to ss3 A 011010011001

Δt = t2-2·tbh

Δt = 2·tbh-2

Δt = 1

Δt = 1 & cntts_4

Second ss4 011001100101

ss3 to ss4 A 011001101001

Second ss3 011001111001

Δt = 1

Δt = t3-2·tbh & (cntts_3 & t4_0)'

Δt = t3-2·tbh & (cntts_3 & t4_0)

ss3 to ss4 B 011001100001

Δt = 2·tbh-1

Δt = 1 & (cntts_4)'

First ss4

011001100100

ss4 to ss3 A 011001100000

ss4 to ss3 B 011001101000

First ss3

011001111000

Δt = t4-2·tbh Δt = 2·tbh-1

system_state = OFF & t4_0

Δt = 1

Δt = 2·tbh

New ts

Initial State 000000000000

ss4 to ss3

011001100010

ss4 to ss4

011001100111

ss3 to ss4

011001100011

ss3 to ss3

011001111011

Δt = 2·tbh-1

Δt = 2·tbh

rst

ss3 to ss2 A 011000111000

ss3 to ss2 B 011000011000

Δt = t3-2·tbh

Δt = 1

Δt = 2·tbh

ss3 to ss2 C 011010011000

Δt = 1 First ss2

011110011000

Second ss2 011110011001

Δt = 1

ss2 to ss2

011110011011

ss2 to ss1 B 000110011000

ss2 to ss1 A 001110011000

ss1 to ss2 A 000110011001

ss1 to ss2 B 001110011001

Δt = 1

ss1

100110011000

Δt = 2·tbh-1

Δt = 2·tbh-2

ss2 to ss3 B 011000011001

ss2 to ss3 C 011000111001

system_state = OFF & (t4_0)'

Δt = 2·tbh

Δt = t2-2·tbh & (t1_0)'

Δt = t2-2·tbh & t1_0 Δt =2·tbh-1

Δt = 2·t1-2·tbh

Δt = t4-2·tbh & (t4_0)'

Δt = t4-2·tbh & t4_0

Fig. 8. Switching-state distribution finite state machine.

OFF

00000

Pole 1 ON & Wait 00100

Pole 3 OFF

01110

Pole 2 OFF

00110

Pole 1 ON & Count 00101

Pole 2 ON

01101

ON 11101

fonoff & (tbh ≠ 2) Δt = 2·(tbh–2)

fonoff & (tbh = 2)

Δt = 4

fonoff

Δt = 2·tbh

Δt = 2·tbh

Δt = 2·tbh

rst

Fig. 9. System on-off finite state machine.

TABLE III CONSUMED FPGA RESOURCES

Resource Amount Used / Total Available

Logic elements 2,466 / 15,408 (16%) Combinational functions 2,465 / 15,408 (16%) Dedicated logic registers 355 / 15,408 (2%) Pins 72 / 347 (21%) Memory bits 170,730 / 516,096 (33%) Embedded Multiplier 9-bit elements 21 / 112 (19%) PLLs 0 / 4 (0%)

Fig. 10. Experimental prototype combining DE0 development and educational board with a four-level three-phase dc-ac converter prototype using 100 V breakdown voltage metal-oxide-semiconductor field-effect transistors.

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vo1

sn11 sp11 sp12 sp13 sn21 sn22 sp21 sp22 sn31 sn32 sn33 sp31

Fig. 11. Experimental leg output terminal voltage vo1 and switch control signals. Conditions: Vdc = 150 V, fo= 50 Hz, m* = 0.8, td=100 ns, tb = 600 ns, ts = 19.2 µs (fs 52 kHz).

V. CONCLUSION

A full FPGA-based controller implementation is concluded to be the best choice to enable the practical use of multilevel active clamped converters and take full advantage of their potential benefits at a reasonable cost. A suitable PWM to operate a four-level three-phase dc-ac active-clamped converter featuring 36 switching devices with independent gate control signals has been efficiently and robustly implemented into a medium performance FPGA, consuming only a limited amount of resources. The remaining FPGA resources can be employed to implement typical closed-loop controls for different applications with a high dynamic performance, and also dynamically reconfiguring the control in runtime, which can be useful, for instance, in implementing fault-tolerant controls [45].

0 5 10 15 20-200

0

200

0 10 20 30 40 500

20

40

0 5 10 15 20-10

0

10

t [ms]

v ab

[V]

i a, i

b, i c

[A

]

ib ia ic

v ab

[Vrm

s]

f [kHz]

t [ms]

80 Vrms

0 5 10 15 20-200

0

200

0 10 20 30 40 500

20

40

0 5 10 15 20-10

0

10

t [ms]

v ab

[V]

i a, i

b, i c

[A

]

ib ia ic

v ab

[Vrm

s]

f [kHz]

t [ms]

106 Vrms

0 5 10 15 20-200

0

200

0 10 20 30 40 500

20

40

0 5 10 15 20-10

0

10

t [ms] v a

b [V

] i a

, ib,

i c [

A] ib ia ic

v ab

[Vrm

s]

f [kHz]

t [ms]

111 Vrms

(a) (b) (c) Fig. 12. Simulation results of the line-to-line output voltage vab, fast Fourier transform (FFT) of vab, and phase currents ia, ib, and ic. Conditions: hbc = 0.98, fo=

50 Hz, fs = 10 kHz, td=100 ns, tb = 1 µs, Vdc = 150 V, C = 155 F, RL = 16.5 , LL = 10 mH. (a) UM, m* = 0.75. (b) OMI, m* = 1.0. (c) OMII, m* = 1.05.

ia ib ic

vab

vab

ia ib ic

vab

vab

ia ib ic

vab

vab

(a) (b) (c) Fig. 13. Experimental results of vab, FFT of vab, ia, ib, and ic. Same conditions as in Fig. 11. (a) UM, m* = 0.75. (b) OMI, m* = 1.0. (c) OMII, m* = 1.05.

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