1

THE FUTURE PROGRAMMABLE IC

FPGA & IT’S ARCHITECTUREFPGA & IT’S ARCHITECTURE

2

Field-Programmable Devices.

Types of Field-Programmable Devices.

The Evolution Of FPGA.

Types of FPGA.

FPGA ARCHITECTURE (XILINX SPARTAN-II).

OUTLAY

3

A Field-Programmable device is a programmable IC.

Unlike traditional application-specific integrated

circuit (ASIC), function is specified by the user

after the device is manufactured.

It can be programmed by users to implement circuit

designs at their own sites.

Instant manufacturing (in minutes) at users’ site.

Field-Programmable Logic Devices

4

CPLDs

FPGAs

Types of Field-Programmable Logic Devices

SPLDs

Simple Programmable Logic Devices

Complex Programmable Logic Devices

Field-Programmable Gate Arrays

5

Simple Programmable Logic Devices(SPLD)

An SPLD is a lot of gates with interconnects thatcan be programmed to form desired logic functions.

There are two basic types of SPLDs:

The PLA : Programmable Logic Array

The PAL : Programmable Array Logic

6

Programmable Logic Array ( PLA )

The PLA has both a programmable AND array & a programmable OR array.

7

Programmable Array Logic ( PAL )

The PAL has a programmable AND array with a fixed OR array

8

Complex Programmable Logic Devices(CPLD)

An CPLD is formed by joining of two or more SPLDs on a single IC using an interconnect.

9

FPGA

Field-Programmable Gate Array Evolution

Introduced in 1985 by Xilinx.

Consists of an two-dimensional array of programmable logic blocks.

10

FPGA = FP + GA

Field Programmable means that the FPGA’sfunction is defined by the user’s program rather than by the manufacturer of the device.

Gate Array means it consists of an array of gates which can be connected according to the requirements of the logic to be implemented.

11

Field-Programmable Gate Array (FPGA)

An array of programmable logic blocks connected with programmable interconnects.A device in which the logic structure can be directly configured by the end user without the use of an IC fabrication facility. A device who's function is specified by the user after the device is manufactured.FPGAs can have medium-to-high capacity(equivalent to that of thousands to millions of logic gates).Speed: up to 200MHz or more.

12

Types of FPGA

Broadly we can divide FPGAs into three types: 1. Antifuse FPGA

2. Flash FPGA

3. SRAM FPGA

13

Antifuse FPGA

Devices are configured by burning a set of fuses.

Once the chip is configured, it cannot be altered

any more.

Hence only one-time programmable.

Its logic cells are made up of conventional logic gates.Used for ASIC replacement for small volumes.

14

Antifuse FPGA

How to make a permanent short connection ?

15

Flash FPGA

Devices may be re-programmed several thousand

times and are non-volatile, i.e. keep their

configuration after power-off.

With only marginal additional effort, the chips

may be updated in the field.

Re-configuration takes several seconds.

16

Static RAM FPGACurrently the dominating technology.

Unlimited re-programming.

Additional circuitry is required to load the

configuration into the FPGA after power on.

Re-configuration is very fast, some devices

allow even partial re-configuration during

operation.

Allows new approaches & applications

like , “Reconfigurable Computing”.

17

FPGA ARCHITECTURE

ARCHITECTURE of XILINX SPARTAN-II FPGAs

18

Basic Spartan-II Block Diagram

19

Structure of a FPGA

20

Configurable Logic Block (CLB)

Programmable Interconnection Network

Programmable Input / Output Block(IOB)

FPGA Architecture Building Blocks

21

Configurable Logic Block (CLB)

–Logic Cell (LC). –Look-Up Tables (LUTs)–Multiplexers–Flip-flops and latches

The basic building block of the CLBs is the logic cell(LC).

Each CLB contains four LCs, organized in two similar slices.Each slice contains two LCs .

Configurable Logic Block (CLB)

22

Logic Cell (LC)

An LC includes a 4-input function generator(Look-Up Table), carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop.

23

Look-Up Table

Any functions of up to ‘K’ variables can be implemented by

a single K-input LUT.

The function generators are implemented as 4-input look-up tables (LUTs) in XILINX SPARTAN-II FPGAs.

Each LUT can provide a 16x1-bit synchronous RAM.

The two LUTs within a slice can be combined to create a 16x2-bit or 32x1-bit synchronous RAM.

24

Look-Up Table Implementation

Example : 2 - LUT Example : 4 - LUT

25

26

Additional Logic

Storage Element : Either edge-triggered D-type flip-flop

or level-sensitive latch.

SR : Synchronous Set/Reset signal.It

forces FF into it’s initialize state as

specified in the configuration.

BX / BY : Forces to opposite state.

G1-4 / F1-4 : Inputs of the LUT.

CE : Clock enable signal.

CLK : Clock signal.

27

Additional LogicF5 Multiplexer : It combines the function generator

o/p.Used to implement 5 i/p function &

select function up to 9 inputs.

F6 Multiplexer : Used to implement 6 i/p function or

8:1 Mux. Select function up to 19 I/p

can be implemented.

CIN : Carry i/p is present in each slice.

XOR Gate : Allows 1-bit full adder implementation.

AND Gate : Improves efficiency of multiplier

implementation .

28

Usage of F5 and F6 Multiplexer

29

Programmable Interconnection Network

Programmable Interconnection Network

–Switch matrices

–Line segments

30

Programmable Interconnection Network

31

Programmable Interconnection Point (PIP)

Two types of PIPs in each switch matrix

Buffered PIP

Pass transistor + buffer

Connected to longer wires

Faster

Unbuffered PIP

Only pass transistor

Connected to shorter wires

Less area

32

Line Segments•Connectable Pair (A,B)

–PIP between them in FPGA

•Non-connectable Pair (C,D)

–No PIP between them

33

Programmable Interconnection PointNot every pair connectable. e.g. no PIP between (N1,S3)

34

Programmable Input/Output Block (IOB)

– Input/Output Pads– Input Path Logic – Output Path Logic

Programmable Input / Output Block

35

Input/Output Block (IOB)

36

Input/Output Block (IOB)IOB Register(T,O,I) : Either edge-triggered D-type flip

flop or level-sensitive latch.

CLK : Each IOB has clock signal shared

by the three registers.

CE : Each register have a independent

clock enable signal.

SR : Synchronous Set/Reset signal.It

forces FF into it’s initialize state

as specified in the configuration.

37

Input/Output Block (IOB)

Input Path : A buffer in i/p path routes the i/p signal

either directly or through optional flip-flop

to internal logic.

Output Path : The output path includes a 3-state output.

buffer that drives the output signal onto

the pad. The output high voltage depends

on an externally supplied Vcco voltage.

(The optional delay element at the D i/p of flip-flop

eliminates pad-to-pad hold time)

38

References•www.xilinx.com

•http://www.em.informatik.uni-frankfurt.de/

•http://crc.stanford.edu

•Logic and Computer Design Fundamentals, 2nd ed., Sections 6.5-6.9.

• Programmable Logic Design: Quick Start Handbook, p.1-8.

•Physical Design for FPGAs Rajeev Jayaraman

• FPGAs become a mainstream ASIC alternative

Shelly Davis, Xilinx Portable Design Magazine ,July 19, 2001

• The Spartan-II Family - The Complete Package

Xilinx, Inc January 10, 2000Xilinx, Inc,March 9, 2000

•Field Programmable Gate Arrays,

Product Specification ,Xilinx, IncMay 14, 1999

39

THANKS