FPGA Implementation of Reversible Vedic Multiplier · reversible Vedic multiplier using Urdhva...

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 13, Number 11 (2018) pp. 9988-9998

© Research India Publications. http://www.ripublication.com

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FPGA Implementation of Reversible Vedic Multiplier

Gowthami P1,*, Dr. R. V. S. Satyanarayana2

1Research scholar, 2Professor Department of Electronics & Communication Engineering,

SVUCE, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.

*Corresponding Author’

ABSTRACT

A Multiplier is a one of the arithmetic circuit which plays a

major role in many computational systems. These systems

speed greatly depends on the speed of its multiplier units and

it is the primary responsibility of power consumption in the

system. In this work, delay and power of the proposed

reversible Vedic multiplier using Urdhva Tiryakbhayam sutra

are calculated and compared with existing reversible and

conventional logic Urdhva Tiryakbhayam multiplier.

Keywords: Multipliers, Urdhva Tiryakbhayam, Reversible

logic.

INTRODUCTION

In between 1911 and 1918 the Swami Sri Bharati Krsna

Tirthaji rediscovered the Vedic mathematics in his research he

implemented sixteen sutras (formulae) and Upa sutras

(subformulae). Vedic Mathematics is an ancient system of

Mathematics. Among them, the Urdhva Tiryakbhayam (UT)

is one of the multiplication sutra which is capable of

minimizing the number of steps involved in multiplication

process. In Sanskrit, words Urdhva and Tiryakbhayam mean

vertically and crosswise respectively [1].

The Urdhva Tiryakbhayam algorithm is applicable for all

types of numerical formats which include Hexadecimal,

Decimal and Binary etc. The concept behind this formula is

that partial product generation can be done and then the

concurrent addition of these partial products is carried out

which leads to the reduction in the computational time.

Multipliers are essential for DSP system to perform operations

such as Convolution, Discrete Wavelet Transform, Fast

Fourier Transform, and Filtering etc [2]. The system speed is

determined by the multiplier unit. In order to enhance the

speed of the systems the faster and efficient multipliers should

be employed. This is one of the suitable places for the use of

Vedic Multiplier which performs the faster multiplications by

removing the undesirable steps in multiplication process.

A multiplier basically consists of partial product generation

circuit and an adder circuit. The partial product generation

circuit generates partial products with the use of two operands

namely multiplier and a multiplicand by multiplying each

digit in multiplier with multiplicand and the addition of partial

products are performed using adder circuit to produce the final

product (result). While designing the multipliers, efficient

adders should be chosen to minimize the delay and power of

the multipliers.

In the recent years, reversible logic has gained an importance

due to lossless of information in various applications such as

Bioinformatics, quantum computing, molecular computing,

quantum dot cellular automata and DNA computing [3].

FUNDAMENTALS OF REVERSIBLE LOGIC

The researcher R. Landauer demonstrated that during

irreversible logic operations when each bit of information lost

results in KTln2 joules of energy dissipation regardless of the

underlying technology [4].

Where K = Boltzmann’s constant and

T = Temperature.

In 1973 C.H. Bennett proved that dissipation of KTln2 amount

of heat energy can be minimized or even avoided if the logic

operation is performed in a reversible manner [5]. The basic

reversible logic gates encountered during the design are listed

below:

Figure 1: CNOT GATE [6]

Figure 2: BVF GATE [7]

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Figure 3: PERES GATE [8]

Figure 4: RMUX1 GATE [9]

Figure 5: BME GATE [10, 11]

Figure 6: HNG GATE [12]

PROPOSED WORK

REVERSIBLE 2X2 URDHVA TIRYAKBHAYAM

MULTIPLIER

The Rakshith T.R and Rakshith Saligram proposed the

Reversible 2x2 Urdhva Tiryakbhayam multiplier design [13].

For the implementation of this design one Feynman Gate and

five Peres gates totally six reversible gates are utilized. The

drawback of the existing design is it does not take the Fan out

into consideration.

The proposed design for reversible 2x2 Urdhva Tiryakbhayam

multiplier is shown in Figure 7 which takes Fan out into

consideration [14]. This design makes use of totally five

Reversible gates. The reversible gates used in the

implementation of the proposed design are two BME, one

Peres, one BVF and one CNOT gate. A BME Gate is mainly

used for generation of partial products in the multiplication

process. With the help of BVF, the fan out problem is avoided

in the design. Peres gate is used as a half adder. CNOT gate is

required to copy the desired outputs and to perform EXOR operation. I0 and I1 are intermediate outputs which are needed

to avoid Fanout problem.

Figure 7: Proposed design of 2x2 Urdhva Tiryakbhayam

multiplier using Reversible Gates.


MULTIPLIER

In this work, the architecture of the irreversible Urdhav

Tiryakbhayam multiplier [15] was modified by replacing the

conventional logic modules with the corresponding reversible

modules.

The existing reversible 4x4 UT Multiplier was designed with

four reversible 2x2 UT Multipliers, two four bit reversible

ripple carry adders and one five bit reversible ripple carry

adder. This design drawback was it suffers from an improper

arrangement of adders [13].

The proposed reversible 2X2 Urdhva Tiryakbhayam (UT)

multiplier is used to implement the reversible 4X4 Urdhva

Tiryakbhayam (UT) multiplier. In this work [16], With the

use of four reversible 2x2 UT multipliers, two 4 bit reversible

ripple carry adders, two reversible half adders and one

reversible OR gate, the reversible 4X4 Urdhva Tiryakbhayam

(UT) multiplier is constructed which is as shown in Figure 8.

Figure 8: Architecture of Reversible 4x4 UT Multiplier.




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In Figure 8 the reversible 4X4 Urdhva Tiryakbhayam (UT)

multiplier consists of four reversible 2x2 UT multipliers

which take the combination of two 4 bit inputs a[3:0], b[3:0].

The LSB’s of the final result (y[1:0]) is obtained from the first

2x2 reversible UT multiplier whose inputs are b[1:0], a[1:0].

The outputs of the second (q1[3:0]) and third (q2[3:0]) 2x2

reversible UT multipliers are added using the upper 4-bit

reversible ripple carry adder. The sum (qa[3:0]) of upper

reversible ripple carry adder, the remaining output bits

(q0[3:2]) of first 2x2 reversible UT multiplier and output LSB

bits (q3[1:0]) of fourth 2x2 reversible UT multiplier are

applied as inputs to the lower 4 bit reversible ripple carry

adder. The sum outputs of lower adder serve as the second,

third, fourth and fifth bits of the final result (y[5:2]). The carry

bits C1 and C2 of the 4-bit reversible ripple carry adders are

given to the 2 input reversible OR gate. The remaining bits of

the final result (y[7:6]) is obtained by using one reversible OR

gate and two reversible half adder gates. In the

implementation of reversible ripple carry adders HNG gate is

used as a reversible full adder. Four HNG gates are used in the

construction of 4-bit reversible ripple carry adder as shown in

Figure 9 and when the third input of the Peres gate is zero

then the Peres gate works as a reversible half adder which is

as shown in Figure 10 and The RMUX1 gate can be used as

reversible OR gate when the second input is zero as shown in

Figure 11.

Figure 9. 4 Bit Reversible Ripple Carry Adder.

Figure 10. Reversible Half Adder.

Figure 11. Reversible OR Gate.


MULTIPLIER

With the use of four reversible 4x4 UT multipliers, two 8 bit

reversible ripple carry adders, four reversible half adders and

one reversible OR gate, the reversible 8X8 Urdhav

Tiryakbhayam multiplier was constructed which is as shown

in Figure 12. Eight HNG gates are used in the implementation

of 8-bit reversible ripple carry adder as shown in Figure 13.

In Figure 12 the reversible 8X8 Urdhva Tiryakbhayam (UT)

multiplier consists of four reversible 4x4 UT multipliers

which take the combination of two 8 bit inputs a[7:0], b[7:0].

The LSB’s of the final result (y[3:0]) is obtained from the first

4x4 reversible UT multiplier whose inputs are b[1:0], a[1:0].

The outputs of the second (q1[7:0]) and third (q2[7:0]) 4x4

reversible UT multipliers are added using the upper 8-bit

reversible ripple carry adder. The sum (qa[7:0]) of upper

reversible ripple carry adder, the remaining output bits

(q0[7:4]) of first 2x2 reversible UT multiplier and output LSB

bits (q3[3:0]) of fourth 2x2 reversible UT multiplier are

applied as inputs to the lower 8 bit reversible ripple carry

adder. The sum outputs of this adder serve as fourth to

eleventh bits of the final result (y[11:4]). The carry bits C1

and C2 of the reversible ripple carry adders are applied to the

2 input reversible OR gate. The remaining bits of the final

result (y[15:12]) is produced by using one reversible OR gate

and four reversible half adder gates.

Figure 12: Architecture of Reversible 4x4 UT Multiplier.




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Figure 13. 8 Bit Reversible Ripple Carry Adder.

RESULTS & COMPARISON

The proposed reversible UT multiplier designs are

functionally verified through a logic simulation process. To

perform simulation, test benches are created for presented

reversible UT multiplier designs. The Verilog HDL is used to

code the designs. The simulation is carried out using Isim

simulation tool of Xilinx 14.3 ISE. The FPGA implementation

of Proposed Reversible Urdhva Tiryakbhayam multipliers has

been performed on Virtex family device XC5VLX50T-

1FF1136 FPGA.

The simulation waveform of the proposed reversible 2x2

Urdhva Tiryakbhayam multiplier is shown in Figure 14.

Figure 15 shows the configuration of Proposed Reversible 2x2

Urdhva Tiryakbhayam multiplier bit file to the FPGA. The

Figure 16 to Figure 22 shows the Proposed Reversible 2x2

Urdhva Tiryakbhayam Multiplier outputs appeared on LEDs

(as a Greenlight) for different input combinations applied with

the help of Switches. The RTL schematic and Technology

schematic of proposed reversible 2x2 UT multipliers has been

shown in Figure 39 and Figure 40.

The simulation waveform of the Proposed Reversible 4x4

Urdhva Tiryakbhayam Multiplier is shown in Figure 23.




Urdhva Tiryakbhayam Multiplier outputs appeared on LEDs

(as a Greenlight) for different input combinations applied with

the help of Switches. The RTL Schematic and Technology

schematic of Proposed Reversible 4x4 Urdhva Tiryakbhayam

Multiplier is shown in Figure 41 and Figure 42.

The simulation waveform of the Proposed Reversible 8x8

Urdhva Tiryakbhayam Multiplier is shown in Figure 31.




Urdhva Tiryakbhayam Multiplier outputs which are in a

decimal format for different hexadecimal input combinations.

The RTL Schematic and Technology schematic of Proposed

Reversible 8x8 Urdhva Tiryakbhayam Multiplier is shown in

Figure 43 and Figure 44.

Figure 14: Simulation waveforms for Proposed Reversible 2x2 Urdhva Tiryakbhayam Multiplier.

Figure 15: Configuration of Proposed Reversible 2x2 Urdhva

Tiryakbhayam Multiplier bit file to FPGA.

Figure 16: Output of Proposed Reversible 2x2 Urdhva

Tiryakbhayam Multiplier for input combinations a = 01, b = 00.




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Tiryakbhayam Multiplier for input combinations a = 10, b = 11. Figure 22: Output of Proposed Reversible 2x2 Urdhva





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Figure 23. Simulation waveforms for Proposed Reversible 4x4 Urdhva Tiryakbhayam Multiplier.


Tiryakbhayam Multiplier bit file to FPGA. Figure 26: Output of Proposed Reversible 4x4 Urdhva

Tiryakbhayam Multiplier for input combinations a = 0011,

b = 0011.

Figure 25: Output of Proposed Reversible 4X4 Urdhva


b = 0011.



b = 1001.




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b = 1110.



b = 1101.

Figure 29: Output of Proposed Reversible 4x4 Urdhva Tiryakbhayam Multiplier

for input combinations a = 1111, b = 1111.

Figure 31: Simulation waveforms for Proposed Reversible 8x8 Urdhva Tiryakbhayam Multiplier.




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Tiryakbhayam Multiplier bit file to FPGA.


Tiryakbhayam Multiplier for input combinations a = 0F, b = 0E.


Tiryakbhayam Multiplier for input combinations a = 09, b = 0B.




Tiryakbhayam Multiplier for input combinations a = AF,

b = 32.


Tiryakbhayam Multiplier for input combinations a = FF, b = FF.




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Tiryakbhayam Multiplier for input combinations a = DC, b =

96.

Figure 39: RTL Schematic of Proposed 2x2 Urdhva

Tiryakbhayam Multiplier.

Figure 40: Technology schematic of Proposed 2x2 Urdhva







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Table 1 shows the comparison of delay and power between the

proposed 4-bit and 8-bit reversible Urdhva Tiryakbhayam

multiplier designs with the existing reversible designs and

conventional logic designs.

Table 1. Delay and Power Comparison of different bit size

Urdhva Tiryakbhayam Multipliers.

Parameters

Conventional logic

design

Existing design

[13]

Proposed

design

4 x 4 8 x 8 4 x 4 8 x 8 4 x 4 8 x 8

Delay (ns) 9.928 13.485 9.566 12.832 8.558 11.979

Power

(µw)

180 910 180 910 170 850


Tiryakbhayam multiplier.

CONCLUSION

This work presents an Urdhva Tiryakbhayam multiplier design

using reversible logic gates. The delay and power consumption

of the proposed 4x4 and 8x8 Urdhva Tiryakbhayam multiplier

designs are compared with the existing reversible and

conventional logic designs shown in Table 1. From this table,

the proposed designs parameters such as delay and power are

reduced than the existing reversible and conventional logic

designs.




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REFERENCES

[1] Jagadguru Swami Sri Bharati Krsna Tirthaji Maharaja,

1965, Vedic Mathematics, Motilal Banarsidass

Publishers, Delhi.

[2] Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo

Kim and Yong Beom Cho, 2008, “Multiplier design

based on ancient Indian Vedic Mathematics” IEEE

International SOC Design Conference, Vol. 2, pp. 65-

68.

[3] Himanshu Thapliyal and Nagarajan Ranganathan,

2009, “Design of Efficient Reversible Binary

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[4] Landauer, R., 1961, "Irreversibility and Heat

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[5] Bennett, C.H., 1973,"Logical reversibility of

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[6] Feynman, R., 1985, "Quantum Mechanical

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[7] Bhagyalakshmi, H. R., and Venkatesha, M. K.,

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[8] Peres, A., 1985,"Reversible Logic and Quantum

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[9] Morrison, M., Lewandowski, M., and Ranganthan,

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[11] Mahfuzzreza, Md., Rakibul Islam and Belayet Ali,

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[12] Haghparast, M., and Navi, K., 2008, "A Novel BCD

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[13] Rakshith, T.R., and Rakshith Saligram., 2013, “Design

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[14] Gowthami, P., and Satyanarayana, R.V.S., “Design of

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[15] Bathija, R.S., Meena, R.S., Sarkar, S., and Rajesh

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