FPGA Configuration
-
Upload
amirali-sharifian -
Category
Technology
-
view
952 -
download
2
Transcript of FPGA Configuration
![Page 1: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/1.jpg)
FPGA ConfigurationMajed Roohani
Amirali Sharifian
1
Spring-2013
![Page 2: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/2.jpg)
Introduction
What is configuration? Process for loading data into the FPGA
Configuration Data
Source
Configuration Data
SourceFPGAFPGA
ControlLogic
(optional)
ControlLogic
(optional)
2
![Page 3: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/3.jpg)
Introduction
When does configuration happen? On power-up
On demand
Why do FPGAs need to be configured? FPGA configuration memory is volatile
What do I need to know about FPGA configuration? What happens during configuration
How to set up various configuration modes and daisy-chains
How to troubleshoot problems
3
![Page 4: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/4.jpg)
FPGA Configuration Process
In order to understand the configuration process, you need to know a little about: Configuration modes Configuration pins
4
![Page 5: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/5.jpg)
Configuration Modes
Configuration modes define the specifics of how the FPGA will interact with: The data source
External control logic (if any)
Many configuration modes to choose from Serial modes (Master and Slave)
SelectMAP mode (Slave Parallel)
Boundary scan mode (Slave) - always available
Other Xilinx FPGA families have more configuration modes
5
![Page 6: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/6.jpg)
Configuration Modes
Configuration pins (M0, M1, M2))
Note:
6
![Page 7: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/7.jpg)
Configuration Modes:Serial Modes
Data is loaded 1 bit per CCLK
Master serial FPGA drives configuration clock
(CCLK)
FPGA provides all control logic
Slave serial External control logic required to
generate CCLK
Microprocessor
Xilinx serial download cable
Another FPGA
SerialData
SerialData FPGAFPGA
CCLK
Data
SerialData
SerialData FPGAFPGA
ControlLogic
ControlLogic
Data
CCLK
7
![Page 8: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/8.jpg)
Configuration Modes:SelectMAP Mode
CCLK is driven by external logic
Data is loaded 1 byte per CCLK
Byte-WideData
Byte-WideData FPGAFPGA
ControlLogic
ControlLogic
Data
CCLKControl Signals
Presentation Name 8
8
![Page 9: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/9.jpg)
Configuration Modes:Boundary Scan Mode
External control logic required
Control signals and data are presented on the boundary scan pins (TDI, TMS, TCK)
Data is loaded 1 bit per TCK
Always available (independently on M0,M1,M2)
SerialData
SerialData FPGAFPGA
ControlLogic
ControlLogic
Data
Control Signals
9
![Page 10: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/10.jpg)
Configuration Pins
Specific pins on the FPGA are used during configuration
Some pins act differently depending on configuration mode Example: CCLK is an output in some modes
and an input in others Some pins are only used in specific
configuration modes Example: CCLK is not used for Boundary
Scan mode
10
![Page 11: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/11.jpg)
Configuration Pin Descriptions
Mode Pins (M0, M1, M2) Input pins that select which configuration
mode is being used PROGRAM
Active low input that initiates configuration CCLK (Configuration Clock)
Input or output, depending on configuration mode
Frequency up to 10MHz (see Data Book for your device family)
DIN Serial input for configuration data
11
![Page 12: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/12.jpg)
Configuration Pin Descriptions
DOUT Output to next device in a daisy-chain Used in daisy-chains only
INIT Open-drain bi-directional pin Error and Power Stabilization Flag
DONE Open-drain bi-directional pin Indicates completion of configuration
process Other pins are used for specific configuration
modes (i.e. JTAG Pins)
12
![Page 13: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/13.jpg)
Configuration Process
Four major phases in the process:
Configuration memory clear
Initialization
Load configuration data
Start-up
13
Configuration Memory
Clear
Configuration Memory
Clear
Initialization
Initialization
Load Configurati
on Data
Load Configurati
on Data
Start-UpStart-Up
![Page 14: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/14.jpg)
Configuration Process Configuration Memory Clear Phase
2 Way to configure
Non-configuration I/O pins are disabled with optional pull-up resistors
INIT and DONE pins are driven low
FPGA memory is cleared PROGRAM is checked after each
memory pass
Proceed to initialization
14
Configuration at Power-Up
Vcc AND Vccnt High?
No
FPGADrives INIT and
DONE low
Configuration During User Operation
User PullsPROGRAM
low
Yes
Clear Configuration
Memory
User HoldingPROGRAM low?
Yes
Initialization
No
![Page 15: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/15.jpg)
Configuration Process:Initialization Phase
INIT pin is released INIT may be held low externally
to delay configuration
Mode pins are sampled Appropriate configuration pins
become active
Proceed to load configuration data
15Configuration
MemoryClear
Release INIT
INITHigh?
Yes
Sample Mode Pins
Load Configuration
Data
No
![Page 16: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/16.jpg)
Configuration Process:Load Configuration Data Phase
FPGA starts receiving data CRC is checked during the
data frames transmission If incorrect value received, INIT
is driven low and rest of data is ignored
If the CRC checks pass, proceed to start-up
16
Initialization
Load Data Frames
CRCCorrect?
Yes
Start-UP
NoPull INIT
Low
![Page 17: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/17.jpg)
Configuration Process:Start-up Phase
Transition phase from configuration to normal operation
Order of events is user programmable Accessed through software options
Default sequence is: DONE pin is released
All I/O pins become active
Global write enable released
Global reset released
FPGA is operational
17Load
ConfigurationData
ReleaseDONE
ActivateI/O Pins
ReleaseGWE
ReleaseGSR
FPGA is Operational
![Page 18: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/18.jpg)
Configuration Process:Start-up Phase
Default sequence is: DONE pin is released
All I/O pins become active
Global write enable released
Global reset released
Another useful sequence is “Sync to DONE” Useful for multiple FPGA configuration
(Daisy chain)
Configuration option
18
![Page 19: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/19.jpg)
Master Serial Mode
All mode pins tied low FPGA drives CCLK as an
output Data stream loaded 1 bit at
a time Use when data stream is
stored in a serial PROM
19
![Page 20: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/20.jpg)
Slave Serial Mode
All mode pins tied high
FPGA receives CCLK as an input
Data stream loaded 1 bit at a time
Use with the Xilinx serial download cable
20
![Page 21: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/21.jpg)
What Is a Daisy-Chain?
Multiple FPGAs connected in series for configuration Allows configuration of many devices from a single
data source
Minimal board traces
First device in the chain can be in master serial or slave serial mode
All other devices must be in slave serial mode
21
![Page 22: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/22.jpg)
Daisy-Chain Question
How do you think these FPGAs could be connected to form a Daisy-chain?
22
![Page 23: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/23.jpg)
Daisy-Chain Answer
Connect all PROGRAM, CCLK and DONE pins together
Connect each DOUT to the DIN of next device
Recommend connecting INIT pins, but not required
23
![Page 24: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/24.jpg)
Creating a Daisy-Chain
Connect PROGRAM pins Required so that all FPGAs will reprogram together
Connect CCLK pins Required so that all FPGAs are synchronized with each other
and with the configuration data
Connect DONE pins Required so that all FPGAs start-up together
Connect each DOUT to the DIN of next device Required to allow each FPGA to receive configuration data
Connect INIT pins Recommended to create a single error flag, but not required
24
![Page 25: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/25.jpg)
How a Daisy-Chain Works
First FPGA in the chain is configured first Keeps DOUT high until its configuration memory is full
Then data is passed to the next device in the chain
Start-up sequence occurs after all devices are configured FPGA devices pause after internally releasing DONE,
and continue when DONE externally goes high
25
![Page 26: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/26.jpg)
Xilinx In-System Programming Using anEmbedded Microcontroller
Use XAPP 058(v 4.1) Virtex® series Spartan® series CoolRunner® series XC9500 series Platform Flash PROM family XC18V00 family
30
![Page 27: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/27.jpg)
important benefits of in-system programmability
Reduces device handling costs and time to market Saves the expense of laying out new PC boards Allows remote maintenance, modification, and
testing Increases the life span and functionality of products Enables unique, customer-specific features
31
![Page 28: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/28.jpg)
Microcontroller and JTAG Chain Schematic
32
![Page 29: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/29.jpg)
XSVF File Generation Flow to Embedded System
33
![Page 30: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/30.jpg)
C-code and header files
lenval.c micro.c ports.c lenval.h micro.h ports.h
34
![Page 31: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/31.jpg)
Configuration PROM Programming File Creation Storage Flow
35
![Page 32: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/32.jpg)
CPLD Programming File Creation and Storage Flow
36
![Page 33: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/33.jpg)
FPGA Programming File Creation and Storage Flow
37
![Page 34: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/34.jpg)
Selected iMPACT Batch Command
38
![Page 35: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/35.jpg)
Using the iMPACT GUI to Create XSVF Files
39
![Page 36: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/36.jpg)
Write XSVF file to selected Device
40
![Page 37: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/37.jpg)
IMPACT batch command41
![Page 38: FPGA Configuration](https://reader036.fdocuments.in/reader036/viewer/2022081506/5585ba9cd8b42a5e5a8b4c6a/html5/thumbnails/38.jpg)
Summary
Field programmable devices are configured on power-up from an external data source
The phases of the configuration process are: Configuration memory clear
Initialization
Load configuration data
Start-up
Master serial and slave serial are the simplest configuration modes
42