FPGA Calculator Core
description
Transcript of FPGA Calculator Core
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FPGA Calculator Core
Project CharacterizationChen ZukermanLiran Moskovitch
Advisor : Moshe Porian
Duration: semesterialDecember 2011
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Contents• Intro• Project Overview • Project Goals • Requirements• Architecture• Micro Architecture• Testability & GUI• Schedule
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Intro• In many projects, there is a tradeoff between
hardware and software implementation.• Hardware benefits:
o Shorter computation timeo Lower power consumptiono Reduced physical sizeo Minimum resourceso Good parallel processing capability
• Software benefits:o Simple implementationo Reduced cost
In this project we will focus on hardware implementation
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Project Overview
GUI FPGA
Feedback
Result
Hardware implementation of calculator core :
• Positive integers
• Operands: ‘+’ , ’-’ , ’x’ , ’/ ’ , ‘^’ , ‘ { ‘ , ‘ } ‘
• Order of operations
• Manually acquisition Input via Matlab GUI
• Result display - LCD + debugging feedback
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Project Goals
• Hardware implementation using FPGA
• Programming FPGA using VHDL
• Implementation of Interactive GUI (MATLAB)
• Experiencing full systemic perspective
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Requirements• Hardware platform: Altera DE2 board - Cyclone
II FPGA
• Host communication via UART protocol
• Internal communication via Wishbone protocol
• Input - Data string to calculate
• Output 1 - The calculated result displayed on the
LCD
• Output 2 – Confirmation of the result (software)
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Architecture
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5x(6+2 2̂) =
GUI
50
50
Yes
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Data packet structure8 bits
SOP
Type
Address
Data Length
Data 0...
Data N-1
CRC
EOP
Header
Packet
Tail
Client address + R/WInner client address
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Result
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UART Protocol
start parity stop
8 bit word
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RX PATH
UART RX
Message decode to wishbone
master
Message Decoder
RAM
CRCRead_value
Read_enable
Data [7..0]
Data [7..0]
valid
error
Frame error
Frame _ok
type
length
address
UART_IN
WB
M1
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TX PATH
UART TX
Message encoder
CRC
RAM
Wishbone to
Message encoder
WBS 2
WB
M 3
Frame_finish
type
address
lenFrame_OK
Wishbone_data[7…0]
Write_enable
Wishbone_data[7..0]
crc
valid
busy
UART_OUT
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Calculator Core
wish
bo
ne
Result Reg
Op Table
DATA
Result to wishbone
wish
bo
ne
WB
M 2
WB
S 1
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Calculator Algorithm
5 x ( 6 + 2 ^ 2 ) (5 x ( 6 + 2 ^ 2 ) )
(5 x ( 6 + 4 )) ( 5 x 10 )50(
5
x
(
6
+
2
^
2
EOC
)
)
4
(
5
x
(
6
+
)
EOC
)
4
10
(
5
x
10
EOC
)
50
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Arithmetic Calculation Unit
DMUX
DMUX
/
+
-
^
xSelect op (3 bit)
Num1 (32 bit)
Num2 (32 bit)
ResMUX
Select op
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Operation Table
Select valueBinary code
(Lsb’s)Operation
- 11111111 (
- 11111110 )
000 11111101 ^
001 11111100 x
010 11111011 /
011 11111010 +
100 11111001 -
- 11111000 EOC
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LCD Core
Binary to Ascii
converter
RAM(digits in Ascii
code)
Result from
wishbone
Result to LCD
WB
S 3
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LCD
RSR/W’E
DB0DB1DB2DB3DB4DB5DB6DB7
DATA
Enable0 :Write
1:Read
Register Select
Resu
lt d
igits
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Wishbone & wishbone intercon
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Clock & Reset
PLL
Reset Block
Clk = 50 [MHz]
Reset_in
lock
Sys_reset
Sys_clk = 100 [MHz]
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ScheduleTasks Date #
Project Characterization & learning26.11.11 - 20.12.11 1Characterization presentation +
comments
Full characterization of all blocks 24.12.11 - 4.1.12 2
VHDL implementation of main blocks 5.1.12 – 4.2.12 3
Exams. Project paused 5.2.12 – 29.2.12 4
Continue VHDL implementation 1.3.12 – 20.3.12 5
Mid Presentation (optional due to Exams B) 22.3.12 6
Simulations & debug 25.3.12 – 5.4.12 7
Synthesis & building GUI 6.4.12 – 20.4.12 8
Integration and Lab testing 21.4 – 10.5.12 9
End of semester presentation 15.5.12 10