USN

M S RAMAIAH INSTITUTE OF TECHNOLOGY(AUTONOMOUS INSTITUTE, AFFILIATED TO VTU)

BANGALORE - 560 054SEMESTER END EXAMINATIONS - JUNE 2010

Course & Branch : M.Tech (Digital Electronics and Semester : IICommunication)

Subject : FPGA Based System Design Max. Marks : 100Subject Code : MDLEC03

M D LEC03M

Duration . 3 Hrs

Instructions to the Candidates:Answer any Five Full questions.

1. a) List the critical parameters considered when MOS devices are (05)designed.

b) Realize the switch level for the following (07)i) Unbuffered AND gateii) XOR Gate

c) Explain how 2-D FPGA fabric interconnects work. (08)

2. a) Explain the I/O circuit design for an FPGA platform. List some of (10)FPGAs applications.

b) Explain Xilinx's CLB architecture. (10)3. a) Explain delay model of a combinational network. How is reduction of (10)

critical path length done?b) Discuss how we can algorithmically optimize power. Explain how (10)

glitches add to power consumption with an example.

4. a) For the circuits given, what are the hazards that are generated and (10)how can they be removed.

CL

(i)

b) What are the different design styles for implementing FSMs? Give an (10)

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MDLEC03

5. a)

example.

Write a VHDL code for detection of: 1011. (10)b) List the various clocking rules. What is clock skewing? How should it (10)

6. a)

be compensated?

Discuss the different optimization problems in floor planning. (10)b) Write the VHDL code for 16-bit barrel shifter. Consider circular shifts (10)

7. a)

either left or right.

Explain the various design methodologies for implementing a design. (10)b) Which are the different encoding techniques used? With an example (10)

justify it.

8. Write short notes: (4x5=20)i) Fine vs coarse grained architectureii) Logic mapping in FPGAsiii) Partitioning for multi - FPGA systemiv) Novel architecture using FPGAs.

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