International Journal of Electronics and Computer Science Engineering 508

Available Online at www.ijecse.org ISSN: 2277-1956

ISSN-2277-1956/V1N2-508-513

FPGA based sigma –Delta analogue to digital converter design

P. A. Uchagaonkar 1, S. A. Shinde 2 V.V. Patil 3, R.K. Kamat 4 1,2,3 Department of Electronics, Shivaji University, Kolhapur-41600, India

Email-raj_kamat@yahoo.com

Abstract- This paper reports design and development of modified Sigma- Delta ADC realized in FPGA paradigm. The wide gain of this ADC makes it a potential candidate in data converter applications in wide ranging domains such as communication systems, instrumentation, precision measurement devices and many others wherein the high resolution precision converter is essential. The proposed architecture encompasses of mixed mode design in which few of the analog and up to 90% digital blocks have been realized on a single platform. The digital building blocks have been tested and implemented in Xilinx ISE with the help of MATLAB system generator tool and instantiated on Spartan 3e FPGA. System performance has been ascertained using the hardware co-simulation and further post verified on the Xilinx analyzer tool.

Keywords: ADC; sigma-delta; FPGA.

1. INTRODUCTION

The sigma delta conversion technique has been in existence for many years, however the recent technological advances now makes it further practicable and thus their use is now increasing than ever before. These type of converters are now increasingly finding its applications in various domains such as communications, consumer and professional audio, industrial weight scales, and precision measurement devices just to mention a few . The key feature of these converters is that they are the only low cost alternatives as compared to their counterparts without compromising both high dynamic range and flexibility especially when it comes to low bandwidth input signals [2].

The very notion of the Σ- ∆ ADC technologies is based on the ∆ which represents the difference while ∑ represents the summation. The Σ- ∆ ADC architecture had its origin in the early development phases of pulse code modulation (PCM) systems. In 1954 C.C. Cutler of Bell Labs filed a significant patent which introduced the principle of oversampling and noise shaping with the specific intent of achieving higher resolution. His objective was not specifically to design a Nyquist ADC, but to transmit the oversampled noise shaped signal without reducing the data rate. Thus Cutler's converter embodied all the concepts in a Σ- ∆ ADC with the exception of digital filtering and decimation which would have been too complex and costly at that time using vacuum tube technology.[1] Although the sigma-delta modulator was first introduced in 1962, it did not gain importance until recent developments in digital VLSI technologies which provide the practical means to implement the large digital signal processing circuitry. The increasing use of digital techniques in communication and audio application has also contributed to the recent interest in cost effective high precision A/D converters. Since the Σ−∆ A/D converters are based on digital filtering techniques, almost 90% of the die is implemented in digital circuitry which enhances the prospect of compatibility.[3]. Recently there are good numbers of research papers reported on the design aspects of the delta-Sigma type of ADC in different manners to attain the improvements such as reliability, speed and cost effectiveness.

The present paper reports the modified delta-sigma ADC based on the earlier reported versions in [4] and [5]. The main significance of the design is its dominant digital implementation i.e. up to 80% design has been realized using digital signal processing. This makes it a suitable implementation candidate in the FPGA paradigm The paper is organized into several section. At the beginning the recent advances pertaining to the Σ- ∆ ADC by the research community has been reviewed. This is followed by the description of our design and development of the DSP section in Matlab System Generator. The same is further explored in terms of the hardware co-simulation technique and realized in terms of the soft IP cores and analog building blocks. Finally the simulation and result of the implemented system have been presented.

2-Prior Art

Notable research work regarding the Σ−∆ technology has been recently reported by Sangil Park [3]. In [3] he has explained DSP56ADC16 based implementation which is proved to have superior performance of the converter

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FPGA based Sigma –Delta analogue to Digital Converter Design

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compared to the performance of more conventional implementations. Conventional high resolution A/D converters, such as SAR and flash type converters are operated at Nyquist rate in which the sampling frequency is approximately equal to twice the maximum frequency in the input signal, which often do not make use of high speed achieved with a scaled VLSI technology. On the other hand, Σ−∆ ADC converters has a high oversampling rate, high resolution can be achieved by the decimation process [3]. Another recent paper by Phuong Vu [8] explores the basic concept of oversampling technique using frequency analysis. As per [8] the ADC conversion with a quantization error of up to ½ LSB has a quantization noise. If the sampling ADC is less than perfect, and its noise is greater than its theoretical minimum quantization noise, then its effective resolution will be less than N-bits. Applying a digital low pass filter (LPF) to the output is removing the quantization noise without affecting the desired signal, therefore its performance is improved. With reference to the above mentioned bottlenecks we have accomplished a high resolution A / D conversion while relaxing the requirements for the input analog anti aliasing filters.

Further in context of these types of ADCs, the output data rate can be reduced lower than the original sampling rate of Kfs because the bandwidth of the digital LPF on the output. The slower data rate is achieved by a process called decimation by a factor of M. This process passes every Mth bit to the output, while discarding the remainder. The factor M can be any integer value, provided that the output data rate is greater than twice the signal bandwidth. No loss of information will result from the decimation process. Resolution can be improved with oversampling; however, it must oversample by a factor of 22N in order to obtain a increase in resolution of N-bits. All these details have been put forth in[6]. Reid Wender and David Ihme have presented an interesting application note on the design of 16 bit Sigma Delta Analog to Digital Converter [7]. In the above mentioned application note they have explored a new design techniques incorporated via-configurable array (VCA) technology to allow mixed signal IP such as Σ∆ converters to be created and further reused as soft-IP. The mixed signal designing consisting of an analog fully differential second order Σ∆ modulator followed by a digital decimation filter are worked out and such details have formed the basis of the present paper [7]. Another reference design given by the lattice semiconductor corporation targets the implementation of an simple sigma delta ADC in CPLD or FPGA [4]. This design implemented with few logic resources comprises of analog comparator, low-pass RC network, and sampling element, accumulate and decimate in addition to simple digital filter. The first stage of filter converts the bits stream from a 1-bit, high frequency data stream. Further the above mentioned design has special features of parameterized bit precision and adjustable sampling frequency. The second stage filter performs an arithmetic average function on the accumulate data thereby providing further decimation to the output frequency of the ADC as well as an anti-aliasing function. Thus the above mentioned papers have formed the basis of the present paper. In our paper the soft IP cores have been designed by the combination of Matlab system generator and the VHDL language and instantiated on Spartan 3E FPGA. The separate DSP filter blocks verified by the hardware co-simulation techniques and its integration to the rest of the system enhances the entire system performance which is tested test on the Chipscope Pro Analyzer. All such details have been discussed in the rest of the paper.

3. ∆ΣADC Design

The schematic diagram of the modified ∆Σ ADC architecture is shown in Fig.1 the circuit comprises of a mixed mode analog and digital modules. The output of the analog comparator has been interfaced to Spartan 3e FPGA through the J4 header and even the residual processing blocks are designed in Spartan 3e FPGA.

Figure 1: The schematic diagram of modified ∆Σ ADC

The analog comparator gives output a digital ‘1’ if the voltage from RC network is lower than the RC network. The Texas Instruments TLV2354 LinCMOS low voltage differential comparator is used for detecting the logic condition. The output of the differential comparator is sampled by the flip flop in order to generate the feedback mechanism of RC circuit for tracking the digital value of analog input frequency. The PCM input data thus obtained by sampling element is translated into 16 bit output stream at a lower sample rate by the Cascaded Integrated comb

IJECSE,Volume1,Number 2 P. A. Uchagaonkar et al.

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(CIC) filter. Principally CIC filter is an optimized class of FIR filter combined with an interpolator or decimator however in the present case it has been used as decimation for a sample rate reduction and also for averaging filter function. The high frequency noise has eliminated with the help of digital filter. Both the CIC filter and Digital filter have been designed by adopting the “Design at higher level of abstraction” methodology using the system generator tool of Xilinx. The system generator tool supports realization of such DSP functions in the FPGA paradigm. It also supports hardware co-simulation, making it possible to incorporate design running in an FPGA directly into a Simulink for post-simulation. The following section details the Soft IP core that comprises of a D flip flop and CIC as well as Digital filter DSP blocks implemented in Spartan 3e FPGA.

3.1 DESIGN of CIC and Digital FILTER

Simulink provides a graphical environment for creating and modeling dynamical systems. The filter has been designed using the Xilinx basic element library which includes the standard building blocks. The required blocks from a block set library are added in a model and specifications as per the design requirements have been selected.

The Xilinx CIC compiler provides the ability to design and implement Cascaded Integrated Comb Filters. The snapshot of the CIC filter design in matlab Simulink is shown in fig.2

Figure 2: Design of CIC Filter in matlab Simulink

The CIC filters are typically employed in applications that have a large excess sample rate i.e. in the systems exhibiting sample rate much larger than the bandwidth required. The block diagram of CIC compiler 2.0 is as shown in fig.3. After specifying all the desired filter specifications the simulation is seen to be on proper lines. After ascertaining the same the Xilinx ISE file is obtained. The VHDL core is generated for rest of the Xilinx blocks by placing the system generator token in Simulink project sheet. The system generator block parameters dialog block allows tailoring Simulink simulation and code generation. Figure 3 & Figure 4 represents the snapshots of generated HDL file of CIC filter and the RTL schematic view of this respectively.

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FPGA based Sigma –Delta analogue to Digital Converter Design

ISSN-2277-1956/V1N2-508-513

Figure 3: Generated HDL file of CIC Filter

Figure 4: RTL-Schematic of CIC Filter

The simulation result of CIC filter is checked on the matlab simulation view and also by the hardware co-simulation technique. It allows the FPGA board to receive data inputs from the host, further process it and then return the outputs to the host for analysis. By changing the parameters of system generator block, the JTAG block is generated for the hardware co-simulation. After linking the proper connection of source and sink for JTAG as per the Fig.2, the obtained hardware co-simulation and matlab simulation view is shown in Fig.5 and Fig. 6 respectively.

Figure 5 :- Hardware Co-simulation View and MATLAB Simulation view

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The digital filter has also been designed on the similar lines as that of CIC filter. In the design of digital filters the FIR compiler 5.0 has been used in addition to Filter Design Tool (FDA) as evident from the fig 8 and fig.9. FIR compiler 5.0 has been used to implement a multiply accumulate kind of architecture based and thus it is in a way distributed arithmetic FIR filter. It accepts a stream of input data and computes filtered output with a fixed delay, based on the filter configuration. The FDA block also provides a means of defining an FDA Tool Object and storing it as part of a System generator model. Thus the FDA provides a powerful means for defining digital filters with a graphical user interface. Fig 10 shows the Matlab Simulink window for digital filter system.

Figure 10: Design of Digital Filter in Matlab Simulink

The RTL schematic and simulation view of digital filter is revealed in fig. 11 and fig. 12 respectively

Figure 11: RTL-Schematic of Digital Filter Figure 12: Simulation View of Digital Filters

The integration of the entire setup goes on the following lines. With reference to the modified architecture of the ADC dealt in depth in above sections, the control logic is created by combining the d flip flop, CIC filter and digital filter architectures which were generated separately. A to D Control Logic is instantiated through VHDL code simulated and synthesized in ISE 12.4. The RTL view of this shown in Fig. 13

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FPGA based Sigma –Delta analogue to Digital Converter Design

ISSN-2277-1956/V1N2-508-513

Figure 13: RTL-Schematic of A to D Control Logic as well as the Chipscope Pro Analyzer

3-RESULTS AND CONCLUSION

The functioning of the Σ−∆ ADC thus realized is verified using the Chipscope Pro Analyzer. The same has been coupled with the key analyzer and measurement hardware components with the target design on Xilinx Spartan 3e FPGA device. Fig. 13 shows the 16 bit digital output of Delta Sigma ADC on the chipscope analyzer which verifies our design. Work is in progress to integrate the modified Σ−∆ ADC designed by us for biomedical applications.

REFERENCES [1] Walt Kester, ADC Architectures III: Sigma-Delta ADC Basics, 10/08, WK Page 1 of 12 MT-022 TUTORIAL retrived from,

http://www.analog.com/static/imported-files/tutorials/MT-022.pdf

[2] Jesper Steensgaard-Madsen,”High-Performance Data Converters” Ph.D. thesis,The Technical University of Denmark, January 20, 1999

[3] Sangil Park, Ph. D. “Principles of Sigma-Delta Modulation for Analog-to-Digital Converters”, Motorola digital signal processors

[4] "Simple Sigma-Delta ADC." FPGA and CPLD Solutions from Lattice Semiconductor. Web. 27 Jan. 2012.http://www.latticesemi.com/products/intellectualproperty/referencedesigns/simplesigmadeltaadc.cfm

[5] “Leverging FPGA and CPLD based digital logic to implement analog to digital converters”, A Lattice Semiconductor White Paper, March 2010

[6] David Jarman, “A Brief Introduction to Sigma Delta Conversion”, Application Note, May 1995,AN9504. http://www.intersil.com/data/an/an9504.pdf

[7] Reid Wender, David Ihme,” 16-bit Sigma Delta ADC Design” Application note-TSA002, Triad semiconductor

[8] Phuong Vu, “Benefits of Sigma Delta ADC”, retrived from www.testedgeinc.com/docs/sigma_delta_adc.pdf

[9] "An Introduction to Delta Sigma Converters." Die Homepage Der Familie Beis. Web. 27 Jan. 2012. http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html

[10] Gagnon, G., and L. MacEachern. "Digital Compensation of DAC Mismatches in Multibit Delta-sigma ADCs." Electronics Letters 44.12 (2008): 721. Print.

[11] Fred harris, Chris Dick,“FPGA signal processing using sigma delta modulation”, USA

[12] Matthew P. Donadio, “ CIC Filter Introduction”, 18 July 2000 retrieved from http://www.amrad.org/projects/dsp/cic1.pdf

[13] Understanding CIC Compensation Filters, Altera Application Note 455, April 2007, ver. 1.0

[14] Spartan 3E FPGA Starter Kit Board User guide, Retrived from www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf

[15] System Generator for DSP System Guide retrived fromwww.xilinx.com/support/sw_manuals/sysgengs.pdf