International Journal of VLSI and Signal Processing Applications, Vol. 1, Issue 2 , May 2011,(38-41) ,ISSN 2231-3133

www.ijvspa.com

FPGA Based Area Efficient Edge Detection Filter for Image Processing

Applications

Rajesh Mehra1, Rachna B. Sardana

2, Rupinder Verma

3

1Faculty of ECE Department, NITTTR, Chandigarh, UT, India

2Faculty of ECE Department, TIT&S, Bhiwani, Haryana, India

3 ME Student, NITTTR, Chandigarh, UT, India

ABSTRACT

In this paper FPGA based efficient design of an

adaptive edge-detection filter for image

processing application has been presented. The

FPGA implementation provides the necessary

performance for real-time image and video

processing, while retaining the system flexibility

to support an adaptive algorithm. A fully parallel

fully pipelined MAC algorithm is used to

implement the proposed filter. This approach is

useful to enhance the system performance by

taking optimal advantage of embedded

Multipliers, BRAMs and Registers available on

target FPGA. The proposed 2D filter is designed

using Matlab and Xilinx DSP Tools, synthesized

with ISE 10.1 and implemented on Virtex-II Pro

based 2vp50ff1148-7 FPGA device. Results

show enhanced performance of proposed design

in terms of area utilization as compared to

standard optimal median filters

Key Words: BRAM, FPGA, ISE, MAC, Matlab

I. INTRODUCTION

Real-time video and image processing is used in

a wide variety of applications from video

surveillance and traffic management to medical

imaging applications. These operations often

require digital signal processing (DSP)

algorithms for several crucial operations [1]. Due

to a growing demand for such complex DSP

applications, high performance, low-cost Soc

implementations of DSP algorithms are

receiving increased attention among researchers

and design engineers. Although ASICs and DSP

chips have been the traditional solution for high

performance applications, now the technology

and the market demands are looking for changes.

On one hand, high development costs and time-

to-market factors associated with ASICs can be

prohibitive for certain applications while, on the

other hand, programmable DSP processors can

be unable to meet desired performance due to

their sequential-execution architecture [2]. In this

context, embedded FPGAs offer a very attractive

solution that balance high flexibility, time-to-

market, cost and performance. Therefore, in this

paper, an area and power efficient adaptive edge

detection filter is implemented on target

FPGA using multiply and accumulate (MAC)

technique. There is a constant requirement for

efficient use of FPGA resources where

occupying less hardware for a given system can

yield significant cost-related benefits like:

(i) Reduced power consumption;

(ii) Area for additional application functionality;

(iii) Potential to use a smaller, cheaper FPGA.

If very high sampling rates are required [3],

fully-parallel hardware must be used where

every clock edge feeds a new input sample and

produces a new output sample. In case fully

parallel implementation is not possible then

partly serial approach can be adopted to enhance

the system performance. The proposed design is

implemented in a fully parallel fully pipelined

style by taking optimal advantage of embedded

Multipliers, Block RAMs and Registers available

on target device. Fully-parallel design cannot

share hardware over multiple clock cycles and so

tend to occupy large amounts of resource. Hence,

efficient implementation of such filters is

important to minimize hardware requirement.

II. EDGE DETECTION FILTER

Edge detection is a fundamental tool used in

most image processing applications to obtain

information from the frames as a precursor step

to feature extraction and object segmentation.

This process detects outlines of an object and

International Journal of VLSI and Signal Processing Applications, Vol. 1, Issue 2 , May 2011,(38-41) ,ISSN 2231-3133

www.ijvspa.com

boundaries between objects and the background

in the image. An edge-detection filter can also be

used to improve the appearance of blurred or

anti-aliased video streams.

The basic edge-detection operator is a matrix

area gradient operation that determines the level

of variance between different pixels. The edge-

detection operator is calculated by forming a

matrix centered on a pixel chosen as the center of

the matrix area. If the value of this matrix area is

above a given threshold, then the middle pixel is

classified as an edge. Examples of gradient-

based edge detectors are Roberts, Prewitt, and

Sobel operators [4]-[8]. All the gradient-based

algorithms have kernel operators that calculate

the strength of the slope in directions which are

orthogonal to each other, commonly vertical and

horizontal. Later, the contributions of the

different components of the slopes are combined

to give the total value of the edge strength. The

Prewitt operator measures two components. The

vertical edge component is calculated with

kernel Kx and the horizontal edge component is

calculated with kernel Ky as shown in Fig.1. |Kx|

+ |Ky| gives an indication of the intensity of the

gradient in the current pixel.

Fig.1 Prewitt horizontal and vertical operators

Depending on the noise characteristics of the

image or streaming video, edge detection results

can vary. Gradient-based algorithms such as the

Prewitt filter have a major drawback of being

very sensitive to noise. The size of the kernel

filter and coefficients are fixed and cannot be

adapted to a given image. An adaptive edge-

detection algorithm is necessary to provide a

robust solution that is adaptable to the varying

noise levels of these images to help distinguish

valid image content from visual artifacts

introduced by noise [9].

III. MATLAB BASED DESIGN &

SIMULATION

This proposed edge detection design has been

developed using a 2-D Image filter as shown in

Fig.2. It can be realized efficiently using n-tap

MAC FIR Filters.

Fig.2 Proposed Edge Detection Model

Fig.3 Proposed Design Flow

The 5x5 size mask is used to implement the

filter. The 2-D filter coefficients are stored in a

block RAM and 5 MAC units are used to

implement the proposed design in fully parallel

and fully pipelined manner. The first step in

design flow is to design 5-tap FIR filter using

Simulink and System Generator as shown in

Fig.3. Then the optimized VHDL code is

developed and synthesized using ISE 10.1i and

implemented on Virtex target device. Fig.4

shows the original image and Fig.5 shows the

image filtered by the proposed edge detection

filter.

Fig.4 Original Image

Matlab Design

HDL Code

Synthesis

Implementation

International Journal of VLSI and Signal Processing Applications, Vol. 1, Issue 2 , May 2011,(38-41) ,ISSN 2231-3133

www.ijvspa.com

Fig.5 Filtered Image

IV. H/W IMPLEMENTATION

RESULTS

The architecture of fully parallel pipelined MAC

based design is shown in Fig.6. The MAC based

fully parallel implementation uses one multiplier

each to process all 5 coefficients in a single clock

and pipelined registers are used to enhance the

speed performance of the filter. The proposed

adaptive edge detection filter is implemented on

Virtex II Pro based 2vp50ff1148-7 target device.

Fig.6 Fully Parallel MAC Architecture

It can be observed from the timing summary

shown in Fig.7 that the proposed design can

operate at maximum frequency of 291MHz by

consuming 346 slices as compared to optimal

median filter maximum frequency of 305 MHz

by consuming 1506 slices [10].

The area utilization of the proposed design has

been shown in Table1 and its power

consumption has been shown in Table2

Fig.7 Speed Performance

Table1. Resource utilization on device

Table2. Power Consumption

The proposed design is using 9 embedded

BRAMS and 5 embedded multipliers of the

target device which results in considerable

reduction in used area in terms of number of

slices, flip-flops, LUTs etc. The power

consumption of the proposed design is 0.2686W

at 27.9°C.

V. CONCLUSIONS

In this paper, a fully parallel fully pipelined

MAC based approach is used to design an area

and power efficient adaptive edge detection for

real time video and image processing

applications. As Compared to adaptive median

filters, MAC based design show better result in

terms area utilization. The proposed design can

work at maximum operating frequency of 291

MHz which is nearly equal to median filter

design by consuming only one fourth slices of

the target device as compared to optimal median

filter design to provide a cost effective solution

for image processing applications. The power

consumption of the proposed design is 0.2686W

at 27.9°C.

International Journal of VLSI and Signal Processing Applications, Vol. 1, Issue 2 , May 2011,(38-41) ,ISSN 2231-3133

www.ijvspa.com

ACKNOWLEDGEMENT

The authors would like to thank Dr. S. Chatterji,

Professor and Head and Dr. Swapna Devi,

Associate Professor, Electronics &

Communication Engineering Department,

NITTTR, Chandigarh for constant

encouragement, and guidance during this

research work.

References

[1] D.J. Allred, H. Yoo, V. Krishnan, W. Huang, and

D. Anderson, “A Novel High Performance Distributed

Arithmetic Adaptive Filter Implementation on an

FPGA”, in Proc. IEEE Int. Conference on Acoustics,

Speech, and Signal Processing (ICASSP’04), Vol. 5,

pp. 161-164, 2004

[2] Patrick Longa and Ali Miri “Area-Efficient FIR

Filter Design on FPGAs using Distributed

Arithmetic”, pp248-252 IEEE International

Symposium on Signal Processing and Information

Technology, 2006.

[3] K.N. Macpherson and R.W. Stewart “Area

efficient FIR filters for high speed FPGA

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2006.

[4] Feng-ying Cui and Li-jun Zou, Bei Song,” Edge

Feature Extraction based on Digital image processing

Techniques” International Conference on Automation

and Logistics, pp. 2320-2324, IEEE 2008.

[5] Mohamed Nasir Bin Mohamed Shukor, Lo Hai

Hiung, Patrick Sebastian, “Implementation of Real

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operator and Genetic Algorithms”, International

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pp. 31-35, IEEE 2009.

[8] Yasri, N.H.Hamid, V.V.Yap, “Performance

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[9] S. A. Fahmy, P. Y. K. Cheung, and W. Luk,

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Authors:

Rajesh Mehra: Mr. Rajesh Mehra is currently

Assistant Professor at National Institute of Technical Teachers’ Training & Research, Chandigarh, India. He is

pursuing his PhD from Panjab University, Chandigarh,

India. He has completed his M.E. from NITTTR, Chandigarh, India and B.Tech. from NIT, Jalandhar, India. Mr. Mehra

has 15 years of academic experience. He has authored more

than 15 research papers in reputed International Journals and 35 research papers in National and International

conferences. Mr. Mehra’s interest areas are VLSI Design,

Embedded System Design, Advanced Digital Signal Processing, Wireless & Mobile Communication and Digital

System Design. Mr. Mehra is life member of ISTE.

Rachna Sardana: Ms. Rachna Sardana is currently Senior Lecturer at The Technological Institute of

Textile and Sciences,Bhiwani,India.She has completed her

M..E from NITTR, Chandigarh, India and B.Tech. from PREC, Pune, India. Ms. Rachna has 13 years of academic

experience. Ms. Rachna’s interest areas are Signal

Processing, Image Processing and VLSI Design.

Rupinder Verma: Ms. Rupinder Verma is pursuing Maters of Engineering from National Institute of

Technical Teachers Training & Research, Chandigarh. She

has done her Bachelors’ of Technology from Institute of Engineering and Technology, Bhaddal under Punjab

Technical University. She has more than three years of

Academic Experience and currently working on VLSI implementation of Edge Detector for various Image

Processing applications.